1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include "imx7d.dtsi" 8 9/ { 10 model = "Freescale i.MX7 SabreSD Board"; 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 13 chosen { 14 stdout-path = &uart1; 15 }; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio_keys>; 26 27 key-volume-up { 28 label = "Volume Up"; 29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 30 linux,code = <KEY_VOLUMEUP>; 31 wakeup-source; 32 }; 33 34 key-volume-down { 35 label = "Volume Down"; 36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 37 linux,code = <KEY_VOLUMEDOWN>; 38 wakeup-source; 39 }; 40 }; 41 42 spi-4 { 43 compatible = "spi-gpio"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_spi4>; 46 sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 47 mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 49 num-chipselects = <1>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 extended_io: gpio-expander@0 { 54 compatible = "fairchild,74hc595"; 55 gpio-controller; 56 #gpio-cells = <2>; 57 reg = <0>; 58 registers-number = <1>; 59 spi-max-frequency = <100000>; 60 }; 61 }; 62 63 reg_sd1_vmmc: regulator-sd1-vmmc { 64 compatible = "regulator-fixed"; 65 regulator-name = "VDD_SD1"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 startup-delay-us = <200000>; 71 off-on-delay-us = <20000>; 72 }; 73 74 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 75 compatible = "regulator-fixed"; 76 regulator-name = "usb_otg1_vbus"; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 84 compatible = "regulator-fixed"; 85 regulator-name = "usb_otg2_vbus"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_vref_1v8: regulator-vref-1v8 { 95 compatible = "regulator-fixed"; 96 regulator-name = "vref-1v8"; 97 regulator-min-microvolt = <1800000>; 98 regulator-max-microvolt = <1800000>; 99 }; 100 101 reg_brcm: regulator-brcm { 102 compatible = "regulator-fixed"; 103 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 104 enable-active-high; 105 regulator-name = "brcm_reg"; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_brcm_reg>; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 startup-delay-us = <200000>; 111 }; 112 113 reg_lcd_3v3: regulator-lcd-3v3 { 114 compatible = "regulator-fixed"; 115 regulator-name = "lcd-3v3"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 119 }; 120 121 reg_can2_3v3: regulator-can2-3v3 { 122 compatible = "regulator-fixed"; 123 regulator-name = "can2-3v3"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_flexcan2_reg>; 126 regulator-min-microvolt = <3300000>; 127 regulator-max-microvolt = <3300000>; 128 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 129 }; 130 131 reg_fec2_3v3: regulator-fec2-3v3 { 132 compatible = "regulator-fixed"; 133 regulator-name = "fec2-3v3"; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_enet2_reg>; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 139 }; 140 141 backlight: backlight { 142 compatible = "pwm-backlight"; 143 pwms = <&pwm1 0 5000000 0>; 144 brightness-levels = <0 4 8 16 32 64 128 255>; 145 default-brightness-level = <6>; 146 status = "okay"; 147 }; 148 149 panel { 150 compatible = "innolux,at043tn24"; 151 backlight = <&backlight>; 152 power-supply = <®_lcd_3v3>; 153 154 port { 155 panel_in: endpoint { 156 remote-endpoint = <&display_out>; 157 }; 158 }; 159 }; 160 161 sound { 162 compatible = "fsl,imx7d-evk-wm8960", 163 "fsl,imx-audio-wm8960"; 164 model = "wm8960-audio"; 165 audio-cpu = <&sai1>; 166 audio-codec = <&codec>; 167 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; 168 audio-routing = 169 "Headphone Jack", "HP_L", 170 "Headphone Jack", "HP_R", 171 "Ext Spk", "SPK_LP", 172 "Ext Spk", "SPK_LN", 173 "Ext Spk", "SPK_RP", 174 "Ext Spk", "SPK_RN", 175 "LINPUT1", "AMIC", 176 "AMIC", "MICB"; 177 }; 178 179 sound-hdmi { 180 compatible = "fsl,imx-audio-sii902x"; 181 model = "sii902x-audio"; 182 audio-cpu = <&sai3>; 183 hdmi-out; 184 }; 185}; 186 187&adc1 { 188 vref-supply = <®_vref_1v8>; 189 status = "okay"; 190}; 191 192&adc2 { 193 vref-supply = <®_vref_1v8>; 194 status = "okay"; 195}; 196 197&cpu0 { 198 cpu-supply = <&sw1a_reg>; 199}; 200 201&cpu1 { 202 cpu-supply = <&sw1a_reg>; 203}; 204 205&ecspi3 { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ecspi3>; 208 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 209 status = "okay"; 210 211 tsc2046@0 { 212 compatible = "ti,tsc2046"; 213 reg = <0>; 214 spi-max-frequency = <1000000>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 217 interrupt-parent = <&gpio2>; 218 interrupts = <29 0>; 219 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; 220 touchscreen-max-pressure = <255>; 221 wakeup-source; 222 }; 223}; 224 225&fec1 { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_enet1>; 228 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 229 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 230 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 231 assigned-clock-rates = <0>, <100000000>; 232 phy-mode = "rgmii"; 233 phy-handle = <ðphy0>; 234 fsl,magic-packet; 235 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 236 status = "okay"; 237 238 mdio { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 ethphy0: ethernet-phy@0 { 243 reg = <0>; 244 }; 245 246 ethphy1: ethernet-phy@1 { 247 reg = <1>; 248 }; 249 }; 250}; 251 252&fec2 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_enet2>; 255 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 256 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 257 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 258 assigned-clock-rates = <0>, <100000000>; 259 phy-mode = "rgmii"; 260 phy-handle = <ðphy1>; 261 phy-supply = <®_fec2_3v3>; 262 fsl,magic-packet; 263 status = "okay"; 264}; 265 266&flexcan2 { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_flexcan2>; 269 xceiver-supply = <®_can2_3v3>; 270 status = "okay"; 271}; 272 273&i2c1 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_i2c1>; 276 status = "okay"; 277 278 pmic: pmic@8 { 279 compatible = "fsl,pfuze3000"; 280 reg = <0x08>; 281 282 regulators { 283 sw1a_reg: sw1a { 284 regulator-min-microvolt = <700000>; 285 regulator-max-microvolt = <1475000>; 286 regulator-boot-on; 287 regulator-always-on; 288 regulator-ramp-delay = <6250>; 289 }; 290 291 /* use sw1c_reg to align with pfuze100/pfuze200 */ 292 sw1c_reg: sw1b { 293 regulator-min-microvolt = <700000>; 294 regulator-max-microvolt = <1475000>; 295 regulator-boot-on; 296 regulator-always-on; 297 regulator-ramp-delay = <6250>; 298 }; 299 300 sw2_reg: sw2 { 301 regulator-min-microvolt = <1800000>; 302 regulator-max-microvolt = <1800000>; 303 regulator-boot-on; 304 regulator-always-on; 305 }; 306 307 sw3a_reg: sw3 { 308 regulator-min-microvolt = <900000>; 309 regulator-max-microvolt = <1650000>; 310 regulator-boot-on; 311 regulator-always-on; 312 }; 313 314 swbst_reg: swbst { 315 regulator-min-microvolt = <5000000>; 316 regulator-max-microvolt = <5150000>; 317 }; 318 319 snvs_reg: vsnvs { 320 regulator-min-microvolt = <1000000>; 321 regulator-max-microvolt = <3000000>; 322 regulator-boot-on; 323 regulator-always-on; 324 }; 325 326 vref_reg: vrefddr { 327 regulator-boot-on; 328 regulator-always-on; 329 }; 330 331 vgen1_reg: vldo1 { 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <3300000>; 334 regulator-always-on; 335 }; 336 337 vgen2_reg: vldo2 { 338 regulator-min-microvolt = <800000>; 339 regulator-max-microvolt = <1550000>; 340 }; 341 342 vgen3_reg: vccsd { 343 regulator-min-microvolt = <2850000>; 344 regulator-max-microvolt = <3300000>; 345 regulator-always-on; 346 }; 347 348 vgen4_reg: v33 { 349 regulator-min-microvolt = <2850000>; 350 regulator-max-microvolt = <3300000>; 351 regulator-always-on; 352 }; 353 354 vgen5_reg: vldo3 { 355 regulator-min-microvolt = <1800000>; 356 regulator-max-microvolt = <3300000>; 357 regulator-always-on; 358 }; 359 360 vgen6_reg: vldo4 { 361 regulator-min-microvolt = <2800000>; 362 regulator-max-microvolt = <2800000>; 363 regulator-always-on; 364 }; 365 }; 366 }; 367}; 368 369&i2c2 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_i2c2>; 372 status = "okay"; 373 374 mpl3115@60 { 375 compatible = "fsl,mpl3115"; 376 reg = <0x60>; 377 }; 378}; 379 380&i2c3 { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_i2c3>; 383 status = "okay"; 384}; 385 386&i2c4 { 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_i2c4>; 389 status = "okay"; 390 391 codec: wm8960@1a { 392 compatible = "wlf,wm8960"; 393 reg = <0x1a>; 394 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 395 clock-names = "mclk"; 396 wlf,shared-lrclk; 397 wlf,hp-cfg = <2 2 3>; 398 wlf,gpio-cfg = <1 3>; 399 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 400 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 401 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 402 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 403 assigned-clock-rates = <0>, <884736000>, <12288000>; 404 }; 405}; 406 407&lcdif { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_lcdif>; 410 status = "okay"; 411 412 port { 413 display_out: endpoint { 414 remote-endpoint = <&panel_in>; 415 }; 416 }; 417}; 418 419&pcie { 420 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 421 status = "okay"; 422}; 423 424®_1p0d { 425 vin-supply = <&sw2_reg>; 426}; 427 428®_1p2 { 429 vin-supply = <&sw2_reg>; 430}; 431 432&sai1 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_sai1>; 435 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 436 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 437 <&clks IMX7D_SAI1_ROOT_CLK>; 438 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 439 assigned-clock-rates = <0>, <884736000>, <36864000>; 440 status = "okay"; 441}; 442 443&sai3 { 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; 446 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, 447 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 448 <&clks IMX7D_SAI3_ROOT_CLK>; 449 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 450 assigned-clock-rates = <0>, <884736000>, <36864000>; 451 status = "okay"; 452}; 453 454&snvs_pwrkey { 455 status = "okay"; 456}; 457 458&uart1 { 459 pinctrl-names = "default"; 460 pinctrl-0 = <&pinctrl_uart1>; 461 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 462 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 463 status = "okay"; 464}; 465 466&uart6 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart6>; 469 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 470 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 471 uart-has-rtscts; 472 status = "okay"; 473}; 474 475&usbotg1 { 476 vbus-supply = <®_usb_otg1_vbus>; 477 status = "okay"; 478}; 479 480&usbotg2 { 481 vbus-supply = <®_usb_otg2_vbus>; 482 dr_mode = "host"; 483 status = "okay"; 484}; 485 486&usdhc1 { 487 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 488 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 489 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 490 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 491 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 492 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 493 vmmc-supply = <®_sd1_vmmc>; 494 wakeup-source; 495 keep-power-in-suspend; 496 status = "okay"; 497}; 498 499&usdhc2 { 500 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 501 pinctrl-0 = <&pinctrl_usdhc2>; 502 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 503 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 504 wakeup-source; 505 keep-power-in-suspend; 506 non-removable; 507 vmmc-supply = <®_brcm>; 508 fsl,tuning-step = <2>; 509 status = "okay"; 510}; 511 512&usdhc3 { 513 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 514 pinctrl-0 = <&pinctrl_usdhc3>; 515 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 516 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 517 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 518 assigned-clock-rates = <400000000>; 519 bus-width = <8>; 520 fsl,tuning-step = <2>; 521 non-removable; 522 status = "okay"; 523}; 524 525&wdog1 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_wdog>; 528 fsl,ext-reset-output; 529}; 530 531&iomuxc { 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_hog>; 534 535 imx7d-sdb { 536 pinctrl_brcm_reg: brcmreggrp { 537 fsl,pins = < 538 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 539 >; 540 }; 541 542 pinctrl_ecspi3: ecspi3grp { 543 fsl,pins = < 544 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 545 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 546 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 547 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 548 >; 549 }; 550 551 pinctrl_enet1: enet1grp { 552 fsl,pins = < 553 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 554 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 555 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 556 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 557 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 558 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 559 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 560 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 561 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 562 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 563 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 564 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 565 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 566 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 567 >; 568 }; 569 570 pinctrl_enet2: enet2grp { 571 fsl,pins = < 572 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 573 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 574 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 575 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 576 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 577 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 578 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 579 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 580 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 581 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 582 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 583 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 584 >; 585 }; 586 587 pinctrl_enet2_reg: enet2reggrp { 588 fsl,pins = < 589 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 590 >; 591 }; 592 593 pinctrl_flexcan2: flexcan2grp { 594 fsl,pins = < 595 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 596 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 597 >; 598 }; 599 600 pinctrl_flexcan2_reg: flexcan2reggrp { 601 fsl,pins = < 602 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 603 >; 604 }; 605 606 pinctrl_gpio_keys: gpio_keysgrp { 607 fsl,pins = < 608 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 609 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 610 >; 611 }; 612 613 pinctrl_hog: hoggrp { 614 fsl,pins = < 615 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 616 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ 617 >; 618 }; 619 620 pinctrl_i2c1: i2c1grp { 621 fsl,pins = < 622 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 623 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 624 >; 625 }; 626 627 pinctrl_i2c2: i2c2grp { 628 fsl,pins = < 629 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 630 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 631 >; 632 }; 633 634 pinctrl_i2c3: i2c3grp { 635 fsl,pins = < 636 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 637 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 638 >; 639 }; 640 641 pinctrl_i2c4: i2c4grp { 642 fsl,pins = < 643 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 644 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 645 >; 646 }; 647 648 pinctrl_lcdif: lcdifgrp { 649 fsl,pins = < 650 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 651 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 652 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 653 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 654 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 655 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 656 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 657 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 658 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 659 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 660 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 661 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 662 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 663 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 664 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 665 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 666 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 667 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 668 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 669 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 670 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 671 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 672 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 673 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 674 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 675 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 676 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 677 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 678 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 679 >; 680 }; 681 682 pinctrl_sai1: sai1grp { 683 fsl,pins = < 684 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 685 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 686 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f 687 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 688 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f 689 >; 690 }; 691 692 pinctrl_sai2: sai2grp { 693 fsl,pins = < 694 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 695 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 696 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 697 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 698 >; 699 }; 700 701 pinctrl_sai3: sai3grp { 702 fsl,pins = < 703 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 704 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 705 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 706 >; 707 }; 708 709 pinctrl_spi4: spi4grp { 710 fsl,pins = < 711 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 712 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 713 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 714 >; 715 }; 716 717 pinctrl_tsc2046_pendown: tsc2046_pendown { 718 fsl,pins = < 719 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 720 >; 721 }; 722 723 pinctrl_uart1: uart1grp { 724 fsl,pins = < 725 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 726 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 727 >; 728 }; 729 730 pinctrl_uart5: uart5grp { 731 fsl,pins = < 732 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 733 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 734 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 735 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 736 >; 737 }; 738 739 pinctrl_uart6: uart6grp { 740 fsl,pins = < 741 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 742 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 743 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 744 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 745 >; 746 }; 747 748 pinctrl_usdhc1_gpio: usdhc1_gpiogrp { 749 fsl,pins = < 750 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 751 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 752 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 753 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ 754 >; 755 }; 756 757 pinctrl_usdhc1: usdhc1grp { 758 fsl,pins = < 759 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 760 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 761 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 762 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 763 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 764 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 765 >; 766 }; 767 768 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { 769 fsl,pins = < 770 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a 771 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a 772 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a 773 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a 774 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a 775 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a 776 >; 777 }; 778 779 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { 780 fsl,pins = < 781 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b 782 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b 783 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b 784 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b 785 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b 786 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b 787 >; 788 }; 789 790 pinctrl_usdhc2: usdhc2grp { 791 fsl,pins = < 792 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 793 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 794 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 795 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 796 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 797 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 798 >; 799 }; 800 801 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 802 fsl,pins = < 803 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 804 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 805 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 806 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 807 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 808 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 809 >; 810 }; 811 812 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 813 fsl,pins = < 814 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 815 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 816 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 817 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 818 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 819 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 820 >; 821 }; 822 823 824 pinctrl_usdhc3: usdhc3grp { 825 fsl,pins = < 826 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 827 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 828 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 829 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 830 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 831 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 832 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 833 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 834 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 835 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 836 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 837 >; 838 }; 839 840 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 841 fsl,pins = < 842 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 843 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 844 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 845 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 846 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 847 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 848 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 849 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 850 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 851 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 852 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 853 >; 854 }; 855 856 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 857 fsl,pins = < 858 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 859 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 860 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 861 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 862 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 863 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 864 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 865 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 866 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 867 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 868 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 869 >; 870 }; 871 }; 872}; 873 874&pwm1 { 875 pinctrl-names = "default"; 876 pinctrl-0 = <&pinctrl_pwm1>; 877 status = "okay"; 878}; 879 880&iomuxc_lpsr { 881 pinctrl_wdog: wdoggrp { 882 fsl,pins = < 883 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 884 >; 885 }; 886 887 pinctrl_pwm1: pwm1grp { 888 fsl,pins = < 889 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 890 >; 891 }; 892 893 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { 894 fsl,pins = < 895 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 896 >; 897 }; 898 899 pinctrl_sai3_mclk: sai3grp_mclk { 900 fsl,pins = < 901 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f 902 >; 903 }; 904}; 905