1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017 exceet electronics GmbH
4 * Copyright (C) 2018 Kontron Electronics GmbH
5 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	gpio-leds {
12		compatible = "gpio-leds";
13		pinctrl-names = "default";
14		pinctrl-0 = <&pinctrl_gpio_leds>;
15
16		led1 {
17			label = "debug-led1";
18			gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
19			default-state = "off";
20			linux,default-trigger = "heartbeat";
21		};
22
23		led2 {
24			label = "debug-led2";
25			gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
26			default-state = "off";
27		};
28
29		led3 {
30			label = "debug-led3";
31			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
32			default-state = "off";
33		};
34	};
35
36	pwm-beeper {
37		compatible = "pwm-beeper";
38		pwms = <&pwm8 0 5000>;
39	};
40
41	reg_3v3: regulator-3v3 {
42		compatible = "regulator-fixed";
43		regulator-name = "3v3";
44		regulator-min-microvolt = <3300000>;
45		regulator-max-microvolt = <3300000>;
46	};
47
48	reg_5v: regulator-5v {
49		compatible = "regulator-fixed";
50		regulator-name = "5v";
51		regulator-min-microvolt = <5000000>;
52		regulator-max-microvolt = <5000000>;
53	};
54
55	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
56		compatible = "regulator-fixed";
57		regulator-name = "usb_otg1_vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
61		enable-active-high;
62	};
63
64	reg_vref_adc: regulator-vref-adc {
65		compatible = "regulator-fixed";
66		regulator-name = "vref-adc";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69	};
70};
71
72&adc1 {
73	pinctrl-names = "default";
74	pinctrl-0 = <&pinctrl_adc1>;
75	vref-supply = <&reg_vref_adc>;
76	status = "okay";
77};
78
79&can2 {
80	pinctrl-names = "default";
81	pinctrl-0 = <&pinctrl_flexcan2>;
82	status = "okay";
83};
84
85&ecspi1 {
86	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
87	pinctrl-names = "default";
88	pinctrl-0 = <&pinctrl_ecspi1>;
89	status = "okay";
90
91	eeprom@0 {
92		compatible = "anvo,anv32e61w", "atmel,at25";
93		reg = <0>;
94		spi-max-frequency = <20000000>;
95		spi-cpha;
96		spi-cpol;
97		pagesize = <1>;
98		size = <8192>;
99		address-width = <16>;
100	};
101};
102
103&fec1 {
104	pinctrl-0 = <&pinctrl_enet1>;
105	/delete-node/ mdio;
106};
107
108&fec2 {
109	pinctrl-names = "default";
110	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
111	phy-mode = "rmii";
112	phy-handle = <&ethphy2>;
113	status = "okay";
114
115	mdio {
116		#address-cells = <1>;
117		#size-cells = <0>;
118
119		ethphy1: ethernet-phy@1 {
120			reg = <1>;
121			micrel,led-mode = <0>;
122			clocks = <&clks IMX6UL_CLK_ENET_REF>;
123			clock-names = "rmii-ref";
124		};
125
126		ethphy2: ethernet-phy@2 {
127			reg = <2>;
128			micrel,led-mode = <0>;
129			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
130			clock-names = "rmii-ref";
131		};
132	};
133};
134
135&i2c1 {
136	clock-frequency = <100000>;
137	pinctrl-names = "default";
138	pinctrl-0 = <&pinctrl_i2c1>;
139	status = "okay";
140};
141
142&i2c4 {
143	clock-frequency = <100000>;
144	pinctrl-names = "default";
145	pinctrl-0 = <&pinctrl_i2c4>;
146	status = "okay";
147
148	rtc@32 {
149		compatible = "epson,rx8900";
150		reg = <0x32>;
151	};
152};
153
154&pwm8 {
155	#pwm-cells = <2>;
156	pinctrl-names = "default";
157	pinctrl-0 = <&pinctrl_pwm8>;
158	status = "okay";
159};
160
161&uart1 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_uart1>;
164	status = "okay";
165};
166
167&uart2 {
168	pinctrl-names = "default";
169	pinctrl-0 = <&pinctrl_uart2>;
170	linux,rs485-enabled-at-boot-time;
171	rs485-rx-during-tx;
172	rs485-rts-active-low;
173	uart-has-rtscts;
174	status = "okay";
175};
176
177&uart3 {
178	pinctrl-names = "default";
179	pinctrl-0 = <&pinctrl_uart3>;
180	uart-has-rtscts;
181	status = "okay";
182};
183
184&uart4 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_uart4>;
187	status = "okay";
188};
189
190&usbotg1 {
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_usbotg1>;
193	dr_mode = "otg";
194	srp-disable;
195	hnp-disable;
196	adp-disable;
197	over-current-active-low;
198	vbus-supply = <&reg_usb_otg1_vbus>;
199	status = "okay";
200};
201
202&usbotg2 {
203	dr_mode = "host";
204	disable-over-current;
205	vbus-supply = <&reg_5v>;
206	status = "okay";
207};
208
209&usdhc1 {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_usdhc1>;
212	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
213	keep-power-in-suspend;
214	wakeup-source;
215	vmmc-supply = <&reg_3v3>;
216	voltage-ranges = <3300 3300>;
217	no-1-8-v;
218	status = "okay";
219};
220
221&usdhc2 {
222	pinctrl-names = "default", "state_100mhz", "state_200mhz";
223	pinctrl-0 = <&pinctrl_usdhc2>;
224	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
225	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
226	non-removable;
227	keep-power-in-suspend;
228	wakeup-source;
229	vmmc-supply = <&reg_3v3>;
230	voltage-ranges = <3300 3300>;
231	no-1-8-v;
232	status = "okay";
233};
234
235&iomuxc {
236	pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
237
238	pinctrl_adc1: adc1grp {
239		fsl,pins = <
240			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
241			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
242			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0xb0
243		>;
244	};
245
246	pinctrl_ecspi1: ecspi1grp {
247		fsl,pins = <
248			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO	0x100b1
249			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI	0x100b1
250			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK	0x100b1
251			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x100b1	/* ECSPI1-CS1 */
252		>;
253	};
254
255	pinctrl_enet2: enet2grp {
256		fsl,pins = <
257			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
258			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
259			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
260			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
261			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
262			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
263			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
264			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b009
265		>;
266	};
267
268	pinctrl_enet2_mdio: enet2mdiogrp {
269		fsl,pins = <
270			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
271			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
272		>;
273	};
274
275	pinctrl_flexcan2: flexcan2grp{
276		fsl,pins = <
277			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
278			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
279		>;
280	};
281
282	pinctrl_gpio: gpiogrp {
283		fsl,pins = <
284			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0	/* DOUT1 */
285			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* DIN1 */
286			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x1b0b0	/* DOUT2 */
287			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0	/* DIN2 */
288		>;
289	};
290
291	pinctrl_gpio_leds: gpioledsgrp {
292		fsl,pins = <
293			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x1b0b0	/* LED H14 */
294			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x1b0b0	/* LED H15 */
295			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* LED H16 */
296		>;
297	};
298
299	pinctrl_i2c1: i2c1grp {
300		fsl,pins = <
301			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
302			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
303		>;
304	};
305
306	pinctrl_i2c4: i2c4grp {
307		fsl,pins = <
308			MX6UL_PAD_UART2_TX_DATA__I2C4_SCL	0x4001f8b0
309			MX6UL_PAD_UART2_RX_DATA__I2C4_SDA	0x4001f8b0
310		>;
311	};
312
313	pinctrl_pwm8: pwm8grp {
314		fsl,pins = <
315			MX6UL_PAD_CSI_HSYNC__PWM8_OUT		0x110b0
316		>;
317	};
318
319	pinctrl_uart1: uart1grp {
320		fsl,pins = <
321			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
322			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
323		>;
324	};
325
326	pinctrl_uart2: uart2grp {
327		fsl,pins = <
328			MX6UL_PAD_NAND_DATA04__UART2_DCE_TX	0x1b0b1
329			MX6UL_PAD_NAND_DATA05__UART2_DCE_RX	0x1b0b1
330			MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS	0x1b0b1
331			/*
332			 * mux unused RTS to make sure it doesn't cause
333			 * any interrupts when it is undefined
334			 */
335			MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS	0x1b0b1
336		>;
337	};
338
339	pinctrl_uart3: uart3grp {
340		fsl,pins = <
341			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
342			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
343			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b1
344			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
345		>;
346	};
347
348	pinctrl_uart4: uart4grp {
349		fsl,pins = <
350			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
351			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
352		>;
353	};
354
355	pinctrl_usbotg1: usbotg1 {
356		fsl,pins = <
357			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x1b0b0
358		>;
359	};
360
361	pinctrl_usdhc1: usdhc1grp {
362		fsl,pins = <
363			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
364			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
365			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
366			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
367			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
368			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
369			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x100b1	/* SD1_CD */
370		>;
371	};
372
373	pinctrl_usdhc2: usdhc2grp {
374		fsl,pins = <
375			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
376			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
377			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
378			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
379			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
380			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
381		>;
382	};
383
384	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
385		fsl,pins = <
386			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
387			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
388			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
389			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
390			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
391			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
392		>;
393	};
394
395	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
396		fsl,pins = <
397			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
398			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
399			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
400			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
401			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
402			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
403		>;
404	};
405};
406