1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 * 6 */ 7 8#include <dt-bindings/clock/imx6qdl-clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11 12/ { 13 chosen { 14 stdout-path = &uart2; 15 }; 16 17 aliases { 18 mmc0 = &usdhc3; 19 mmc1 = &usdhc4; 20 }; 21 22 memory@10000000 { 23 device_type = "memory"; 24 reg = <0x10000000 0x40000000>; 25 }; 26 27 regulators { 28 compatible = "simple-bus"; 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 reg_2p5v: regulator@0 { 33 compatible = "regulator-fixed"; 34 reg = <0>; 35 regulator-name = "2P5V"; 36 regulator-min-microvolt = <2500000>; 37 regulator-max-microvolt = <2500000>; 38 regulator-always-on; 39 }; 40 41 reg_3p3v: regulator@1 { 42 compatible = "regulator-fixed"; 43 reg = <1>; 44 regulator-name = "3P3V"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 regulator-always-on; 48 }; 49 50 reg_usb_otg_vbus: regulator@2 { 51 compatible = "regulator-fixed"; 52 reg = <2>; 53 regulator-name = "usb_otg_vbus"; 54 regulator-min-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>; 56 gpio = <&gpio3 22 0>; 57 enable-active-high; 58 }; 59 60 reg_can_xcvr: regulator@3 { 61 compatible = "regulator-fixed"; 62 reg = <3>; 63 regulator-name = "CAN XCVR"; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_can_xcvr>; 68 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 69 }; 70 71 reg_1p5v: regulator@4 { 72 compatible = "regulator-fixed"; 73 reg = <4>; 74 regulator-name = "1P5V"; 75 regulator-min-microvolt = <1500000>; 76 regulator-max-microvolt = <1500000>; 77 regulator-always-on; 78 }; 79 80 reg_1p8v: regulator@5 { 81 compatible = "regulator-fixed"; 82 reg = <5>; 83 regulator-name = "1P8V"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 regulator-always-on; 87 }; 88 89 reg_2p8v: regulator@6 { 90 compatible = "regulator-fixed"; 91 reg = <6>; 92 regulator-name = "2P8V"; 93 regulator-min-microvolt = <2800000>; 94 regulator-max-microvolt = <2800000>; 95 regulator-always-on; 96 }; 97 98 reg_usb_h1_vbus: regulator@7 { 99 compatible = "regulator-fixed"; 100 reg = <7>; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_usbh1>; 103 regulator-name = "usb_h1_vbus"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 }; 110 111 mipi_xclk: mipi_xclk { 112 compatible = "pwm-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <22000000>; 115 clock-output-names = "mipi_pwm3"; 116 pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ 117 status = "okay"; 118 }; 119 120 gpio-keys { 121 compatible = "gpio-keys"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_gpio_keys>; 124 125 power { 126 label = "Power Button"; 127 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 128 linux,code = <KEY_POWER>; 129 wakeup-source; 130 }; 131 132 menu { 133 label = "Menu"; 134 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 135 linux,code = <KEY_MENU>; 136 }; 137 138 home { 139 label = "Home"; 140 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 141 linux,code = <KEY_HOME>; 142 }; 143 144 back { 145 label = "Back"; 146 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 147 linux,code = <KEY_BACK>; 148 }; 149 150 volume-up { 151 label = "Volume Up"; 152 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 153 linux,code = <KEY_VOLUMEUP>; 154 }; 155 156 volume-down { 157 label = "Volume Down"; 158 gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; 159 linux,code = <KEY_VOLUMEDOWN>; 160 }; 161 }; 162 163 sound { 164 compatible = "fsl,imx6q-sabrelite-sgtl5000", 165 "fsl,imx-audio-sgtl5000"; 166 model = "imx6q-sabrelite-sgtl5000"; 167 ssi-controller = <&ssi1>; 168 audio-codec = <&codec>; 169 audio-routing = 170 "MIC_IN", "Mic Jack", 171 "Mic Jack", "Mic Bias", 172 "Headphone Jack", "HP_OUT"; 173 mux-int-port = <1>; 174 mux-ext-port = <4>; 175 }; 176 177 backlight_lcd: backlight-lcd { 178 compatible = "pwm-backlight"; 179 pwms = <&pwm1 0 5000000>; 180 brightness-levels = <0 4 8 16 32 64 128 255>; 181 default-brightness-level = <7>; 182 power-supply = <®_3p3v>; 183 status = "okay"; 184 }; 185 186 backlight_lvds: backlight-lvds { 187 compatible = "pwm-backlight"; 188 pwms = <&pwm4 0 5000000>; 189 brightness-levels = <0 4 8 16 32 64 128 255>; 190 default-brightness-level = <7>; 191 power-supply = <®_3p3v>; 192 status = "okay"; 193 }; 194 195 lcd_display: disp0 { 196 compatible = "fsl,imx-parallel-display"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interface-pix-fmt = "bgr666"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_j15>; 202 status = "okay"; 203 204 port@0 { 205 reg = <0>; 206 207 lcd_display_in: endpoint { 208 remote-endpoint = <&ipu1_di0_disp0>; 209 }; 210 }; 211 212 port@1 { 213 reg = <1>; 214 215 lcd_display_out: endpoint { 216 remote-endpoint = <&lcd_panel_in>; 217 }; 218 }; 219 }; 220 221 panel-lcd { 222 compatible = "okaya,rs800480t-7x0gp"; 223 backlight = <&backlight_lcd>; 224 225 port { 226 lcd_panel_in: endpoint { 227 remote-endpoint = <&lcd_display_out>; 228 }; 229 }; 230 }; 231 232 panel-lvds0 { 233 compatible = "hannstar,hsd100pxn1"; 234 backlight = <&backlight_lvds>; 235 236 port { 237 panel_in: endpoint { 238 remote-endpoint = <&lvds0_out>; 239 }; 240 }; 241 }; 242}; 243 244&ipu1_csi0_from_ipu1_csi0_mux { 245 bus-width = <8>; 246 data-shift = <12>; /* Lines 19:12 used */ 247 hsync-active = <1>; 248 vync-active = <1>; 249}; 250 251&ipu1_csi0_mux_from_parallel_sensor { 252 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; 253}; 254 255&ipu1_csi0 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_ipu1_csi0>; 258}; 259 260&audmux { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_audmux>; 263 status = "okay"; 264}; 265 266&can1 { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_can1>; 269 xceiver-supply = <®_can_xcvr>; 270 status = "okay"; 271}; 272 273&clks { 274 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 275 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 276 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 277 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 278}; 279 280&ecspi1 { 281 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_ecspi1>; 284 status = "okay"; 285 286 flash: flash@0 { 287 compatible = "sst,sst25vf016b", "jedec,spi-nor"; 288 spi-max-frequency = <20000000>; 289 reg = <0>; 290 }; 291}; 292 293&fec { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_enet>; 296 phy-mode = "rgmii"; 297 phy-handle = <ðphy>; 298 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 299 status = "okay"; 300 301 mdio { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 ethphy: ethernet-phy { 306 compatible = "ethernet-phy-ieee802.3-c22"; 307 txen-skew-ps = <0>; 308 txc-skew-ps = <3000>; 309 rxdv-skew-ps = <0>; 310 rxc-skew-ps = <3000>; 311 rxd0-skew-ps = <0>; 312 rxd1-skew-ps = <0>; 313 rxd2-skew-ps = <0>; 314 rxd3-skew-ps = <0>; 315 txd0-skew-ps = <0>; 316 txd1-skew-ps = <0>; 317 txd2-skew-ps = <0>; 318 txd3-skew-ps = <0>; 319 }; 320 }; 321}; 322 323&hdmi { 324 ddc-i2c-bus = <&i2c2>; 325 status = "okay"; 326}; 327 328&i2c1 { 329 clock-frequency = <100000>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_i2c1>; 332 status = "okay"; 333 334 codec: sgtl5000@a { 335 compatible = "fsl,sgtl5000"; 336 reg = <0x0a>; 337 clocks = <&clks IMX6QDL_CLK_CKO>; 338 VDDA-supply = <®_2p5v>; 339 VDDIO-supply = <®_3p3v>; 340 }; 341}; 342 343&i2c2 { 344 clock-frequency = <100000>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_i2c2>; 347 status = "okay"; 348 349 ov5640: camera@40 { 350 compatible = "ovti,ov5640"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_ov5640>; 353 reg = <0x40>; 354 clocks = <&mipi_xclk>; 355 clock-names = "xclk"; 356 DOVDD-supply = <®_1p8v>; 357 AVDD-supply = <®_2p8v>; 358 DVDD-supply = <®_1p5v>; 359 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */ 360 powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */ 361 362 port { 363 ov5640_to_mipi_csi2: endpoint { 364 remote-endpoint = <&mipi_csi2_in>; 365 clock-lanes = <0>; 366 data-lanes = <1 2>; 367 }; 368 }; 369 }; 370 371 ov5642: camera@42 { 372 compatible = "ovti,ov5642"; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_ov5642>; 375 clocks = <&clks IMX6QDL_CLK_CKO2>; 376 clock-names = "xclk"; 377 reg = <0x42>; 378 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 379 powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 380 gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 381 status = "disabled"; 382 383 port { 384 ov5642_to_ipu1_csi0_mux: endpoint { 385 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 386 bus-width = <8>; 387 hsync-active = <1>; 388 vsync-active = <1>; 389 }; 390 }; 391 }; 392}; 393 394&i2c3 { 395 clock-frequency = <100000>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_i2c3>; 398 status = "okay"; 399}; 400 401&iomuxc { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_hog>; 404 405 imx6q-sabrelite { 406 pinctrl_hog: hoggrp { 407 fsl,pins = < 408 /* SGTL5000 sys_mclk */ 409 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 410 >; 411 }; 412 413 pinctrl_audmux: audmuxgrp { 414 fsl,pins = < 415 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 416 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 417 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 418 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 419 >; 420 }; 421 422 pinctrl_can1: can1grp { 423 fsl,pins = < 424 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 425 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 426 >; 427 }; 428 429 pinctrl_can_xcvr: can-xcvrgrp { 430 fsl,pins = < 431 /* Flexcan XCVR enable */ 432 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 433 >; 434 }; 435 436 pinctrl_ecspi1: ecspi1grp { 437 fsl,pins = < 438 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 439 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 440 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 441 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */ 442 >; 443 }; 444 445 pinctrl_enet: enetgrp { 446 fsl,pins = < 447 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 448 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 449 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 450 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 451 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 452 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 453 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 454 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 455 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 456 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 457 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 458 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 459 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 460 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 461 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 462 /* Phy reset */ 463 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 464 >; 465 }; 466 467 pinctrl_gpio_keys: gpio-keysgrp { 468 fsl,pins = < 469 /* Power Button */ 470 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 471 /* Menu Button */ 472 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 473 /* Home Button */ 474 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 475 /* Back Button */ 476 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 477 /* Volume Up Button */ 478 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 479 /* Volume Down Button */ 480 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 481 >; 482 }; 483 484 pinctrl_i2c1: i2c1grp { 485 fsl,pins = < 486 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 487 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 488 >; 489 }; 490 491 pinctrl_i2c2: i2c2grp { 492 fsl,pins = < 493 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 494 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 495 >; 496 }; 497 498 pinctrl_i2c3: i2c3grp { 499 fsl,pins = < 500 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 501 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 502 >; 503 }; 504 505 pinctrl_ipu1_csi0: ipu1csi0grp { 506 fsl,pins = < 507 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 508 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 509 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 510 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 511 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 512 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 513 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 514 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 515 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 516 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 517 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 518 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 519 >; 520 }; 521 522 pinctrl_j15: j15grp { 523 fsl,pins = < 524 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 525 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 526 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 527 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 528 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 529 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 530 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 531 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 532 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 533 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 534 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 535 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 536 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 537 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 538 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 539 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 540 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 541 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 542 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 543 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 544 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 545 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 546 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 547 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 548 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 549 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 550 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 551 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 552 >; 553 }; 554 555 pinctrl_ov5640: ov5640grp { 556 fsl,pins = < 557 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 558 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 559 >; 560 }; 561 562 pinctrl_ov5642: ov5642grp { 563 fsl,pins = < 564 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 565 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 566 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 567 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 568 >; 569 }; 570 571 pinctrl_pwm1: pwm1grp { 572 fsl,pins = < 573 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 574 >; 575 }; 576 577 pinctrl_pwm3: pwm3grp { 578 fsl,pins = < 579 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 580 >; 581 }; 582 583 pinctrl_pwm4: pwm4grp { 584 fsl,pins = < 585 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 586 >; 587 }; 588 589 pinctrl_uart1: uart1grp { 590 fsl,pins = < 591 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 592 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 593 >; 594 }; 595 596 pinctrl_uart2: uart2grp { 597 fsl,pins = < 598 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 599 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 600 >; 601 }; 602 603 pinctrl_usbh1: usbh1grp { 604 fsl,pins = < 605 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0 606 >; 607 }; 608 609 pinctrl_usbotg: usbotggrp { 610 fsl,pins = < 611 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 612 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 613 /* power enable, high active */ 614 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 615 >; 616 }; 617 618 pinctrl_usdhc3: usdhc3grp { 619 fsl,pins = < 620 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 621 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 622 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 623 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 624 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 625 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 626 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ 627 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */ 628 >; 629 }; 630 631 pinctrl_usdhc4: usdhc4grp { 632 fsl,pins = < 633 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 634 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 635 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 636 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 637 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 638 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 639 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */ 640 >; 641 }; 642 }; 643}; 644 645&ipu1_di0_disp0 { 646 remote-endpoint = <&lcd_display_in>; 647}; 648 649&ldb { 650 status = "okay"; 651 652 lvds-channel@0 { 653 status = "okay"; 654 655 port@4 { 656 reg = <4>; 657 658 lvds0_out: endpoint { 659 remote-endpoint = <&panel_in>; 660 }; 661 }; 662 }; 663}; 664 665&pcie { 666 status = "okay"; 667}; 668 669&pwm1 { 670 #pwm-cells = <2>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&pinctrl_pwm1>; 673 status = "okay"; 674}; 675 676&pwm3 { 677 #pwm-cells = <2>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_pwm3>; 680 status = "okay"; 681}; 682 683&pwm4 { 684 #pwm-cells = <2>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_pwm4>; 687 status = "okay"; 688}; 689 690&ssi1 { 691 status = "okay"; 692}; 693 694&uart1 { 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_uart1>; 697 status = "okay"; 698}; 699 700&uart2 { 701 pinctrl-names = "default"; 702 pinctrl-0 = <&pinctrl_uart2>; 703 status = "okay"; 704}; 705 706&usbh1 { 707 vbus-supply = <®_usb_h1_vbus>; 708 status = "okay"; 709}; 710 711&usbotg { 712 vbus-supply = <®_usb_otg_vbus>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_usbotg>; 715 disable-over-current; 716 status = "okay"; 717}; 718 719&usdhc3 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&pinctrl_usdhc3>; 722 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 723 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 724 vmmc-supply = <®_3p3v>; 725 status = "okay"; 726}; 727 728&usdhc4 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_usdhc4>; 731 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; 732 vmmc-supply = <®_3p3v>; 733 status = "okay"; 734}; 735 736&mipi_csi { 737 status = "okay"; 738 739 port@0 { 740 reg = <0>; 741 742 mipi_csi2_in: endpoint { 743 remote-endpoint = <&ov5640_to_mipi_csi2>; 744 clock-lanes = <0>; 745 data-lanes = <1 2>; 746 }; 747 }; 748}; 749