1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 PHYTEC Messtechnik
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7/ {
8	display: display0 {
9		#address-cells = <1>;
10		#size-cells = <0>;
11		compatible = "fsl,imx-parallel-display";
12		pinctrl-names = "default";
13		pinctrl-0 = <&pinctrl_disp0>;
14		interface-pix-fmt = "rgb24";
15		status = "disabled";
16
17		port@0 {
18			reg = <0>;
19
20			display0_in: endpoint {
21				remote-endpoint = <&ipu1_di0_disp0>;
22			};
23		};
24
25		port@1 {
26			reg = <1>;
27
28			display0_out: endpoint {
29				remote-endpoint = <&peb_panel_lcd_in>;
30			};
31		};
32	};
33
34	panel-lcd {
35		compatible = "edt,etm0700g0edh6";
36		pinctrl-names = "default";
37		pinctrl-0 = <&pinctrl_disp0_pwr>;
38		power-supply = <&reg_display>;
39		enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
40		backlight = <&backlight>;
41		status = "disabled";
42
43		port {
44			peb_panel_lcd_in: endpoint {
45				remote-endpoint = <&display0_out>;
46			};
47		};
48	};
49
50	reg_display: regulator-peb-display {
51		compatible = "regulator-fixed";
52		regulator-name = "peb-display";
53		regulator-min-microvolt = <3300000>;
54		regulator-max-microvolt = <3300000>;
55	};
56};
57
58&i2c1 {
59	edt_ft5x06: touchscreen@38 {
60		compatible = "edt,edt-ft5406";
61		pinctrl-names = "default";
62		pinctrl-0 = <&pinctrl_edt_ft5x06>;
63		reg = <0x38>;
64		interrupt-parent = <&gpio3>;
65		interrupts = <2 IRQ_TYPE_NONE>;
66		status = "disabled";
67	};
68};
69
70&ipu1_di0_disp0 {
71	remote-endpoint = <&display0_in>;
72};
73
74&iomuxc {
75	pinctrl_disp0: disp0grp {
76		fsl,pins = <
77			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
78			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
79			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
80			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x1b080
81			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
82			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
83			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
84			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
85			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
86			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
87			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
88			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
89			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
90			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
91			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
92			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
93			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
94			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
95			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
96			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
97			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
98			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
99			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
100			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
101			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
102			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
103			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
104			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
105		>;
106	};
107
108	pinctrl_disp0_pwr: disp0pwrgrp {
109		fsl,pins = <
110			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
111		>;
112	};
113
114	pinctrl_edt_ft5x06: edtft5x06grp {
115		fsl,pins = <
116			MX6QDL_PAD_EIM_DA2__GPIO3_IO02			0xb0b1
117		>;
118	};
119};
120