1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/sound/fsl-imx-audmux.h>
10
11/ {
12	/* these are used by bootloader for disabling nodes */
13	aliases {
14		led0 = &led0;
15		led1 = &led1;
16		led2 = &led2;
17		nand = &gpmi;
18		ssi0 = &ssi1;
19		usb0 = &usbh1;
20		usb1 = &usbotg;
21	};
22
23	chosen {
24		bootargs = "console=ttymxc1,115200";
25	};
26
27	backlight {
28		compatible = "pwm-backlight";
29		pwms = <&pwm4 0 5000000>;
30		brightness-levels = <0 4 8 16 32 64 128 255>;
31		default-brightness-level = <7>;
32	};
33
34	gpio-keys {
35		compatible = "gpio-keys";
36
37		user-pb {
38			label = "user_pb";
39			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
40			linux,code = <BTN_0>;
41		};
42
43		user-pb1x {
44			label = "user_pb1x";
45			linux,code = <BTN_1>;
46			interrupt-parent = <&gsc>;
47			interrupts = <0>;
48		};
49
50		key-erased {
51			label = "key-erased";
52			linux,code = <BTN_2>;
53			interrupt-parent = <&gsc>;
54			interrupts = <1>;
55		};
56
57		eeprom-wp {
58			label = "eeprom_wp";
59			linux,code = <BTN_3>;
60			interrupt-parent = <&gsc>;
61			interrupts = <2>;
62		};
63
64		tamper {
65			label = "tamper";
66			linux,code = <BTN_4>;
67			interrupt-parent = <&gsc>;
68			interrupts = <5>;
69		};
70
71		switch-hold {
72			label = "switch_hold";
73			linux,code = <BTN_5>;
74			interrupt-parent = <&gsc>;
75			interrupts = <7>;
76		};
77	};
78
79	leds {
80		compatible = "gpio-leds";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_gpio_leds>;
83
84		led0: led-user1 {
85			label = "user1";
86			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87			default-state = "on";
88			linux,default-trigger = "heartbeat";
89		};
90
91		led1: led-user2 {
92			label = "user2";
93			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
94			default-state = "off";
95		};
96
97		led2: led-user3 {
98			label = "user3";
99			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
100			default-state = "off";
101		};
102	};
103
104	memory@10000000 {
105		device_type = "memory";
106		reg = <0x10000000 0x40000000>;
107	};
108
109	pps {
110		compatible = "pps-gpio";
111		pinctrl-names = "default";
112		pinctrl-0 = <&pinctrl_pps>;
113		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
114		status = "okay";
115	};
116
117	regulators {
118		compatible = "simple-bus";
119		#address-cells = <1>;
120		#size-cells = <0>;
121
122		reg_1p0v: regulator@0 {
123			compatible = "regulator-fixed";
124			reg = <0>;
125			regulator-name = "1P0V";
126			regulator-min-microvolt = <1000000>;
127			regulator-max-microvolt = <1000000>;
128			regulator-always-on;
129		};
130
131		reg_3p3v: regulator@1 {
132			compatible = "regulator-fixed";
133			reg = <1>;
134			regulator-name = "3P3V";
135			regulator-min-microvolt = <3300000>;
136			regulator-max-microvolt = <3300000>;
137			regulator-always-on;
138		};
139
140		reg_can1_stby: regulator-can1-stby {
141			compatible = "regulator-fixed";
142			pinctrl-names = "default";
143			pinctrl-0 = <&pinctrl_reg_can1>;
144			regulator-name = "can1_stby";
145			gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
146			regulator-min-microvolt = <3300000>;
147			regulator-max-microvolt = <3300000>;
148		};
149
150		reg_usb_h1_vbus: regulator@2 {
151			compatible = "regulator-fixed";
152			reg = <2>;
153			regulator-name = "usb_h1_vbus";
154			regulator-min-microvolt = <5000000>;
155			regulator-max-microvolt = <5000000>;
156			regulator-always-on;
157		};
158
159		reg_usb_otg_vbus: regulator@3 {
160			compatible = "regulator-fixed";
161			reg = <3>;
162			regulator-name = "usb_otg_vbus";
163			regulator-min-microvolt = <5000000>;
164			regulator-max-microvolt = <5000000>;
165			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
166			enable-active-high;
167		};
168	};
169
170	sound-analog {
171		compatible = "fsl,imx6q-ventana-sgtl5000",
172			     "fsl,imx-audio-sgtl5000";
173		model = "sgtl5000-audio";
174		ssi-controller = <&ssi1>;
175		audio-codec = <&sgtl5000>;
176		audio-routing =
177			"MIC_IN", "Mic Jack",
178			"Mic Jack", "Mic Bias",
179			"Headphone Jack", "HP_OUT";
180		mux-int-port = <1>;
181		mux-ext-port = <4>;
182	};
183};
184
185&audmux {
186	pinctrl-names = "default";
187	pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
188	status = "okay";
189
190	mux-ssi2 {
191		fsl,audmux-port = <1>;
192		fsl,port-config = <
193			(IMX_AUDMUX_V2_PTCR_TFSDIR |
194			IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
195			IMX_AUDMUX_V2_PTCR_TCLKDIR |
196			IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
197			IMX_AUDMUX_V2_PTCR_SYN)
198			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
199		>;
200	};
201
202	mux-aud5 {
203		fsl,audmux-port = <4>;
204		fsl,port-config = <
205			IMX_AUDMUX_V2_PTCR_SYN
206			IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
207	};
208};
209
210&can1 {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_flexcan1>;
213	xceiver-supply = <&reg_can1_stby>;
214	status = "okay";
215};
216
217&clks {
218	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
219			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
220	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
221				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
222};
223
224&ecspi2 {
225	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_ecspi2>;
228	status = "okay";
229};
230
231&fec {
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_enet>;
234	phy-mode = "rgmii-id";
235	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
236	status = "okay";
237};
238
239&gpmi {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_gpmi_nand>;
242	status = "okay";
243};
244
245&hdmi {
246	ddc-i2c-bus = <&i2c3>;
247	status = "okay";
248};
249
250&i2c1 {
251	clock-frequency = <100000>;
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_i2c1>;
254	status = "okay";
255
256	gsc: gsc@20 {
257		compatible = "gw,gsc";
258		reg = <0x20>;
259		interrupt-parent = <&gpio1>;
260		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
261		interrupt-controller;
262		#interrupt-cells = <1>;
263		#address-cells = <1>;
264		#size-cells = <0>;
265
266		adc {
267			compatible = "gw,gsc-adc";
268			#address-cells = <1>;
269			#size-cells = <0>;
270
271			channel@0 {
272				gw,mode = <0>;
273				reg = <0x00>;
274				label = "temp";
275			};
276
277			channel@2 {
278				gw,mode = <1>;
279				reg = <0x02>;
280				label = "vdd_vin";
281			};
282
283			channel@5 {
284				gw,mode = <1>;
285				reg = <0x05>;
286				label = "vdd_3p3";
287			};
288
289			channel@8 {
290				gw,mode = <1>;
291				reg = <0x08>;
292				label = "vdd_bat";
293			};
294
295			channel@b {
296				gw,mode = <1>;
297				reg = <0x0b>;
298				label = "vdd_5p0";
299			};
300
301			channel@e {
302				gw,mode = <1>;
303				reg = <0xe>;
304				label = "vdd_arm";
305			};
306
307			channel@11 {
308				gw,mode = <1>;
309				reg = <0x11>;
310				label = "vdd_soc";
311			};
312
313			channel@14 {
314				gw,mode = <1>;
315				reg = <0x14>;
316				label = "vdd_3p0";
317			};
318
319			channel@17 {
320				gw,mode = <1>;
321				reg = <0x17>;
322				label = "vdd_1p5";
323			};
324
325			channel@1d {
326				gw,mode = <1>;
327				reg = <0x1d>;
328				label = "vdd_1p8";
329			};
330
331			channel@20 {
332				gw,mode = <1>;
333				reg = <0x20>;
334				label = "vdd_1p0";
335			};
336
337			channel@23 {
338				gw,mode = <1>;
339				reg = <0x23>;
340				label = "vdd_2p5";
341			};
342
343			channel@26 {
344				gw,mode = <1>;
345				reg = <0x26>;
346				label = "vdd_gps";
347			};
348		};
349
350		fan-controller@2c {
351			compatible = "gw,gsc-fan";
352			reg = <0x2c>;
353		};
354	};
355
356	gsc_gpio: gpio@23 {
357		compatible = "nxp,pca9555";
358		reg = <0x23>;
359		gpio-controller;
360		#gpio-cells = <2>;
361		interrupt-parent = <&gsc>;
362		interrupts = <4>;
363	};
364
365	eeprom1: eeprom@50 {
366		compatible = "atmel,24c02";
367		reg = <0x50>;
368		pagesize = <16>;
369	};
370
371	eeprom2: eeprom@51 {
372		compatible = "atmel,24c02";
373		reg = <0x51>;
374		pagesize = <16>;
375	};
376
377	eeprom3: eeprom@52 {
378		compatible = "atmel,24c02";
379		reg = <0x52>;
380		pagesize = <16>;
381	};
382
383	eeprom4: eeprom@53 {
384		compatible = "atmel,24c02";
385		reg = <0x53>;
386		pagesize = <16>;
387	};
388
389	rtc: ds1672@68 {
390		compatible = "dallas,ds1672";
391		reg = <0x68>;
392	};
393};
394
395&i2c2 {
396	clock-frequency = <100000>;
397	pinctrl-names = "default";
398	pinctrl-0 = <&pinctrl_i2c2>;
399	status = "okay";
400
401	pmic: pmic@8 {
402		compatible = "fsl,pfuze100";
403		reg = <0x08>;
404
405		regulators {
406			sw1a_reg: sw1ab {
407				regulator-min-microvolt = <300000>;
408				regulator-max-microvolt = <1875000>;
409				regulator-boot-on;
410				regulator-always-on;
411				regulator-ramp-delay = <6250>;
412			};
413
414			sw1c_reg: sw1c {
415				regulator-min-microvolt = <300000>;
416				regulator-max-microvolt = <1875000>;
417				regulator-boot-on;
418				regulator-always-on;
419				regulator-ramp-delay = <6250>;
420			};
421
422			sw2_reg: sw2 {
423				regulator-min-microvolt = <800000>;
424				regulator-max-microvolt = <3950000>;
425				regulator-boot-on;
426				regulator-always-on;
427			};
428
429			sw3a_reg: sw3a {
430				regulator-min-microvolt = <400000>;
431				regulator-max-microvolt = <1975000>;
432				regulator-boot-on;
433				regulator-always-on;
434			};
435
436			sw3b_reg: sw3b {
437				regulator-min-microvolt = <400000>;
438				regulator-max-microvolt = <1975000>;
439				regulator-boot-on;
440				regulator-always-on;
441			};
442
443			sw4_reg: sw4 {
444				regulator-min-microvolt = <800000>;
445				regulator-max-microvolt = <3300000>;
446			};
447
448			swbst_reg: swbst {
449				regulator-min-microvolt = <5000000>;
450				regulator-max-microvolt = <5150000>;
451				regulator-boot-on;
452				regulator-always-on;
453			};
454
455			snvs_reg: vsnvs {
456				regulator-min-microvolt = <1000000>;
457				regulator-max-microvolt = <3000000>;
458				regulator-boot-on;
459				regulator-always-on;
460			};
461
462			vref_reg: vrefddr {
463				regulator-boot-on;
464				regulator-always-on;
465			};
466
467			vgen1_reg: vgen1 {
468				regulator-min-microvolt = <800000>;
469				regulator-max-microvolt = <1550000>;
470			};
471
472			vgen2_reg: vgen2 {
473				regulator-min-microvolt = <800000>;
474				regulator-max-microvolt = <1550000>;
475			};
476
477			vgen3_reg: vgen3 {
478				regulator-min-microvolt = <1800000>;
479				regulator-max-microvolt = <3300000>;
480			};
481
482			vgen4_reg: vgen4 {
483				regulator-min-microvolt = <1800000>;
484				regulator-max-microvolt = <3300000>;
485				regulator-always-on;
486			};
487
488			vgen5_reg: vgen5 {
489				regulator-min-microvolt = <1800000>;
490				regulator-max-microvolt = <3300000>;
491				regulator-always-on;
492			};
493
494			vgen6_reg: vgen6 {
495				regulator-min-microvolt = <1800000>;
496				regulator-max-microvolt = <3300000>;
497				regulator-always-on;
498			};
499		};
500	};
501};
502
503&i2c3 {
504	clock-frequency = <100000>;
505	pinctrl-names = "default";
506	pinctrl-0 = <&pinctrl_i2c3>;
507	status = "okay";
508
509	sgtl5000: audio-codec@a {
510		compatible = "fsl,sgtl5000";
511		reg = <0x0a>;
512		clocks = <&clks IMX6QDL_CLK_CKO>;
513		VDDA-supply = <&sw4_reg>;
514		VDDIO-supply = <&reg_3p3v>;
515	};
516
517	touchscreen: egalax_ts@4 {
518		compatible = "eeti,egalax_ts";
519		reg = <0x04>;
520		interrupt-parent = <&gpio7>;
521		interrupts = <12 2>;
522		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
523	};
524
525	accel@1e {
526		compatible = "nxp,fxos8700";
527		reg = <0x1e>;
528	};
529};
530
531&ldb {
532	status = "okay";
533
534	lvds-channel@0 {
535		fsl,data-mapping = "spwg";
536		fsl,data-width = <18>;
537		status = "okay";
538
539		display-timings {
540			native-mode = <&timing0>;
541			timing0: hsd100pxn1 {
542				clock-frequency = <65000000>;
543				hactive = <1024>;
544				vactive = <768>;
545				hback-porch = <220>;
546				hfront-porch = <40>;
547				vback-porch = <21>;
548				vfront-porch = <7>;
549				hsync-len = <60>;
550				vsync-len = <10>;
551			};
552		};
553	};
554};
555
556&pcie {
557	pinctrl-names = "default";
558	pinctrl-0 = <&pinctrl_pcie>;
559	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
560	status = "okay";
561};
562
563&pwm1 {
564	pinctrl-names = "default";
565	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
566	status = "disabled";
567};
568
569&pwm2 {
570	pinctrl-names = "default";
571	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
572	status = "disabled";
573};
574
575&pwm3 {
576	pinctrl-names = "default";
577	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
578	status = "disabled";
579};
580
581&pwm4 {
582	#pwm-cells = <2>;
583	pinctrl-names = "default", "state_dio";
584	pinctrl-0 = <&pinctrl_pwm4_backlight>;
585	pinctrl-1 = <&pinctrl_pwm4_dio>;
586	status = "okay";
587};
588
589&ssi1 {
590	status = "okay";
591};
592
593&ssi2 {
594	status = "okay";
595};
596
597&uart1 {
598	pinctrl-names = "default";
599	pinctrl-0 = <&pinctrl_uart1>;
600	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
601	status = "okay";
602};
603
604&uart2 {
605	pinctrl-names = "default";
606	pinctrl-0 = <&pinctrl_uart2>;
607	status = "okay";
608};
609
610&uart5 {
611	pinctrl-names = "default";
612	pinctrl-0 = <&pinctrl_uart5>;
613	status = "okay";
614};
615
616&usbotg {
617	vbus-supply = <&reg_usb_otg_vbus>;
618	pinctrl-names = "default";
619	pinctrl-0 = <&pinctrl_usbotg>;
620	disable-over-current;
621	status = "okay";
622};
623
624&usbh1 {
625	vbus-supply = <&reg_usb_h1_vbus>;
626	status = "okay";
627};
628
629&usdhc3 {
630	pinctrl-names = "default", "state_100mhz", "state_200mhz";
631	pinctrl-0 = <&pinctrl_usdhc3>;
632	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
633	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
634	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
635	vmmc-supply = <&reg_3p3v>;
636	no-1-8-v; /* firmware will remove if board revision supports */
637	status = "okay";
638};
639
640&wdog1 {
641	status = "disabled";
642};
643
644&wdog2 {
645	pinctrl-names = "default";
646	pinctrl-0 = <&pinctrl_wdog>;
647	fsl,ext-reset-output;
648	status = "okay";
649};
650
651&iomuxc {
652	pinctrl_audmux: audmuxgrp {
653		fsl,pins = <
654			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
655			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
656			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
657			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
658			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0 /* AUD4_MCK */
659			MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
660			MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
661			MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
662		>;
663	};
664
665	pinctrl_enet: enetgrp {
666		fsl,pins = <
667			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
668			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
669			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
670			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
671			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
672			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
673			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
674			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
675			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
676			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
677			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
678			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
679			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
680			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
681			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
682			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
683		>;
684	};
685
686	pinctrl_ecspi2: escpi2grp {
687		fsl,pins = <
688			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
689			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
690			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
691			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
692		>;
693	};
694
695	pinctrl_flexcan1: flexcan1grp {
696		fsl,pins = <
697			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
698			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
699		>;
700	};
701
702	pinctrl_gpio_leds: gpioledsgrp {
703		fsl,pins = <
704			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
705			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
706			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
707		>;
708	};
709
710	pinctrl_gpmi_nand: gpminandgrp {
711		fsl,pins = <
712			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
713			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
714			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
715			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
716			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
717			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
718			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
719			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
720			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
721			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
722			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
723			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
724			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
725			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
726			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
727		>;
728	};
729
730	pinctrl_i2c1: i2c1grp {
731		fsl,pins = <
732			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
733			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
734			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
735		>;
736	};
737
738	pinctrl_i2c2: i2c2grp {
739		fsl,pins = <
740			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
741			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
742		>;
743	};
744
745	pinctrl_i2c3: i2c3grp {
746		fsl,pins = <
747			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
748			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
749		>;
750	};
751
752	pinctrl_pcie: pciegrp {
753		fsl,pins = <
754			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0 /* PCIE IRQ */
755			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE RST */
756		>;
757	};
758
759	pinctrl_pps: ppsgrp {
760		fsl,pins = <
761			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
762		>;
763	};
764
765	pinctrl_pwm1: pwm1grp {
766		fsl,pins = <
767			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
768		>;
769	};
770
771	pinctrl_pwm2: pwm2grp {
772		fsl,pins = <
773			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
774		>;
775	};
776
777	pinctrl_pwm3: pwm3grp {
778		fsl,pins = <
779			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
780		>;
781	};
782
783	pinctrl_pwm4_backlight: pwm4grpbacklight {
784		fsl,pins = <
785			/* LVDS_PWM J6.5 */
786			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
787		>;
788	};
789
790	pinctrl_pwm4_dio: pwm4grpdio {
791		fsl,pins = <
792			/* DIO3 J16.4 */
793			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
794		>;
795	};
796
797	pinctrl_reg_can1: regcan1grp {
798		fsl,pins = <
799			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0 /* CAN_STBY */
800		>;
801	};
802
803	pinctrl_uart1: uart1grp {
804		fsl,pins = <
805			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
806			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
807			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
808		>;
809	};
810
811	pinctrl_uart2: uart2grp {
812		fsl,pins = <
813			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
814			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
815		>;
816	};
817
818	pinctrl_uart5: uart5grp {
819		fsl,pins = <
820			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
821			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
822		>;
823	};
824
825	pinctrl_usbotg: usbotggrp {
826		fsl,pins = <
827			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
828			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
829			MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x17059
830		>;
831	};
832
833	pinctrl_usdhc3: usdhc3grp {
834		fsl,pins = <
835			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
836			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
837			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
838			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
839			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
840			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
841			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
842			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
843		>;
844	};
845
846	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
847		fsl,pins = <
848			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
849			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
850			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
851			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
852			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
853			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
854			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
855			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
856		>;
857	};
858
859	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
860		fsl,pins = <
861			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
862			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
863			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
864			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
865			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
866			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
867			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
868			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
869		>;
870	};
871
872	pinctrl_wdog: wdoggrp {
873		fsl,pins = <
874			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
875		>;
876	};
877};
878