1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		nand = &gpmi;
17		ssi0 = &ssi1;
18		usb0 = &usbh1;
19		usb1 = &usbotg;
20	};
21
22	chosen {
23		bootargs = "console=ttymxc1,115200";
24	};
25
26	backlight {
27		compatible = "pwm-backlight";
28		pwms = <&pwm4 0 5000000>;
29		brightness-levels = <0 4 8 16 32 64 128 255>;
30		default-brightness-level = <7>;
31	};
32
33	gpio-keys {
34		compatible = "gpio-keys";
35
36		user-pb {
37			label = "user_pb";
38			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
39			linux,code = <BTN_0>;
40		};
41
42		user-pb1x {
43			label = "user_pb1x";
44			linux,code = <BTN_1>;
45			interrupt-parent = <&gsc>;
46			interrupts = <0>;
47		};
48
49		key-erased {
50			label = "key-erased";
51			linux,code = <BTN_2>;
52			interrupt-parent = <&gsc>;
53			interrupts = <1>;
54		};
55
56		eeprom-wp {
57			label = "eeprom_wp";
58			linux,code = <BTN_3>;
59			interrupt-parent = <&gsc>;
60			interrupts = <2>;
61		};
62
63		tamper {
64			label = "tamper";
65			linux,code = <BTN_4>;
66			interrupt-parent = <&gsc>;
67			interrupts = <5>;
68		};
69
70		switch-hold {
71			label = "switch_hold";
72			linux,code = <BTN_5>;
73			interrupt-parent = <&gsc>;
74			interrupts = <7>;
75		};
76	};
77
78	leds {
79		compatible = "gpio-leds";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_gpio_leds>;
82
83		led0: led-user1 {
84			label = "user1";
85			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
86			default-state = "on";
87			linux,default-trigger = "heartbeat";
88		};
89
90		led1: led-user2 {
91			label = "user2";
92			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93			default-state = "off";
94		};
95
96		led2: led-user3 {
97			label = "user3";
98			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99			default-state = "off";
100		};
101	};
102
103	memory@10000000 {
104		device_type = "memory";
105		reg = <0x10000000 0x20000000>;
106	};
107
108	pps {
109		compatible = "pps-gpio";
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_pps>;
112		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
113		status = "okay";
114	};
115
116	reg_1p0v: regulator-1p0v {
117		compatible = "regulator-fixed";
118		regulator-name = "1P0V";
119		regulator-min-microvolt = <1000000>;
120		regulator-max-microvolt = <1000000>;
121		regulator-always-on;
122	};
123
124	reg_3p3v: regulator-3p3v {
125		compatible = "regulator-fixed";
126		regulator-name = "3P3V";
127		regulator-min-microvolt = <3300000>;
128		regulator-max-microvolt = <3300000>;
129		regulator-always-on;
130	};
131
132	reg_5p0v: regulator-5p0v {
133		compatible = "regulator-fixed";
134		regulator-name = "5P0V";
135		regulator-min-microvolt = <5000000>;
136		regulator-max-microvolt = <5000000>;
137		regulator-always-on;
138	};
139
140	reg_can1_stby: regulator-can1-stby {
141		compatible = "regulator-fixed";
142		pinctrl-names = "default";
143		pinctrl-0 = <&pinctrl_reg_can1>;
144		regulator-name = "can1_stby";
145		gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
146		regulator-min-microvolt = <3300000>;
147		regulator-max-microvolt = <3300000>;
148	};
149
150	reg_usb_otg_vbus: regulator-usb-otg-vbus {
151		compatible = "regulator-fixed";
152		regulator-name = "usb_otg_vbus";
153		regulator-min-microvolt = <5000000>;
154		regulator-max-microvolt = <5000000>;
155		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
156		enable-active-high;
157	};
158
159	sound {
160		compatible = "fsl,imx6q-ventana-sgtl5000",
161			     "fsl,imx-audio-sgtl5000";
162		model = "sgtl5000-audio";
163		ssi-controller = <&ssi1>;
164		audio-codec = <&codec>;
165		audio-routing =
166			"MIC_IN", "Mic Jack",
167			"Mic Jack", "Mic Bias",
168			"Headphone Jack", "HP_OUT";
169		mux-int-port = <1>;
170		mux-ext-port = <4>;
171	};
172};
173
174&audmux {
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_audmux>;
177	status = "okay";
178};
179
180&can1 {
181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_flexcan1>;
183	xceiver-supply = <&reg_can1_stby>;
184	status = "okay";
185};
186
187&clks {
188	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
189			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
190	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
191				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
192};
193
194&ecspi3 {
195	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_ecspi3>;
198	status = "okay";
199};
200
201&fec {
202	pinctrl-names = "default";
203	pinctrl-0 = <&pinctrl_enet>;
204	phy-mode = "rgmii-id";
205	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
206	status = "okay";
207};
208
209&gpmi {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_gpmi_nand>;
212	status = "okay";
213};
214
215&hdmi {
216	ddc-i2c-bus = <&i2c3>;
217	status = "okay";
218};
219
220&i2c1 {
221	clock-frequency = <100000>;
222	pinctrl-names = "default";
223	pinctrl-0 = <&pinctrl_i2c1>;
224	status = "okay";
225
226	gsc: gsc@20 {
227		compatible = "gw,gsc";
228		reg = <0x20>;
229		interrupt-parent = <&gpio1>;
230		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
231		interrupt-controller;
232		#interrupt-cells = <1>;
233		#size-cells = <0>;
234
235		adc {
236			compatible = "gw,gsc-adc";
237			#address-cells = <1>;
238			#size-cells = <0>;
239
240			channel@0 {
241				gw,mode = <0>;
242				reg = <0x00>;
243				label = "temp";
244			};
245
246			channel@2 {
247				gw,mode = <1>;
248				reg = <0x02>;
249				label = "vdd_vin";
250			};
251
252			channel@5 {
253				gw,mode = <1>;
254				reg = <0x05>;
255				label = "vdd_3p3";
256			};
257
258			channel@8 {
259				gw,mode = <1>;
260				reg = <0x08>;
261				label = "vdd_bat";
262			};
263
264			channel@b {
265				gw,mode = <1>;
266				reg = <0x0b>;
267				label = "vdd_5p0";
268			};
269
270			channel@e {
271				gw,mode = <1>;
272				reg = <0xe>;
273				label = "vdd_arm";
274			};
275
276			channel@11 {
277				gw,mode = <1>;
278				reg = <0x11>;
279				label = "vdd_soc";
280			};
281
282			channel@14 {
283				gw,mode = <1>;
284				reg = <0x14>;
285				label = "vdd_3p0";
286			};
287
288			channel@17 {
289				gw,mode = <1>;
290				reg = <0x17>;
291				label = "vdd_1p5";
292			};
293
294			channel@1d {
295				gw,mode = <1>;
296				reg = <0x1d>;
297				label = "vdd_1p8";
298			};
299
300			channel@20 {
301				gw,mode = <1>;
302				reg = <0x20>;
303				label = "vdd_1p0";
304			};
305
306			channel@23 {
307				gw,mode = <1>;
308				reg = <0x23>;
309				label = "vdd_2p5";
310			};
311
312			channel@29 {
313				gw,mode = <1>;
314				reg = <0x29>;
315				label = "vdd_an1";
316			};
317		};
318	};
319
320	gsc_gpio: gpio@23 {
321		compatible = "nxp,pca9555";
322		reg = <0x23>;
323		gpio-controller;
324		#gpio-cells = <2>;
325		interrupt-parent = <&gsc>;
326		interrupts = <4>;
327	};
328
329	eeprom1: eeprom@50 {
330		compatible = "atmel,24c02";
331		reg = <0x50>;
332		pagesize = <16>;
333	};
334
335	eeprom2: eeprom@51 {
336		compatible = "atmel,24c02";
337		reg = <0x51>;
338		pagesize = <16>;
339	};
340
341	eeprom3: eeprom@52 {
342		compatible = "atmel,24c02";
343		reg = <0x52>;
344		pagesize = <16>;
345	};
346
347	eeprom4: eeprom@53 {
348		compatible = "atmel,24c02";
349		reg = <0x53>;
350		pagesize = <16>;
351	};
352
353	rtc: ds1672@68 {
354		compatible = "dallas,ds1672";
355		reg = <0x68>;
356	};
357};
358
359&i2c2 {
360	clock-frequency = <100000>;
361	pinctrl-names = "default";
362	pinctrl-0 = <&pinctrl_i2c2>;
363	status = "okay";
364
365	ltc3676: pmic@3c {
366		compatible = "lltc,ltc3676";
367		reg = <0x3c>;
368		pinctrl-names = "default";
369		pinctrl-0 = <&pinctrl_pmic>;
370		interrupt-parent = <&gpio1>;
371		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
372
373		regulators {
374			/* VDD_SOC (1+R1/R2 = 1.635) */
375			reg_vdd_soc: sw1 {
376				regulator-name = "vddsoc";
377				regulator-min-microvolt = <674400>;
378				regulator-max-microvolt = <1308000>;
379				lltc,fb-voltage-divider = <127000 200000>;
380				regulator-ramp-delay = <7000>;
381				regulator-boot-on;
382				regulator-always-on;
383			};
384
385			/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
386			reg_1p8v: sw2 {
387				regulator-name = "vdd1p8";
388				regulator-min-microvolt = <1033310>;
389				regulator-max-microvolt = <2004000>;
390				lltc,fb-voltage-divider = <301000 200000>;
391				regulator-ramp-delay = <7000>;
392				regulator-boot-on;
393				regulator-always-on;
394			};
395
396			/* VDD_ARM (1+R1/R2 = 1.635) */
397			reg_vdd_arm: sw3 {
398				regulator-name = "vddarm";
399				regulator-min-microvolt = <674400>;
400				regulator-max-microvolt = <1308000>;
401				lltc,fb-voltage-divider = <127000 200000>;
402				regulator-ramp-delay = <7000>;
403				regulator-boot-on;
404				regulator-always-on;
405			};
406
407			/* VDD_DDR (1+R1/R2 = 2.105) */
408			reg_vdd_ddr: sw4 {
409				regulator-name = "vddddr";
410				regulator-min-microvolt = <868310>;
411				regulator-max-microvolt = <1684000>;
412				lltc,fb-voltage-divider = <221000 200000>;
413				regulator-ramp-delay = <7000>;
414				regulator-boot-on;
415				regulator-always-on;
416			};
417
418			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
419			reg_2p5v: ldo2 {
420				regulator-name = "vdd2p5";
421				regulator-min-microvolt = <2490375>;
422				regulator-max-microvolt = <2490375>;
423				lltc,fb-voltage-divider = <487000 200000>;
424				regulator-boot-on;
425				regulator-always-on;
426			};
427
428			/* VDD_AUD_1P8: Audio codec */
429			reg_aud_1p8v: ldo3 {
430				regulator-name = "vdd1p8a";
431				regulator-min-microvolt = <1800000>;
432				regulator-max-microvolt = <1800000>;
433				regulator-boot-on;
434			};
435
436			/* VDD_HIGH (1+R1/R2 = 4.17) */
437			reg_3p0v: ldo4 {
438				regulator-name = "vdd3p0";
439				regulator-min-microvolt = <3023250>;
440				regulator-max-microvolt = <3023250>;
441				lltc,fb-voltage-divider = <634000 200000>;
442				regulator-boot-on;
443				regulator-always-on;
444			};
445		};
446	};
447};
448
449&i2c3 {
450	clock-frequency = <100000>;
451	pinctrl-names = "default";
452	pinctrl-0 = <&pinctrl_i2c3>;
453	status = "okay";
454
455	codec: sgtl5000@a {
456		compatible = "fsl,sgtl5000";
457		reg = <0x0a>;
458		#sound-dai-cells = <0>;
459		clocks = <&clks IMX6QDL_CLK_CKO>;
460		VDDA-supply = <&reg_1p8v>;
461		VDDIO-supply = <&reg_3p3v>;
462	};
463
464	touchscreen: egalax_ts@4 {
465		compatible = "eeti,egalax_ts";
466		reg = <0x04>;
467		interrupt-parent = <&gpio7>;
468		interrupts = <12 2>;
469		wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
470	};
471
472	accel@1e {
473		compatible = "nxp,fxos8700";
474		reg = <0x1e>;
475	};
476};
477
478&ldb {
479	status = "okay";
480
481	lvds-channel@0 {
482		fsl,data-mapping = "spwg";
483		fsl,data-width = <18>;
484		status = "okay";
485
486		display-timings {
487			native-mode = <&timing0>;
488			timing0: hsd100pxn1 {
489				clock-frequency = <65000000>;
490				hactive = <1024>;
491				vactive = <768>;
492				hback-porch = <220>;
493				hfront-porch = <40>;
494				vback-porch = <21>;
495				vfront-porch = <7>;
496				hsync-len = <60>;
497				vsync-len = <10>;
498			};
499		};
500	};
501};
502
503&pcie {
504	pinctrl-names = "default";
505	pinctrl-0 = <&pinctrl_pcie>;
506	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
507	status = "okay";
508};
509
510&pwm2 {
511	pinctrl-names = "default";
512	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
513	status = "disabled";
514};
515
516&pwm3 {
517	pinctrl-names = "default";
518	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
519	status = "disabled";
520};
521
522&pwm4 {
523	#pwm-cells = <2>;
524	pinctrl-names = "default";
525	pinctrl-0 = <&pinctrl_pwm4>;
526	status = "okay";
527};
528
529&ssi1 {
530	status = "okay";
531};
532
533&uart1 {
534	pinctrl-names = "default";
535	pinctrl-0 = <&pinctrl_uart1>;
536	rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
537	status = "okay";
538};
539
540&uart2 {
541	pinctrl-names = "default";
542	pinctrl-0 = <&pinctrl_uart2>;
543	status = "okay";
544};
545
546&uart5 {
547	pinctrl-names = "default";
548	pinctrl-0 = <&pinctrl_uart5>;
549	status = "okay";
550};
551
552&usbotg {
553	vbus-supply = <&reg_usb_otg_vbus>;
554	pinctrl-names = "default";
555	pinctrl-0 = <&pinctrl_usbotg>;
556	disable-over-current;
557	status = "okay";
558};
559
560&usbh1 {
561	status = "okay";
562};
563
564&usdhc3 {
565	pinctrl-names = "default", "state_100mhz", "state_200mhz";
566	pinctrl-0 = <&pinctrl_usdhc3>;
567	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
568	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
569	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
570	vmmc-supply = <&reg_3p3v>;
571	no-1-8-v; /* firmware will remove if board revision supports */
572	status = "okay";
573};
574
575&wdog1 {
576	pinctrl-names = "default";
577	pinctrl-0 = <&pinctrl_wdog>;
578	fsl,ext-reset-output;
579};
580
581&iomuxc {
582	pinctrl_audmux: audmuxgrp {
583		fsl,pins = <
584			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
585			MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
586			MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
587			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
588			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x130b0 /* AUD4_MCK */
589		>;
590	};
591
592	pinctrl_ecspi3: escpi3grp {
593		fsl,pins = <
594			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
595			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
596			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
597			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x100b1
598		>;
599	};
600
601	pinctrl_enet: enetgrp {
602		fsl,pins = <
603			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
604			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
605			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
606			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
607			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
608			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
609			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
610			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
611			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
612			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
613			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
614			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
615			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
616			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
617			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
618			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
619			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0 /* PHY Reset */
620		>;
621	};
622
623	pinctrl_flexcan1: flexcan1grp {
624		fsl,pins = <
625			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
626			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
627		>;
628	};
629
630	pinctrl_gpio_leds: gpioledsgrp {
631		fsl,pins = <
632			MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
633			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
634			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
635		>;
636	};
637
638	pinctrl_gpmi_nand: gpminandgrp {
639		fsl,pins = <
640			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
641			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
642			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
643			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
644			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
645			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
646			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
647			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
648			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
649			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
650			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
651			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
652			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
653			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
654			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
655		>;
656	};
657
658	pinctrl_i2c1: i2c1grp {
659		fsl,pins = <
660			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
661			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
662			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
663		>;
664	};
665
666	pinctrl_i2c2: i2c2grp {
667		fsl,pins = <
668			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
669			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
670		>;
671	};
672
673	pinctrl_i2c3: i2c3grp {
674		fsl,pins = <
675			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
676			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
677		>;
678	};
679
680	pinctrl_pcie: pciegrp {
681		fsl,pins = <
682			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0 /* PCIE_RST# */
683		>;
684	};
685
686	pinctrl_pmic: pmicgrp {
687		fsl,pins = <
688			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0001b0b0 /* PMIC_IRQ# */
689		>;
690	};
691
692	pinctrl_pps: ppsgrp {
693		fsl,pins = <
694			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
695		>;
696	};
697
698	pinctrl_pwm2: pwm2grp {
699		fsl,pins = <
700			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
701		>;
702	};
703
704	pinctrl_pwm3: pwm3grp {
705		fsl,pins = <
706			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
707		>;
708	};
709
710	pinctrl_pwm4: pwm4grp {
711		fsl,pins = <
712			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
713		>;
714	};
715
716	pinctrl_reg_can1: regcan1grp {
717		fsl,pins = <
718			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x4001b0b0 /* CAN_STBY */
719		>;
720	};
721
722	pinctrl_uart1: uart1grp {
723		fsl,pins = <
724			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
725			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
726			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x4001b0b1 /* TEN */
727		>;
728	};
729
730	pinctrl_uart2: uart2grp {
731		fsl,pins = <
732			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
733			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
734		>;
735	};
736
737	pinctrl_uart5: uart5grp {
738		fsl,pins = <
739			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
740			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
741		>;
742	};
743
744	pinctrl_usbotg: usbotggrp {
745		fsl,pins = <
746			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
747			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x1b0b0 /* OTG_PWR_EN */
748			MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x17059
749		>;
750	};
751
752	pinctrl_usdhc3: usdhc3grp {
753		fsl,pins = <
754			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
755			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
756			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
757			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
758			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
759			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
760			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
761			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
762		>;
763	};
764
765	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
766		fsl,pins = <
767			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
768			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x170b9
769			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
770			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
771			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
772			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
773			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
774			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
775		>;
776	};
777
778	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
779		fsl,pins = <
780			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
781			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
782			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
783			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
784			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
785			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
786			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
787			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
788		>;
789	};
790
791	pinctrl_wdog: wdoggrp {
792		fsl,pins = <
793			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
794		>;
795	};
796};
797