xref: /openbmc/linux/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi (revision e2942062) 
1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6dl-pinfunc.h"
7#include "imx6qdl.dtsi"
8
9/ {
10	aliases {
11		i2c3 = &i2c4;
12	};
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a9";
20			device_type = "cpu";
21			reg = <0>;
22			next-level-cache = <&L2>;
23			operating-points = <
24				/* kHz    uV */
25				996000  1250000
26				792000  1175000
27				396000  1150000
28			>;
29			fsl,soc-operating-points = <
30				/* ARM kHz  SOC-PU uV */
31				996000	1175000
32				792000	1175000
33				396000	1175000
34			>;
35			clock-latency = <61036>; /* two CLK32 periods */
36			#cooling-cells = <2>;
37			clocks = <&clks IMX6QDL_CLK_ARM>,
38				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39				 <&clks IMX6QDL_CLK_STEP>,
40				 <&clks IMX6QDL_CLK_PLL1_SW>,
41				 <&clks IMX6QDL_CLK_PLL1_SYS>;
42			clock-names = "arm", "pll2_pfd2_396m", "step",
43				      "pll1_sw", "pll1_sys";
44			arm-supply = <&reg_arm>;
45			pu-supply = <&reg_pu>;
46			soc-supply = <&reg_soc>;
47			nvmem-cells = <&cpu_speed_grade>;
48			nvmem-cell-names = "speed_grade";
49		};
50
51		cpu@1 {
52			compatible = "arm,cortex-a9";
53			device_type = "cpu";
54			reg = <1>;
55			next-level-cache = <&L2>;
56			operating-points = <
57				/* kHz    uV */
58				996000  1250000
59				792000  1175000
60				396000  1150000
61			>;
62			fsl,soc-operating-points = <
63				/* ARM kHz  SOC-PU uV */
64				996000	1175000
65				792000	1175000
66				396000	1175000
67			>;
68			clock-latency = <61036>; /* two CLK32 periods */
69			#cooling-cells = <2>;
70			clocks = <&clks IMX6QDL_CLK_ARM>,
71				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
72				 <&clks IMX6QDL_CLK_STEP>,
73				 <&clks IMX6QDL_CLK_PLL1_SW>,
74				 <&clks IMX6QDL_CLK_PLL1_SYS>;
75			clock-names = "arm", "pll2_pfd2_396m", "step",
76				      "pll1_sw", "pll1_sys";
77			arm-supply = <&reg_arm>;
78			pu-supply = <&reg_pu>;
79			soc-supply = <&reg_soc>;
80		};
81	};
82
83	soc: soc {
84		ocram: sram@900000 {
85			compatible = "mmio-sram";
86			reg = <0x00900000 0x20000>;
87			ranges = <0 0x00900000 0x20000>;
88			#address-cells = <1>;
89			#size-cells = <1>;
90			clocks = <&clks IMX6QDL_CLK_OCRAM>;
91		};
92
93		aips1: bus@2000000 {
94			pxp: pxp@20f0000 {
95				reg = <0x020f0000 0x4000>;
96				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
97			};
98
99			epdc: epdc@20f4000 {
100				reg = <0x020f4000 0x4000>;
101				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
102			};
103		};
104
105		aips2: bus@2100000 {
106			i2c4: i2c@21f8000 {
107				#address-cells = <1>;
108				#size-cells = <0>;
109				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
110				reg = <0x021f8000 0x4000>;
111				interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
112				clocks = <&clks IMX6DL_CLK_I2C4>;
113				status = "disabled";
114			};
115		};
116	};
117
118	capture-subsystem {
119		compatible = "fsl,imx-capture-subsystem";
120		ports = <&ipu1_csi0>, <&ipu1_csi1>;
121	};
122
123	display-subsystem {
124		compatible = "fsl,imx-display-subsystem";
125		ports = <&ipu1_di0>, <&ipu1_di1>;
126	};
127};
128
129&gpio1 {
130	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
131		      <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
132		      <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
133		      <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
134		      <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
135		      <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
136		      <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
137};
138
139&gpio2 {
140	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
141		      <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
142		      <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
143		      <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
144		      <&iomuxc 28 113 4>;
145};
146
147&gpio3 {
148	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
149		      <&iomuxc 16 81 16>;
150};
151
152&gpio4 {
153	gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
154		      <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
155		      <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
156		      <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
157		      <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
158};
159
160&gpio5 {
161	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
162		      <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
163		      <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
164		      <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
165};
166
167&gpio6 {
168	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
169		      <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
170		      <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
171		      <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
172		      <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
173		      <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
174};
175
176&gpio7 {
177	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
178		      <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
179		      <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
180};
181
182&gpr {
183	ipu1_csi0_mux {
184		compatible = "video-mux";
185		mux-controls = <&mux 0>;
186		#address-cells = <1>;
187		#size-cells = <0>;
188
189		port@0 {
190			reg = <0>;
191
192			ipu1_csi0_mux_from_mipi_vc0: endpoint {
193				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
194			};
195		};
196
197		port@1 {
198			reg = <1>;
199
200			ipu1_csi0_mux_from_mipi_vc1: endpoint {
201				remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
202			};
203		};
204
205		port@2 {
206			reg = <2>;
207
208			ipu1_csi0_mux_from_mipi_vc2: endpoint {
209				remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
210			};
211		};
212
213		port@3 {
214			reg = <3>;
215
216			ipu1_csi0_mux_from_mipi_vc3: endpoint {
217				remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
218			};
219		};
220
221		port@4 {
222			reg = <4>;
223
224			ipu1_csi0_mux_from_parallel_sensor: endpoint {
225			};
226		};
227
228		port@5 {
229			reg = <5>;
230
231			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
232				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
233			};
234		};
235	};
236
237	ipu1_csi1_mux {
238		compatible = "video-mux";
239		mux-controls = <&mux 1>;
240		#address-cells = <1>;
241		#size-cells = <0>;
242
243		port@0 {
244			reg = <0>;
245
246			ipu1_csi1_mux_from_mipi_vc0: endpoint {
247				remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
248			};
249		};
250
251		port@1 {
252			reg = <1>;
253
254			ipu1_csi1_mux_from_mipi_vc1: endpoint {
255				remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
256			};
257		};
258
259		port@2 {
260			reg = <2>;
261
262			ipu1_csi1_mux_from_mipi_vc2: endpoint {
263				remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
264			};
265		};
266
267		port@3 {
268			reg = <3>;
269
270			ipu1_csi1_mux_from_mipi_vc3: endpoint {
271				remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
272			};
273		};
274
275		port@4 {
276			reg = <4>;
277
278			ipu1_csi1_mux_from_parallel_sensor: endpoint {
279			};
280		};
281
282		port@5 {
283			reg = <5>;
284
285			ipu1_csi1_mux_to_ipu1_csi1: endpoint {
286				remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
287			};
288		};
289	};
290};
291
292&gpt {
293	compatible = "fsl,imx6dl-gpt";
294};
295
296&hdmi {
297	compatible = "fsl,imx6dl-hdmi";
298};
299
300&iomuxc {
301	compatible = "fsl,imx6dl-iomuxc";
302};
303
304&ipu1_csi1 {
305	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
306		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
307	};
308};
309
310&ldb {
311	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
312		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
313		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
314	clock-names = "di0_pll", "di1_pll",
315		      "di0_sel", "di1_sel",
316		      "di0", "di1";
317};
318
319&mipi_csi {
320	port@1 {
321		reg = <1>;
322		#address-cells = <1>;
323		#size-cells = <0>;
324
325		mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
326			reg = <0>;
327			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
328		};
329
330		mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
331			reg = <1>;
332			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
333		};
334	};
335
336	port@2 {
337		reg = <2>;
338		#address-cells = <1>;
339		#size-cells = <0>;
340
341		mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
342			reg = <0>;
343			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
344		};
345
346		mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
347			reg = <1>;
348			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
349		};
350	};
351
352	port@3 {
353		reg = <3>;
354		#address-cells = <1>;
355		#size-cells = <0>;
356
357		mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
358			reg = <0>;
359			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
360		};
361
362		mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
363			reg = <1>;
364			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
365		};
366	};
367
368	port@4 {
369		reg = <4>;
370		#address-cells = <1>;
371		#size-cells = <0>;
372
373		mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
374			reg = <0>;
375			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
376		};
377
378		mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
379			reg = <1>;
380			remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
381		};
382	};
383};
384
385&mux {
386	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
387			<0x34 0x00000038>, /* IPU_CSI1_MUX */
388			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
389			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
390			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
391			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
392			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
393};
394
395&vpu {
396	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
397};
398