1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2016 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include <dt-bindings/display/sdtv-standards.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/media/tvp5150.h>
13#include <dt-bindings/sound/fsl-imx-audmux.h>
14#include "imx6dl.dtsi"
15
16/ {
17	model = "Protonic MVT board";
18	compatible = "prt,prtmvt", "fsl,imx6dl";
19
20	chosen {
21		stdout-path = &uart4;
22	};
23
24	backlight: backlight {
25		compatible = "pwm-backlight";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_backlight>;
28		pwms = <&pwm1 0 5000000 0>;
29		brightness-levels = <0 16 64 255>;
30		num-interpolated-steps = <16>;
31		default-brightness-level = <1>;
32		power-supply = <&reg_3v3>;
33		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
34	};
35
36	connector {
37		compatible = "composite-video-connector";
38		label = "Composite0";
39		sdtv-standards = <SDTV_STD_PAL_B>;
40
41		port {
42			comp0_out: endpoint {
43				remote-endpoint = <&tvp5150_comp0_in>;
44			};
45		};
46	};
47
48	gpio-keys {
49		compatible = "gpio-keys";
50		pinctrl-names = "default";
51		pinctrl-0 = <&pinctrl_gpiokeys>;
52		autorepeat;
53
54		key-power {
55			label = "Power Button";
56			gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
57			linux,code = <KEY_POWER>;
58			wakeup-source;
59		};
60
61		key-f1 {
62			label = "GPIO Key F1";
63			linux,code = <KEY_F1>;
64			gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
65		};
66
67		key-f2 {
68			label = "GPIO Key F2";
69			linux,code = <KEY_F2>;
70			gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
71		};
72
73		key-f3 {
74			label = "GPIO Key F3";
75			linux,code = <KEY_F3>;
76			gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
77		};
78
79		key-f4 {
80			label = "GPIO Key F4";
81			linux,code = <KEY_F4>;
82			gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
83		};
84
85		key-f5 {
86			label = "GPIO Key F5";
87			linux,code = <KEY_F5>;
88			gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
89		};
90
91		key-cycle {
92			label = "GPIO Key CYCLE";
93			linux,code = <KEY_CYCLEWINDOWS>;
94			gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
95		};
96
97		key-esc {
98			label = "GPIO Key ESC";
99			linux,code = <KEY_ESC>;
100			gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
101		};
102
103		key-up {
104			label = "GPIO Key UP";
105			linux,code = <KEY_UP>;
106			gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
107		};
108
109		key-down {
110			label = "GPIO Key DOWN";
111			linux,code = <KEY_DOWN>;
112			gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
113		};
114
115		key-ok {
116			label = "GPIO Key OK";
117			linux,code = <KEY_OK>;
118			gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
119		};
120
121		key-f6 {
122			label = "GPIO Key F6";
123			linux,code = <KEY_F6>;
124			gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
125		};
126
127		key-f7 {
128			label = "GPIO Key F7";
129			linux,code = <KEY_F7>;
130			gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
131		};
132
133		key-f8 {
134			label = "GPIO Key F8";
135			linux,code = <KEY_F8>;
136			gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
137		};
138
139		key-f9 {
140			label = "GPIO Key F9";
141			linux,code = <KEY_F9>;
142			gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
143		};
144
145		key-f10 {
146			label = "GPIO Key F10";
147			linux,code = <KEY_F10>;
148			gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
149		};
150
151	};
152
153	leds {
154		compatible = "gpio-leds";
155		pinctrl-names = "default";
156		pinctrl-0 = <&pinctrl_leds>;
157
158		led-0 {
159			label = "debug0";
160			function = LED_FUNCTION_HEARTBEAT;
161			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
162			linux,default-trigger = "heartbeat";
163		};
164
165		led-1 {
166			label = "debug1";
167			function = LED_FUNCTION_DISK;
168			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
169			linux,default-trigger = "disk-activity";
170		};
171
172		led-2 {
173			label = "power_led";
174			function = LED_FUNCTION_POWER;
175			gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
176			default-state = "on";
177		};
178	};
179
180	panel {
181		compatible = "kyo,tcg070wvlq", "lg,lb070wv8";
182		backlight = <&backlight>;
183		power-supply = <&reg_3v3>;
184
185		port {
186			panel_in: endpoint {
187				remote-endpoint = <&lvds0_out>;
188			};
189		};
190	};
191
192	clk50m_phy: phy-clock {
193		compatible = "fixed-clock";
194		#clock-cells = <0>;
195		clock-frequency = <50000000>;
196		clock-output-names = "enet_ref_pad";
197	};
198
199	reg_1v8: regulator-1v8 {
200		compatible = "regulator-fixed";
201		regulator-name = "1v8";
202		regulator-min-microvolt = <1800000>;
203		regulator-max-microvolt = <1800000>;
204	};
205
206	reg_3v3: regulator-3v3 {
207		compatible = "regulator-fixed";
208		regulator-name = "3v3";
209		regulator-min-microvolt = <3300000>;
210		regulator-max-microvolt = <3300000>;
211	};
212
213	reg_h1_vbus: regulator-h1-vbus {
214		compatible = "regulator-fixed";
215		regulator-name = "h1-vbus";
216		regulator-min-microvolt = <5000000>;
217		regulator-max-microvolt = <5000000>;
218		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
219		enable-active-high;
220	};
221
222	reg_otg_vbus: regulator-otg-vbus {
223		compatible = "regulator-fixed";
224		regulator-name = "otg-vbus";
225		regulator-min-microvolt = <5000000>;
226		regulator-max-microvolt = <5000000>;
227		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
228		enable-active-high;
229	};
230
231	sound {
232		compatible = "simple-audio-card";
233		simple-audio-card,name = "prti6q-sgtl5000";
234		simple-audio-card,format = "i2s";
235		simple-audio-card,widgets =
236			"Microphone", "Microphone Jack",
237			"Line", "Line In Jack",
238			"Headphone", "Headphone Jack",
239			"Speaker", "External Speaker";
240		simple-audio-card,routing =
241			"MIC_IN", "Microphone Jack",
242			"LINE_IN", "Line In Jack",
243			"Headphone Jack", "HP_OUT",
244			"External Speaker", "LINE_OUT";
245
246		simple-audio-card,cpu {
247			sound-dai = <&ssi1>;
248			system-clock-frequency = <0>;
249		};
250
251		simple-audio-card,codec {
252			sound-dai = <&codec>;
253			bitclock-master;
254			frame-master;
255		};
256	};
257};
258
259&audmux {
260	pinctrl-names = "default";
261	pinctrl-0 = <&pinctrl_audmux>;
262	status = "okay";
263
264	mux-ssi1 {
265		fsl,audmux-port = <0>;
266		fsl,port-config = <
267			IMX_AUDMUX_V2_PTCR_SYN		0
268			IMX_AUDMUX_V2_PTCR_TFSEL(2)	0
269			IMX_AUDMUX_V2_PTCR_TCSEL(2)	0
270			IMX_AUDMUX_V2_PTCR_TFSDIR	0
271			IMX_AUDMUX_V2_PTCR_TCLKDIR	IMX_AUDMUX_V2_PDCR_RXDSEL(2)
272		>;
273	};
274
275	mux-pins3 {
276		fsl,audmux-port = <2>;
277		fsl,port-config = <
278			IMX_AUDMUX_V2_PTCR_SYN		IMX_AUDMUX_V2_PDCR_RXDSEL(0)
279			0				IMX_AUDMUX_V2_PDCR_TXRXEN
280		>;
281	};
282};
283
284&can1 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_can1>;
287	status = "okay";
288};
289
290&can2 {
291	pinctrl-names = "default";
292	pinctrl-0 = <&pinctrl_can2>;
293	status = "okay";
294};
295
296&clks {
297	clocks = <&clk50m_phy>;
298	clock-names = "enet_ref_pad";
299	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
300	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>;
301};
302
303&ecspi1 {
304	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
305	pinctrl-names = "default";
306	pinctrl-0 = <&pinctrl_ecspi1>;
307	status = "okay";
308
309	flash@0 {
310		compatible = "jedec,spi-nor";
311		reg = <0>;
312		spi-max-frequency = <20000000>;
313	};
314};
315
316&fec {
317	pinctrl-names = "default";
318	pinctrl-0 = <&pinctrl_enet>;
319	phy-mode = "rmii";
320	phy-handle = <&rmii_phy>;
321	status = "okay";
322
323	mdio {
324		#address-cells = <1>;
325		#size-cells = <0>;
326
327		/* Microchip KSZ8081RNA PHY */
328		rmii_phy: ethernet-phy@0 {
329			reg = <0>;
330			interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
331			reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
332			reset-assert-us = <10000>;
333			reset-deassert-us = <3000>;
334		};
335	};
336};
337
338&gpio1 {
339	gpio-line-names =
340		"CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
341			"CAM2_MIRROR", "", "", "SMBALERT",
342		"DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
343		"SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
344			"SD1_DATA3", "", "",
345		"", "", "", "", "", "", "", "";
346};
347
348&gpio2 {
349	gpio-line-names =
350		"", "", "", "", "", "", "", "",
351		"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
352			"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
353		"", "", "", "", "", "", "", "ON_SWITCH",
354		"POWER_LED", "", "", "", "", "", "", "";
355};
356
357&gpio3 {
358	gpio-line-names =
359		"", "", "", "", "", "", "", "",
360		"", "", "", "", "", "", "", "",
361		"ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1",
362			"CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ",
363		"TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0",
364			"YACO_RESET";
365};
366
367&gpio4 {
368	gpio-line-names =
369		"", "", "", "", "", "", "", "",
370		"", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX",
371		"", "", "DIP1_FB", "", "", "", "", "",
372		"CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN",
373			"BL_PWM", "ETH_INTRP", "";
374};
375
376&gpio5 {
377	gpio-line-names =
378		"", "", "", "", "", "", "", "",
379		"", "", "", "", "", "", "", "",
380		"", "", "", "", "", "", "", "",
381		"I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
382			"YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
383};
384
385&i2c1 {
386	clock-frequency = <100000>;
387	pinctrl-names = "default";
388	pinctrl-0 = <&pinctrl_i2c1>;
389	status = "okay";
390
391	codec: audio-codec@a {
392		compatible = "fsl,sgtl5000";
393		reg = <0xa>;
394		#sound-dai-cells = <0>;
395		clocks = <&clks 201>;
396		VDDA-supply = <&reg_3v3>;
397		VDDIO-supply = <&reg_3v3>;
398		VDDD-supply = <&reg_1v8>;
399	};
400
401	video@5c {
402		compatible = "ti,tvp5150";
403		reg = <0x5c>;
404		#address-cells = <1>;
405		#size-cells = <0>;
406
407		port@0 {
408			reg = <0>;
409
410			tvp5150_comp0_in: endpoint {
411				remote-endpoint = <&comp0_out>;
412			};
413		};
414
415		/* Output port 2 is video output pad */
416		port@2 {
417			reg = <2>;
418			tvp5151_to_ipu1_csi0_mux: endpoint {
419				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
420			};
421		};
422	};
423
424	gpio_pca: gpio@74 {
425		compatible = "nxp,pca9539";
426		reg = <0x74>;
427		pinctrl-names = "default";
428		pinctrl-0 = <&pinctrl_pca9539>;
429		interrupt-parent = <&gpio4>;
430		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
431		gpio-controller;
432		#gpio-cells = <2>;
433	};
434
435	/* additional i2c devices are added automatically by the boot loader */
436};
437
438&i2c3 {
439	clock-frequency = <100000>;
440	pinctrl-names = "default";
441	pinctrl-0 = <&pinctrl_i2c3>;
442	status = "okay";
443
444	adc@49 {
445		compatible = "ti,ads1015";
446		reg = <0x49>;
447		#address-cells = <1>;
448		#size-cells = <0>;
449
450		channel@4 {
451			reg = <4>;
452			ti,gain = <3>;
453			ti,datarate = <3>;
454		};
455
456		channel@5 {
457			reg = <5>;
458			ti,gain = <3>;
459			ti,datarate = <3>;
460		};
461
462		channel@6 {
463			reg = <6>;
464			ti,gain = <3>;
465			ti,datarate = <3>;
466		};
467
468		channel@7 {
469			reg = <7>;
470			ti,gain = <3>;
471			ti,datarate = <3>;
472		};
473	};
474
475	rtc@51 {
476		compatible = "nxp,pcf8563";
477		reg = <0x51>;
478	};
479
480	temperature-sensor@70 {
481		compatible = "ti,tmp103";
482		reg = <0x70>;
483	};
484};
485
486&ipu1_csi0 {
487	pinctrl-names = "default";
488	pinctrl-0 = <&pinctrl_ipu1_csi0>;
489	status = "okay";
490};
491
492&ipu1_csi0_mux_from_parallel_sensor {
493	remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>;
494};
495
496&ldb {
497	status = "okay";
498
499	lvds-channel@0 {
500		status = "okay";
501
502		port@4 {
503			reg = <4>;
504
505			lvds0_out: endpoint {
506				remote-endpoint = <&panel_in>;
507			};
508		};
509	};
510};
511
512&pcie {
513	status = "okay";
514};
515
516&pwm1 {
517	pinctrl-names = "default";
518	pinctrl-0 = <&pinctrl_pwm1>;
519	status = "okay";
520};
521
522&ssi1 {
523	#sound-dai-cells = <0>;
524	fsl,mode = "ac97-slave";
525	status = "okay";
526};
527
528&uart1 {
529	pinctrl-names = "default";
530	pinctrl-0 = <&pinctrl_uart1>;
531	status = "okay";
532};
533
534&uart2 {
535	pinctrl-names = "default";
536	pinctrl-0 = <&pinctrl_uart2>;
537	status = "okay";
538};
539
540&uart3 {
541	pinctrl-names = "default";
542	pinctrl-0 = <&pinctrl_uart3>;
543	status = "okay";
544};
545
546&uart4 {
547	pinctrl-names = "default";
548	pinctrl-0 = <&pinctrl_uart4>;
549	status = "okay";
550};
551
552&uart5 {
553	pinctrl-names = "default";
554	pinctrl-0 = <&pinctrl_uart5>;
555	status = "okay";
556};
557
558&usbh1 {
559	vbus-supply = <&reg_h1_vbus>;
560	pinctrl-names = "default";
561	phy_type = "utmi";
562	dr_mode = "host";
563	disable-over-current;
564	status = "okay";
565};
566
567&usbotg {
568	vbus-supply = <&reg_otg_vbus>;
569	pinctrl-names = "default";
570	pinctrl-0 = <&pinctrl_usbotg>;
571	phy_type = "utmi";
572	dr_mode = "host";
573	over-current-active-low;
574	status = "okay";
575};
576
577&usbphynop1 {
578	status = "disabled";
579};
580
581&usbphynop2 {
582	status = "disabled";
583};
584
585&usdhc1 {
586	pinctrl-names = "default";
587	pinctrl-0 = <&pinctrl_usdhc1>;
588	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
589	no-1-8-v;
590	disable-wp;
591	cap-sd-highspeed;
592	no-mmc;
593	no-sdio;
594	status = "okay";
595};
596
597&usdhc3 {
598	pinctrl-names = "default";
599	pinctrl-0 = <&pinctrl_usdhc3>;
600	bus-width = <8>;
601	no-1-8-v;
602	non-removable;
603	no-sd;
604	no-sdio;
605	status = "okay";
606};
607
608&iomuxc {
609	pinctrl-names = "default";
610	pinctrl-0 = <&pinctrl_hog>;
611
612	pinctrl_audmux: audmuxgrp {
613		fsl,pins = <
614			/* SGTL5000 sys_mclk */
615			MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1			0x030b0
616			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD			0x130b0
617			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC			0x130b0
618			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD			0x110b0
619			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS			0x130b0
620		>;
621	};
622
623	pinctrl_backlight: backlightgrp {
624		fsl,pins = <
625			MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28		0x1b0b0
626		>;
627	};
628
629	pinctrl_can1: can1grp {
630		fsl,pins = <
631			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX		0x1b000
632			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX		0x3008
633			/* CAN1_SR */
634			MX6QDL_PAD_KEY_COL3__GPIO4_IO12			0x13008
635			/* CAN1_TERM */
636			MX6QDL_PAD_GPIO_0__GPIO1_IO00			0x1b088
637		>;
638	};
639
640	pinctrl_can2: can2grp {
641		fsl,pins = <
642			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX		0x1b000
643			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX		0x3008
644			/* CAN2_SR */
645			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13			0x13008
646		>;
647	};
648
649	pinctrl_ecspi1: ecspi1grp {
650		fsl,pins = <
651			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x100b1
652			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0x100b1
653			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0x100b1
654			/* CS */
655			MX6QDL_PAD_EIM_D19__GPIO3_IO19			0x000b1
656		>;
657	};
658
659	pinctrl_enet: enetgrp {
660		fsl,pins = <
661			/* MX6QDL_ENET_PINGRP4 */
662			MX6QDL_PAD_ENET_MDC__ENET_MDC			0x1b0b0
663			MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x1b0b0
664			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x1b0b0
665			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x1b0b0
666			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER		0x1b0b0
667			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x1b0b0
668			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x1b0b0
669			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x1b0b0
670			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x1b0b0
671			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0
672			/* Phy reset */
673			MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26		0x1b0b0
674			/* nINTRP */
675			MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30		0x1b0b0
676		>;
677	};
678
679	pinctrl_gpiokeys: gpiokeygrp {
680		fsl,pins = <
681			/* nON_SWITCH */
682			MX6QDL_PAD_EIM_CS0__GPIO2_IO23			0x1b0b0
683		>;
684	};
685
686	pinctrl_hog: hoggrp {
687		fsl,pins = <
688			/* ITU656_nRESET */
689			MX6QDL_PAD_GPIO_2__GPIO1_IO02			0x1b0b0
690			/* CAM1_MIRROR */
691			MX6QDL_PAD_GPIO_3__GPIO1_IO03			0x130b0
692			/* CAM2_MIRROR */
693			MX6QDL_PAD_GPIO_4__GPIO1_IO04			0x130b0
694			/* CAM_nDETECT */
695			MX6QDL_PAD_GPIO_17__GPIO7_IO12			0x1b0b0
696			/* ISB_IN1 */
697			MX6QDL_PAD_EIM_A16__GPIO2_IO22			0x130b0
698			/* ISB_nIN2 */
699			MX6QDL_PAD_EIM_A17__GPIO2_IO21			0x1b0b0
700			/* WARN_LIGHT */
701			MX6QDL_PAD_EIM_A19__GPIO2_IO19			0x100b0
702			/* ON2_FB */
703			MX6QDL_PAD_EIM_A25__GPIO5_IO02			0x100b0
704			/* YACO_nIRQ */
705			MX6QDL_PAD_EIM_D23__GPIO3_IO23			0x1b0b0
706			/* YACO_BOOT0 */
707			MX6QDL_PAD_EIM_D30__GPIO3_IO30			0x130b0
708			/* YACO_nRESET */
709			MX6QDL_PAD_EIM_D31__GPIO3_IO31			0x1b0b0
710			/* FORCE_ON1 */
711			MX6QDL_PAD_EIM_EB2__GPIO2_IO30			0x1b0b0
712			/* AUDIO_nRESET */
713			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21		0x1f0b0
714			/* ITU656_nPDN */
715			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20		0x1b0b0
716
717			/* HW revision detect */
718			/* REV_ID0 */
719			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08			0x1b0b0
720			/* REV_ID1 */
721			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09			0x1b0b0
722			/* REV_ID2 */
723			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10			0x1b0b0
724			/* REV_ID3 */
725			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11			0x1b0b0
726			/* REV_ID4 */
727			MX6QDL_PAD_SD4_DAT4__GPIO2_IO12			0x1b0b0
728
729			/* New in HW revision 1 */
730			/* ON1_FB */
731			MX6QDL_PAD_EIM_D20__GPIO3_IO20			0x100b0
732			/* DIP1_FB */
733			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18			0x1b0b0
734		>;
735	};
736
737	pinctrl_i2c1: i2c1grp {
738		fsl,pins = <
739			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001f8b1
740			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001f8b1
741		>;
742	};
743
744	pinctrl_i2c3: i2c3grp {
745		fsl,pins = <
746			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
747			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
748		>;
749	};
750
751	pinctrl_ipu1_csi0: ipu1csi0grp {
752		fsl,pins = <
753			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
754			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
755			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
756			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
757			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
758			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
759			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
760			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
761			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
762		>;
763	};
764
765	pinctrl_leds: ledsgrp {
766		fsl,pins = <
767			/* DEBUG0 */
768			MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16		0x1b0b0
769			/* DEBUG1 */
770			MX6QDL_PAD_DI0_PIN15__GPIO4_IO17		0x1b0b0
771			/* POWER_LED */
772			MX6QDL_PAD_EIM_CS1__GPIO2_IO24			0x1b0b0
773		>;
774	};
775
776	pinctrl_pca9539: pca9539 {
777		fsl,pins = <
778			MX6QDL_PAD_GPIO_19__GPIO4_IO05			0x1b0b0
779		>;
780	};
781
782	pinctrl_pwm1: pwm1grp {
783		fsl,pins = <
784			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT			0x1b0b0
785		>;
786	};
787
788	/* YaCO AUX Uart */
789	pinctrl_uart1: uart1grp {
790		fsl,pins = <
791			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA		0x1b0b1
792			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA		0x1b0b1
793		>;
794	};
795
796	pinctrl_uart2: uart2grp {
797		fsl,pins = <
798			MX6QDL_PAD_EIM_D26__UART2_TX_DATA		0x1b0b1
799			MX6QDL_PAD_EIM_D27__UART2_RX_DATA		0x1b0b1
800		>;
801	};
802
803	/* YaCO Touchscreen UART */
804	pinctrl_uart3: uart3grp {
805		fsl,pins = <
806			MX6QDL_PAD_EIM_D24__UART3_TX_DATA		0x1b0b1
807			MX6QDL_PAD_EIM_D25__UART3_RX_DATA		0x1b0b1
808		>;
809	};
810
811	pinctrl_uart4: uart4grp {
812		fsl,pins = <
813			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA		0x1b0b1
814			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA		0x1b0b1
815		>;
816	};
817
818	pinctrl_uart5: uart5grp {
819		fsl,pins = <
820			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA		0x1b0b1
821			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA		0x1b0b1
822		>;
823	};
824
825	pinctrl_usbotg: usbotggrp {
826		fsl,pins = <
827			MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x1b0b0
828			/* power enable, high active */
829			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
830		>;
831	};
832
833	pinctrl_usdhc1: usdhc1grp {
834		fsl,pins = <
835			MX6QDL_PAD_SD1_CMD__SD1_CMD			0x170f9
836			MX6QDL_PAD_SD1_CLK__SD1_CLK			0x100f9
837			MX6QDL_PAD_SD1_DAT0__SD1_DATA0			0x170f9
838			MX6QDL_PAD_SD1_DAT1__SD1_DATA1			0x170f9
839			MX6QDL_PAD_SD1_DAT2__SD1_DATA2			0x170f9
840			MX6QDL_PAD_SD1_DAT3__SD1_DATA3			0x170f9
841			MX6QDL_PAD_GPIO_1__GPIO1_IO01			0x1b0b0
842		>;
843	};
844
845	pinctrl_usdhc3: usdhc3grp {
846		fsl,pins = <
847			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17099
848			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10099
849			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17099
850			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17099
851			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17099
852			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17099
853			MX6QDL_PAD_SD3_DAT4__SD3_DATA4			0x17099
854			MX6QDL_PAD_SD3_DAT5__SD3_DATA5			0x17099
855			MX6QDL_PAD_SD3_DAT6__SD3_DATA6			0x17099
856			MX6QDL_PAD_SD3_DAT7__SD3_DATA7			0x17099
857			MX6QDL_PAD_SD3_RST__SD3_RESET			0x1b0b1
858		>;
859	};
860};
861