1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Sascha Hauer, Pengutronix
4 */
5
6/dts-v1/;
7#include "imx27.dtsi"
8
9/ {
10	model = "Phytec pcm038";
11	compatible = "phytec,imx27-pcm038", "fsl,imx27";
12
13	memory@a0000000 {
14		device_type = "memory";
15		reg = <0xa0000000 0x08000000>;
16	};
17
18	reg_3v3: regulator-0 {
19		compatible = "regulator-fixed";
20		regulator-name = "3V3";
21		regulator-min-microvolt = <3300000>;
22		regulator-max-microvolt = <3300000>;
23	};
24
25	reg_5v0: regulator-1 {
26		compatible = "regulator-fixed";
27		regulator-name = "5V0";
28		regulator-min-microvolt = <5000000>;
29		regulator-max-microvolt = <5000000>;
30	};
31
32	usbphy {
33		compatible = "simple-bus";
34		#address-cells = <1>;
35		#size-cells = <0>;
36
37		usbphy0: usbphy@0 {
38			compatible = "usb-nop-xceiv";
39			reg = <0>;
40			vcc-supply = <&sw3_reg>;
41			clocks = <&clks IMX27_CLK_DUMMY>;
42			clock-names = "main_clk";
43			#phy-cells = <0>;
44		};
45	};
46};
47
48&audmux {
49	status = "okay";
50
51	/* SSI0 <=> PINS_4 (MC13783 Audio) */
52	ssi0 {
53		fsl,audmux-port = <0>;
54		fsl,port-config = <0xcb205000>;
55	};
56
57	pins4 {
58		fsl,audmux-port = <2>;
59		fsl,port-config = <0x00001000>;
60	};
61};
62
63&cspi1 {
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_cspi1>;
66	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
67	status = "okay";
68
69	pmic: mc13783@0 {
70		compatible = "fsl,mc13783";
71		pinctrl-names = "default";
72		pinctrl-0 = <&pinctrl_pmic>;
73		reg = <0>;
74		spi-cs-high;
75		spi-max-frequency = <20000000>;
76		interrupt-parent = <&gpio2>;
77		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
78		fsl,mc13xxx-uses-adc;
79		fsl,mc13xxx-uses-rtc;
80
81		pmicleds: leds {
82			#address-cells = <1>;
83			#size-cells = <0>;
84			led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
85		};
86
87		regulators {
88			/* SW1A and SW1B joined operation */
89			sw1_reg: sw1a {
90				regulator-min-microvolt = <1200000>;
91				regulator-max-microvolt = <1520000>;
92				regulator-always-on;
93				regulator-boot-on;
94			};
95
96			/* SW2A and SW2B joined operation */
97			sw2_reg: sw2a {
98				regulator-min-microvolt = <1800000>;
99				regulator-max-microvolt = <1800000>;
100				regulator-always-on;
101				regulator-boot-on;
102			};
103
104			sw3_reg: sw3 {
105				regulator-min-microvolt = <5000000>;
106				regulator-max-microvolt = <5000000>;
107				regulator-always-on;
108				regulator-boot-on;
109			};
110
111			vaudio_reg: vaudio {
112				regulator-always-on;
113				regulator-boot-on;
114			};
115
116			violo_reg: violo {
117				regulator-min-microvolt = <1800000>;
118				regulator-max-microvolt = <1800000>;
119				regulator-always-on;
120				regulator-boot-on;
121			};
122
123			viohi_reg: viohi {
124				regulator-always-on;
125				regulator-boot-on;
126			};
127
128			vgen_reg: vgen {
129				regulator-min-microvolt = <1500000>;
130				regulator-max-microvolt = <1500000>;
131				regulator-always-on;
132				regulator-boot-on;
133			};
134
135			vcam_reg: vcam {
136				regulator-min-microvolt = <2800000>;
137				regulator-max-microvolt = <2800000>;
138			};
139
140			vrf1_reg: vrf1 {
141				regulator-min-microvolt = <2775000>;
142				regulator-max-microvolt = <2775000>;
143				regulator-always-on;
144				regulator-boot-on;
145			};
146
147			vrf2_reg: vrf2 {
148				regulator-min-microvolt = <2775000>;
149				regulator-max-microvolt = <2775000>;
150				regulator-always-on;
151				regulator-boot-on;
152			};
153
154			vmmc1_reg: vmmc1 {
155				regulator-min-microvolt = <1600000>;
156				regulator-max-microvolt = <3000000>;
157			};
158
159			gpo1_reg: gpo1 { };
160
161			pwgt1spi_reg: pwgt1spi {
162				regulator-always-on;
163			};
164		};
165	};
166};
167
168&fec {
169	phy-mode = "mii";
170	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
171	phy-supply = <&reg_3v3>;
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_fec1>;
174	status = "okay";
175};
176
177&i2c2 {
178	clock-frequency = <400000>;
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_i2c2>;
181	status = "okay";
182
183	at24@52 {
184		compatible = "atmel,24c32";
185		pagesize = <32>;
186		reg = <0x52>;
187	};
188
189	pcf8563@51 {
190		compatible = "nxp,pcf8563";
191		reg = <0x51>;
192	};
193
194	lm75@4a {
195		compatible = "national,lm75";
196		reg = <0x4a>;
197	};
198};
199
200&iomuxc {
201	imx27_phycore_som {
202		pinctrl_cspi1: cspi1grp {
203			fsl,pins = <
204				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
205				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
206				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
207				MX27_PAD_CSPI1_SS0__GPIO4_28	0x0 /* SPI1 CS0 */
208			>;
209		};
210
211		pinctrl_fec1: fec1grp {
212			fsl,pins = <
213				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
214				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
215				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
216				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
217				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
218				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
219				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
220				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
221				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
222				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
223				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
224				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
225				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
226				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
227				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
228				MX27_PAD_ATA_DATA13__FEC_COL 0x0
229				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
230				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
231				MX27_PAD_SSI3_TXDAT__GPIO3_30	0x0 /* FEC RST */
232			>;
233		};
234
235		pinctrl_i2c2: i2c2grp {
236			fsl,pins = <
237				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
238				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
239			>;
240		};
241
242		pinctrl_nfc: nfcgrp {
243			fsl,pins = <
244				MX27_PAD_NFRB__NFRB 0x0
245				MX27_PAD_NFCLE__NFCLE 0x0
246				MX27_PAD_NFWP_B__NFWP_B 0x0
247				MX27_PAD_NFCE_B__NFCE_B 0x0
248				MX27_PAD_NFALE__NFALE 0x0
249				MX27_PAD_NFRE_B__NFRE_B 0x0
250				MX27_PAD_NFWE_B__NFWE_B 0x0
251			>;
252		};
253
254		pinctrl_pmic: pmicgrp {
255			fsl,pins = <
256				MX27_PAD_USB_PWR__GPIO2_23	0x0 /* PMIC IRQ */
257			>;
258		};
259
260		pinctrl_ssi1: ssi1grp {
261			fsl,pins = <
262				MX27_PAD_SSI1_FS__SSI1_FS 0x0
263				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
264				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
265				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
266			>;
267		};
268
269		pinctrl_usbotg: usbotggrp {
270			fsl,pins = <
271				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
272				MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
273				MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
274				MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
275				MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
276				MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
277				MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
278				MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
279				MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
280				MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
281				MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
282				MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
283			>;
284		};
285	};
286};
287
288&nfc {
289	pinctrl-names = "default";
290	pinctrl-0 = <&pinctrl_nfc>;
291	nand-bus-width = <8>;
292	nand-ecc-mode = "hw";
293	nand-on-flash-bbt;
294	status = "okay";
295};
296
297&ssi1 {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_ssi1>;
300	status = "okay";
301};
302
303&usbotg {
304	pinctrl-names = "default";
305	pinctrl-0 = <&pinctrl_usbotg>;
306	dr_mode = "otg";
307	phy_type = "ulpi";
308	fsl,usbphy = <&usbphy0>;
309	vbus-supply = <&sw3_reg>;
310	disable-over-current;
311	status = "okay";
312};
313
314&weim {
315	status = "okay";
316
317	nor: nor@0,0 {
318		compatible = "cfi-flash";
319		reg = <0 0x00000000 0x02000000>;
320		bank-width = <2>;
321		linux,mtd-name = "physmap-flash.0";
322		fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
323		#address-cells = <1>;
324		#size-cells = <1>;
325	};
326
327	sram: sram@1,0 {
328		compatible = "mtd-ram";
329		reg = <1 0x00000000 0x00800000>;
330		bank-width = <2>;
331		linux,mtd-name = "mtd-ram.0";
332		fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
333		#address-cells = <1>;
334		#size-cells = <1>;
335	};
336};
337