1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra30-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra30-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8#include <dt-bindings/thermal/thermal.h> 9 10#include "tegra30-peripherals-opp.dtsi" 11 12/ { 13 compatible = "nvidia,tegra30"; 14 interrupt-parent = <&lic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x80000000 0x0>; 21 }; 22 23 pcie@3000 { 24 compatible = "nvidia,tegra30-pcie"; 25 device_type = "pci"; 26 reg = <0x00003000 0x00000800>, /* PADS registers */ 27 <0x00003800 0x00000200>, /* AFI registers */ 28 <0x10000000 0x10000000>; /* configuration space */ 29 reg-names = "pads", "afi", "cs"; 30 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 31 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 32 interrupt-names = "intr", "msi"; 33 34 #interrupt-cells = <1>; 35 interrupt-map-mask = <0 0 0 0>; 36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 37 38 bus-range = <0x00 0xff>; 39 #address-cells = <3>; 40 #size-cells = <2>; 41 42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ 43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ 44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ 45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ 46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ 47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 48 49 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 50 <&tegra_car TEGRA30_CLK_AFI>, 51 <&tegra_car TEGRA30_CLK_PLL_E>, 52 <&tegra_car TEGRA30_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 power-domains = <&pd_core>; 59 operating-points-v2 = <&pcie_dvfs_opp_table>; 60 status = "disabled"; 61 62 pci@1,0 { 63 device_type = "pci"; 64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 65 reg = <0x000800 0 0 0 0>; 66 bus-range = <0x00 0xff>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <2>; 74 }; 75 76 pci@2,0 { 77 device_type = "pci"; 78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 79 reg = <0x001000 0 0 0 0>; 80 bus-range = <0x00 0xff>; 81 status = "disabled"; 82 83 #address-cells = <3>; 84 #size-cells = <2>; 85 ranges; 86 87 nvidia,num-lanes = <2>; 88 }; 89 90 pci@3,0 { 91 device_type = "pci"; 92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 93 reg = <0x001800 0 0 0 0>; 94 bus-range = <0x00 0xff>; 95 status = "disabled"; 96 97 #address-cells = <3>; 98 #size-cells = <2>; 99 ranges; 100 101 nvidia,num-lanes = <2>; 102 }; 103 }; 104 105 sram@40000000 { 106 compatible = "mmio-sram"; 107 reg = <0x40000000 0x40000>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0x40000000 0x40000>; 111 112 vde_pool: sram@400 { 113 reg = <0x400 0x3fc00>; 114 pool; 115 }; 116 }; 117 118 host1x@50000000 { 119 compatible = "nvidia,tegra30-host1x"; 120 reg = <0x50000000 0x00024000>; 121 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 122 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 123 interrupt-names = "syncpt", "host1x"; 124 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 125 clock-names = "host1x"; 126 resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; 127 reset-names = "host1x", "mc"; 128 iommus = <&mc TEGRA_SWGROUP_HC>; 129 power-domains = <&pd_heg>; 130 operating-points-v2 = <&host1x_dvfs_opp_table>; 131 132 #address-cells = <1>; 133 #size-cells = <1>; 134 135 ranges = <0x54000000 0x54000000 0x04000000>; 136 137 mpe@54040000 { 138 compatible = "nvidia,tegra30-mpe"; 139 reg = <0x54040000 0x00040000>; 140 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&tegra_car TEGRA30_CLK_MPE>; 142 resets = <&tegra_car 60>; 143 reset-names = "mpe"; 144 power-domains = <&pd_mpe>; 145 operating-points-v2 = <&mpe_dvfs_opp_table>; 146 147 iommus = <&mc TEGRA_SWGROUP_MPE>; 148 149 status = "disabled"; 150 }; 151 152 vi@54080000 { 153 compatible = "nvidia,tegra30-vi"; 154 reg = <0x54080000 0x00040000>; 155 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&tegra_car TEGRA30_CLK_VI>; 157 resets = <&tegra_car 20>; 158 reset-names = "vi"; 159 power-domains = <&pd_venc>; 160 operating-points-v2 = <&vi_dvfs_opp_table>; 161 162 iommus = <&mc TEGRA_SWGROUP_VI>; 163 164 status = "disabled"; 165 }; 166 167 epp@540c0000 { 168 compatible = "nvidia,tegra30-epp"; 169 reg = <0x540c0000 0x00040000>; 170 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&tegra_car TEGRA30_CLK_EPP>; 172 resets = <&tegra_car 19>; 173 reset-names = "epp"; 174 power-domains = <&pd_heg>; 175 operating-points-v2 = <&epp_dvfs_opp_table>; 176 177 iommus = <&mc TEGRA_SWGROUP_EPP>; 178 179 status = "disabled"; 180 }; 181 182 isp@54100000 { 183 compatible = "nvidia,tegra30-isp"; 184 reg = <0x54100000 0x00040000>; 185 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&tegra_car TEGRA30_CLK_ISP>; 187 resets = <&tegra_car 23>; 188 reset-names = "isp"; 189 power-domains = <&pd_venc>; 190 191 iommus = <&mc TEGRA_SWGROUP_ISP>; 192 193 status = "disabled"; 194 }; 195 196 gr2d@54140000 { 197 compatible = "nvidia,tegra30-gr2d"; 198 reg = <0x54140000 0x00040000>; 199 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 201 resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; 202 reset-names = "2d", "mc"; 203 power-domains = <&pd_heg>; 204 operating-points-v2 = <&gr2d_dvfs_opp_table>; 205 206 iommus = <&mc TEGRA_SWGROUP_G2>; 207 }; 208 209 gr3d@54180000 { 210 compatible = "nvidia,tegra30-gr3d"; 211 reg = <0x54180000 0x00040000>; 212 clocks = <&tegra_car TEGRA30_CLK_GR3D>, 213 <&tegra_car TEGRA30_CLK_GR3D2>; 214 clock-names = "3d", "3d2"; 215 resets = <&tegra_car 24>, 216 <&tegra_car 98>, 217 <&mc TEGRA30_MC_RESET_3D>, 218 <&mc TEGRA30_MC_RESET_3D2>; 219 reset-names = "3d", "3d2", "mc", "mc2"; 220 power-domains = <&pd_3d0>, <&pd_3d1>; 221 power-domain-names = "3d0", "3d1"; 222 operating-points-v2 = <&gr3d_dvfs_opp_table>; 223 224 iommus = <&mc TEGRA_SWGROUP_NV>, 225 <&mc TEGRA_SWGROUP_NV2>; 226 }; 227 228 dc@54200000 { 229 compatible = "nvidia,tegra30-dc"; 230 reg = <0x54200000 0x00040000>; 231 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 233 <&tegra_car TEGRA30_CLK_PLL_P>; 234 clock-names = "dc", "parent"; 235 resets = <&tegra_car 27>; 236 reset-names = "dc"; 237 power-domains = <&pd_core>; 238 operating-points-v2 = <&disp1_dvfs_opp_table>; 239 240 iommus = <&mc TEGRA_SWGROUP_DC>; 241 242 nvidia,head = <0>; 243 244 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, 245 <&mc TEGRA30_MC_DISPLAY0B &emc>, 246 <&mc TEGRA30_MC_DISPLAY1B &emc>, 247 <&mc TEGRA30_MC_DISPLAY0C &emc>, 248 <&mc TEGRA30_MC_DISPLAYHC &emc>; 249 interconnect-names = "wina", 250 "winb", 251 "winb-vfilter", 252 "winc", 253 "cursor"; 254 255 rgb { 256 status = "disabled"; 257 }; 258 }; 259 260 dc@54240000 { 261 compatible = "nvidia,tegra30-dc"; 262 reg = <0x54240000 0x00040000>; 263 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 265 <&tegra_car TEGRA30_CLK_PLL_P>; 266 clock-names = "dc", "parent"; 267 resets = <&tegra_car 26>; 268 reset-names = "dc"; 269 power-domains = <&pd_core>; 270 operating-points-v2 = <&disp2_dvfs_opp_table>; 271 272 iommus = <&mc TEGRA_SWGROUP_DCB>; 273 274 nvidia,head = <1>; 275 276 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, 277 <&mc TEGRA30_MC_DISPLAY0BB &emc>, 278 <&mc TEGRA30_MC_DISPLAY1BB &emc>, 279 <&mc TEGRA30_MC_DISPLAY0CB &emc>, 280 <&mc TEGRA30_MC_DISPLAYHCB &emc>; 281 interconnect-names = "wina", 282 "winb", 283 "winb-vfilter", 284 "winc", 285 "cursor"; 286 287 rgb { 288 status = "disabled"; 289 }; 290 }; 291 292 hdmi@54280000 { 293 compatible = "nvidia,tegra30-hdmi"; 294 reg = <0x54280000 0x00040000>; 295 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 297 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 298 clock-names = "hdmi", "parent"; 299 resets = <&tegra_car 51>; 300 reset-names = "hdmi"; 301 power-domains = <&pd_core>; 302 operating-points-v2 = <&hdmi_dvfs_opp_table>; 303 status = "disabled"; 304 }; 305 306 tvo@542c0000 { 307 compatible = "nvidia,tegra30-tvo"; 308 reg = <0x542c0000 0x00040000>; 309 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&tegra_car TEGRA30_CLK_TVO>; 311 power-domains = <&pd_core>; 312 operating-points-v2 = <&tvo_dvfs_opp_table>; 313 status = "disabled"; 314 }; 315 316 dsi@54300000 { 317 compatible = "nvidia,tegra30-dsi"; 318 reg = <0x54300000 0x00040000>; 319 clocks = <&tegra_car TEGRA30_CLK_DSIA>, 320 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 321 clock-names = "dsi", "parent"; 322 resets = <&tegra_car 48>; 323 reset-names = "dsi"; 324 power-domains = <&pd_core>; 325 operating-points-v2 = <&dsia_dvfs_opp_table>; 326 status = "disabled"; 327 }; 328 329 dsi@54400000 { 330 compatible = "nvidia,tegra30-dsi"; 331 reg = <0x54400000 0x00040000>; 332 clocks = <&tegra_car TEGRA30_CLK_DSIB>, 333 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 334 clock-names = "dsi", "parent"; 335 resets = <&tegra_car 84>; 336 reset-names = "dsi"; 337 power-domains = <&pd_core>; 338 operating-points-v2 = <&dsib_dvfs_opp_table>; 339 status = "disabled"; 340 }; 341 }; 342 343 timer@50040600 { 344 compatible = "arm,cortex-a9-twd-timer"; 345 reg = <0x50040600 0x20>; 346 interrupt-parent = <&intc>; 347 interrupts = <GIC_PPI 13 348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 349 clocks = <&tegra_car TEGRA30_CLK_TWD>; 350 }; 351 352 intc: interrupt-controller@50041000 { 353 compatible = "arm,cortex-a9-gic"; 354 reg = <0x50041000 0x1000>, 355 <0x50040100 0x0100>; 356 interrupt-controller; 357 #interrupt-cells = <3>; 358 interrupt-parent = <&intc>; 359 }; 360 361 cache-controller@50043000 { 362 compatible = "arm,pl310-cache"; 363 reg = <0x50043000 0x1000>; 364 arm,data-latency = <6 6 2>; 365 arm,tag-latency = <5 5 2>; 366 cache-unified; 367 cache-level = <2>; 368 }; 369 370 lic: interrupt-controller@60004000 { 371 compatible = "nvidia,tegra30-ictlr"; 372 reg = <0x60004000 0x100>, 373 <0x60004100 0x50>, 374 <0x60004200 0x50>, 375 <0x60004300 0x50>, 376 <0x60004400 0x50>; 377 interrupt-controller; 378 #interrupt-cells = <3>; 379 interrupt-parent = <&intc>; 380 }; 381 382 timer@60005000 { 383 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 384 reg = <0x60005000 0x400>; 385 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 392 }; 393 394 tegra_car: clock@60006000 { 395 compatible = "nvidia,tegra30-car"; 396 reg = <0x60006000 0x1000>; 397 #clock-cells = <1>; 398 #reset-cells = <1>; 399 400 pll-c { 401 compatible = "nvidia,tegra30-pllc"; 402 clocks = <&tegra_car TEGRA30_CLK_PLL_C>; 403 power-domains = <&pd_core>; 404 operating-points-v2 = <&pll_c_dvfs_opp_table>; 405 }; 406 407 pll-e { 408 compatible = "nvidia,tegra30-plle"; 409 clocks = <&tegra_car TEGRA30_CLK_PLL_E>; 410 power-domains = <&pd_core>; 411 operating-points-v2 = <&pll_e_dvfs_opp_table>; 412 }; 413 414 pll-m { 415 compatible = "nvidia,tegra30-pllm"; 416 clocks = <&tegra_car TEGRA30_CLK_PLL_M>; 417 power-domains = <&pd_core>; 418 operating-points-v2 = <&pll_m_dvfs_opp_table>; 419 }; 420 421 sclk { 422 compatible = "nvidia,tegra30-sclk"; 423 clocks = <&tegra_car TEGRA30_CLK_SCLK>; 424 power-domains = <&pd_core>; 425 operating-points-v2 = <&sclk_dvfs_opp_table>; 426 }; 427 }; 428 429 flow-controller@60007000 { 430 compatible = "nvidia,tegra30-flowctrl"; 431 reg = <0x60007000 0x1000>; 432 }; 433 434 apbdma: dma@6000a000 { 435 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 436 reg = <0x6000a000 0x1400>; 437 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 470 resets = <&tegra_car 34>; 471 reset-names = "dma"; 472 #dma-cells = <1>; 473 }; 474 475 ahb: ahb@6000c000 { 476 compatible = "nvidia,tegra30-ahb"; 477 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 478 }; 479 480 actmon: actmon@6000c800 { 481 compatible = "nvidia,tegra30-actmon"; 482 reg = <0x6000c800 0x400>; 483 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&tegra_car TEGRA30_CLK_ACTMON>, 485 <&tegra_car TEGRA30_CLK_EMC>; 486 clock-names = "actmon", "emc"; 487 resets = <&tegra_car TEGRA30_CLK_ACTMON>; 488 reset-names = "actmon"; 489 operating-points-v2 = <&emc_bw_dfs_opp_table>; 490 interconnects = <&mc TEGRA30_MC_MPCORER &emc>; 491 interconnect-names = "cpu-read"; 492 #cooling-cells = <2>; 493 }; 494 495 gpio: gpio@6000d000 { 496 compatible = "nvidia,tegra30-gpio"; 497 reg = <0x6000d000 0x1000>; 498 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 506 #gpio-cells = <2>; 507 gpio-controller; 508 #interrupt-cells = <2>; 509 interrupt-controller; 510 gpio-ranges = <&pinmux 0 0 248>; 511 }; 512 513 vde@6001a000 { 514 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 515 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 516 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 517 <0x6001c000 0x100>, /* Macroblock Engine */ 518 <0x6001c200 0x100>, /* Post-processing Engine */ 519 <0x6001c400 0x100>, /* Motion Compensation Engine */ 520 <0x6001c600 0x100>, /* Transform Engine */ 521 <0x6001c800 0x100>, /* Pixel prediction block */ 522 <0x6001ca00 0x100>, /* Video DMA */ 523 <0x6001d800 0x400>; /* Video frame controls */ 524 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 525 "tfe", "ppb", "vdma", "frameid"; 526 iram = <&vde_pool>; /* IRAM region */ 527 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 528 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 529 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 530 interrupt-names = "sync-token", "bsev", "sxe"; 531 clocks = <&tegra_car TEGRA30_CLK_VDE>; 532 reset-names = "vde", "mc"; 533 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 534 iommus = <&mc TEGRA_SWGROUP_VDE>; 535 power-domains = <&pd_vde>; 536 operating-points-v2 = <&vde_dvfs_opp_table>; 537 }; 538 539 apbmisc@70000800 { 540 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 541 reg = <0x70000800 0x64>, /* Chip revision */ 542 <0x70000008 0x04>; /* Strapping options */ 543 }; 544 545 pinmux: pinmux@70000868 { 546 compatible = "nvidia,tegra30-pinmux"; 547 reg = <0x70000868 0x0d4>, /* Pad control registers */ 548 <0x70003000 0x3e4>; /* Mux registers */ 549 }; 550 551 /* 552 * There are two serial driver i.e. 8250 based simple serial 553 * driver and APB DMA based serial driver for higher baudrate 554 * and performace. To enable the 8250 based driver, the compatible 555 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 556 * the APB DMA based serial driver, the compatible is 557 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 558 */ 559 uarta: serial@70006000 { 560 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 561 reg = <0x70006000 0x40>; 562 reg-shift = <2>; 563 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 565 resets = <&tegra_car 6>; 566 reset-names = "serial"; 567 dmas = <&apbdma 8>, <&apbdma 8>; 568 dma-names = "rx", "tx"; 569 status = "disabled"; 570 }; 571 572 uartb: serial@70006040 { 573 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 574 reg = <0x70006040 0x40>; 575 reg-shift = <2>; 576 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 578 resets = <&tegra_car 7>; 579 reset-names = "serial"; 580 dmas = <&apbdma 9>, <&apbdma 9>; 581 dma-names = "rx", "tx"; 582 status = "disabled"; 583 }; 584 585 uartc: serial@70006200 { 586 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 587 reg = <0x70006200 0x100>; 588 reg-shift = <2>; 589 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 591 resets = <&tegra_car 55>; 592 reset-names = "serial"; 593 dmas = <&apbdma 10>, <&apbdma 10>; 594 dma-names = "rx", "tx"; 595 status = "disabled"; 596 }; 597 598 uartd: serial@70006300 { 599 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 600 reg = <0x70006300 0x100>; 601 reg-shift = <2>; 602 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 604 resets = <&tegra_car 65>; 605 reset-names = "serial"; 606 dmas = <&apbdma 19>, <&apbdma 19>; 607 dma-names = "rx", "tx"; 608 status = "disabled"; 609 }; 610 611 uarte: serial@70006400 { 612 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 613 reg = <0x70006400 0x100>; 614 reg-shift = <2>; 615 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 617 resets = <&tegra_car 66>; 618 reset-names = "serial"; 619 dmas = <&apbdma 20>, <&apbdma 20>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 gmi@70009000 { 625 compatible = "nvidia,tegra30-gmi"; 626 reg = <0x70009000 0x1000>; 627 #address-cells = <2>; 628 #size-cells = <1>; 629 ranges = <0 0 0x48000000 0x7ffffff>; 630 clocks = <&tegra_car TEGRA30_CLK_NOR>; 631 clock-names = "gmi"; 632 resets = <&tegra_car 42>; 633 reset-names = "gmi"; 634 power-domains = <&pd_core>; 635 operating-points-v2 = <&nor_dvfs_opp_table>; 636 status = "disabled"; 637 }; 638 639 pwm: pwm@7000a000 { 640 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 641 reg = <0x7000a000 0x100>; 642 #pwm-cells = <2>; 643 clocks = <&tegra_car TEGRA30_CLK_PWM>; 644 resets = <&tegra_car 17>; 645 reset-names = "pwm"; 646 power-domains = <&pd_core>; 647 operating-points-v2 = <&pwm_dvfs_opp_table>; 648 status = "disabled"; 649 }; 650 651 i2c@7000c000 { 652 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 653 reg = <0x7000c000 0x100>; 654 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 658 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 659 clock-names = "div-clk", "fast-clk"; 660 resets = <&tegra_car 12>; 661 reset-names = "i2c"; 662 dmas = <&apbdma 21>, <&apbdma 21>; 663 dma-names = "rx", "tx"; 664 status = "disabled"; 665 }; 666 667 i2c@7000c400 { 668 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 669 reg = <0x7000c400 0x100>; 670 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 674 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 675 clock-names = "div-clk", "fast-clk"; 676 resets = <&tegra_car 54>; 677 reset-names = "i2c"; 678 dmas = <&apbdma 22>, <&apbdma 22>; 679 dma-names = "rx", "tx"; 680 status = "disabled"; 681 }; 682 683 i2c@7000c500 { 684 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 685 reg = <0x7000c500 0x100>; 686 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 690 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 691 clock-names = "div-clk", "fast-clk"; 692 resets = <&tegra_car 67>; 693 reset-names = "i2c"; 694 dmas = <&apbdma 23>, <&apbdma 23>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 i2c@7000c700 { 700 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 701 reg = <0x7000c700 0x100>; 702 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 706 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 707 resets = <&tegra_car 103>; 708 reset-names = "i2c"; 709 clock-names = "div-clk", "fast-clk"; 710 dmas = <&apbdma 26>, <&apbdma 26>; 711 dma-names = "rx", "tx"; 712 status = "disabled"; 713 }; 714 715 i2c@7000d000 { 716 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 717 reg = <0x7000d000 0x100>; 718 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 722 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 723 clock-names = "div-clk", "fast-clk"; 724 resets = <&tegra_car 47>; 725 reset-names = "i2c"; 726 dmas = <&apbdma 24>, <&apbdma 24>; 727 dma-names = "rx", "tx"; 728 status = "disabled"; 729 }; 730 731 spi@7000d400 { 732 compatible = "nvidia,tegra30-slink"; 733 reg = <0x7000d400 0x200>; 734 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 738 resets = <&tegra_car 41>; 739 reset-names = "spi"; 740 dmas = <&apbdma 15>, <&apbdma 15>; 741 dma-names = "rx", "tx"; 742 power-domains = <&pd_core>; 743 operating-points-v2 = <&sbc1_dvfs_opp_table>; 744 status = "disabled"; 745 }; 746 747 spi@7000d600 { 748 compatible = "nvidia,tegra30-slink"; 749 reg = <0x7000d600 0x200>; 750 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 754 resets = <&tegra_car 44>; 755 reset-names = "spi"; 756 dmas = <&apbdma 16>, <&apbdma 16>; 757 dma-names = "rx", "tx"; 758 power-domains = <&pd_core>; 759 operating-points-v2 = <&sbc2_dvfs_opp_table>; 760 status = "disabled"; 761 }; 762 763 spi@7000d800 { 764 compatible = "nvidia,tegra30-slink"; 765 reg = <0x7000d800 0x200>; 766 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 770 resets = <&tegra_car 46>; 771 reset-names = "spi"; 772 dmas = <&apbdma 17>, <&apbdma 17>; 773 dma-names = "rx", "tx"; 774 power-domains = <&pd_core>; 775 operating-points-v2 = <&sbc3_dvfs_opp_table>; 776 status = "disabled"; 777 }; 778 779 spi@7000da00 { 780 compatible = "nvidia,tegra30-slink"; 781 reg = <0x7000da00 0x200>; 782 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 786 resets = <&tegra_car 68>; 787 reset-names = "spi"; 788 dmas = <&apbdma 18>, <&apbdma 18>; 789 dma-names = "rx", "tx"; 790 power-domains = <&pd_core>; 791 operating-points-v2 = <&sbc4_dvfs_opp_table>; 792 status = "disabled"; 793 }; 794 795 spi@7000dc00 { 796 compatible = "nvidia,tegra30-slink"; 797 reg = <0x7000dc00 0x200>; 798 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 802 resets = <&tegra_car 104>; 803 reset-names = "spi"; 804 dmas = <&apbdma 27>, <&apbdma 27>; 805 dma-names = "rx", "tx"; 806 power-domains = <&pd_core>; 807 operating-points-v2 = <&sbc5_dvfs_opp_table>; 808 status = "disabled"; 809 }; 810 811 spi@7000de00 { 812 compatible = "nvidia,tegra30-slink"; 813 reg = <0x7000de00 0x200>; 814 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 818 resets = <&tegra_car 106>; 819 reset-names = "spi"; 820 dmas = <&apbdma 28>, <&apbdma 28>; 821 dma-names = "rx", "tx"; 822 power-domains = <&pd_core>; 823 operating-points-v2 = <&sbc6_dvfs_opp_table>; 824 status = "disabled"; 825 }; 826 827 rtc@7000e000 { 828 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 829 reg = <0x7000e000 0x100>; 830 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&tegra_car TEGRA30_CLK_RTC>; 832 }; 833 834 kbc@7000e200 { 835 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 836 reg = <0x7000e200 0x100>; 837 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&tegra_car TEGRA30_CLK_KBC>; 839 resets = <&tegra_car 36>; 840 reset-names = "kbc"; 841 status = "disabled"; 842 }; 843 844 tegra_pmc: pmc@7000e400 { 845 compatible = "nvidia,tegra30-pmc"; 846 reg = <0x7000e400 0x400>; 847 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 848 clock-names = "pclk", "clk32k_in"; 849 #clock-cells = <1>; 850 851 pd_core: core-domain { 852 #power-domain-cells = <0>; 853 operating-points-v2 = <&core_opp_table>; 854 }; 855 856 powergates { 857 pd_heg: heg { 858 clocks = <&tegra_car TEGRA30_CLK_GR2D>, 859 <&tegra_car TEGRA30_CLK_EPP>, 860 <&tegra_car TEGRA30_CLK_HOST1X>; 861 resets = <&mc TEGRA30_MC_RESET_2D>, 862 <&mc TEGRA30_MC_RESET_EPP>, 863 <&mc TEGRA30_MC_RESET_HC>, 864 <&tegra_car TEGRA30_CLK_GR2D>, 865 <&tegra_car TEGRA30_CLK_EPP>, 866 <&tegra_car TEGRA30_CLK_HOST1X>; 867 power-domains = <&pd_core>; 868 #power-domain-cells = <0>; 869 }; 870 871 pd_mpe: mpe { 872 clocks = <&tegra_car TEGRA30_CLK_MPE>; 873 resets = <&mc TEGRA30_MC_RESET_MPE>, 874 <&tegra_car TEGRA30_CLK_MPE>; 875 power-domains = <&pd_core>; 876 #power-domain-cells = <0>; 877 }; 878 879 pd_3d0: td { 880 clocks = <&tegra_car TEGRA30_CLK_GR3D>; 881 resets = <&mc TEGRA30_MC_RESET_3D>, 882 <&tegra_car TEGRA30_CLK_GR3D>; 883 power-domains = <&pd_core>; 884 #power-domain-cells = <0>; 885 }; 886 887 pd_3d1: td2 { 888 clocks = <&tegra_car TEGRA30_CLK_GR3D2>; 889 resets = <&mc TEGRA30_MC_RESET_3D2>, 890 <&tegra_car TEGRA30_CLK_GR3D2>; 891 power-domains = <&pd_core>; 892 #power-domain-cells = <0>; 893 }; 894 895 pd_vde: vdec { 896 clocks = <&tegra_car TEGRA30_CLK_VDE>; 897 resets = <&mc TEGRA30_MC_RESET_VDE>, 898 <&tegra_car TEGRA30_CLK_VDE>; 899 power-domains = <&pd_core>; 900 #power-domain-cells = <0>; 901 }; 902 903 pd_venc: venc { 904 clocks = <&tegra_car TEGRA30_CLK_ISP>, 905 <&tegra_car TEGRA30_CLK_VI>, 906 <&tegra_car TEGRA30_CLK_CSI>; 907 resets = <&mc TEGRA30_MC_RESET_ISP>, 908 <&mc TEGRA30_MC_RESET_VI>, 909 <&tegra_car TEGRA30_CLK_ISP>, 910 <&tegra_car 20 /* VI */>, 911 <&tegra_car TEGRA30_CLK_CSI>; 912 power-domains = <&pd_core>; 913 #power-domain-cells = <0>; 914 }; 915 }; 916 }; 917 918 mc: memory-controller@7000f000 { 919 compatible = "nvidia,tegra30-mc"; 920 reg = <0x7000f000 0x400>; 921 clocks = <&tegra_car TEGRA30_CLK_MC>; 922 clock-names = "mc"; 923 924 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 925 926 #iommu-cells = <1>; 927 #reset-cells = <1>; 928 #interconnect-cells = <1>; 929 }; 930 931 emc: memory-controller@7000f400 { 932 compatible = "nvidia,tegra30-emc"; 933 reg = <0x7000f400 0x400>; 934 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&tegra_car TEGRA30_CLK_EMC>; 936 power-domains = <&pd_core>; 937 938 nvidia,memory-controller = <&mc>; 939 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 940 941 #interconnect-cells = <0>; 942 }; 943 944 fuse@7000f800 { 945 compatible = "nvidia,tegra30-efuse"; 946 reg = <0x7000f800 0x400>; 947 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 948 clock-names = "fuse"; 949 resets = <&tegra_car 39>; 950 reset-names = "fuse"; 951 power-domains = <&pd_core>; 952 operating-points-v2 = <&fuse_burn_dvfs_opp_table>; 953 }; 954 955 tsensor: tsensor@70014000 { 956 compatible = "nvidia,tegra30-tsensor"; 957 reg = <0x70014000 0x500>; 958 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 960 resets = <&tegra_car TEGRA30_CLK_TSENSOR>; 961 962 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 963 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; 964 assigned-clock-rates = <500000>; 965 966 #thermal-sensor-cells = <1>; 967 }; 968 969 hda@70030000 { 970 compatible = "nvidia,tegra30-hda"; 971 reg = <0x70030000 0x10000>; 972 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&tegra_car TEGRA30_CLK_HDA>, 974 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 975 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 976 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 977 resets = <&tegra_car 125>, /* hda */ 978 <&tegra_car 128>, /* hda2hdmi */ 979 <&tegra_car 111>; /* hda2codec_2x */ 980 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 981 status = "disabled"; 982 }; 983 984 ahub@70080000 { 985 compatible = "nvidia,tegra30-ahub"; 986 reg = <0x70080000 0x200>, 987 <0x70080200 0x100>; 988 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 990 <&tegra_car TEGRA30_CLK_APBIF>; 991 clock-names = "d_audio", "apbif"; 992 resets = <&tegra_car 106>, /* d_audio */ 993 <&tegra_car 107>, /* apbif */ 994 <&tegra_car 30>, /* i2s0 */ 995 <&tegra_car 11>, /* i2s1 */ 996 <&tegra_car 18>, /* i2s2 */ 997 <&tegra_car 101>, /* i2s3 */ 998 <&tegra_car 102>, /* i2s4 */ 999 <&tegra_car 108>, /* dam0 */ 1000 <&tegra_car 109>, /* dam1 */ 1001 <&tegra_car 110>, /* dam2 */ 1002 <&tegra_car 10>; /* spdif */ 1003 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1004 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1005 "spdif"; 1006 dmas = <&apbdma 1>, <&apbdma 1>, 1007 <&apbdma 2>, <&apbdma 2>, 1008 <&apbdma 3>, <&apbdma 3>, 1009 <&apbdma 4>, <&apbdma 4>; 1010 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1011 "rx3", "tx3"; 1012 ranges; 1013 #address-cells = <1>; 1014 #size-cells = <1>; 1015 1016 tegra_i2s0: i2s@70080300 { 1017 compatible = "nvidia,tegra30-i2s"; 1018 reg = <0x70080300 0x100>; 1019 nvidia,ahub-cif-ids = <4 4>; 1020 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 1021 resets = <&tegra_car 30>; 1022 reset-names = "i2s"; 1023 status = "disabled"; 1024 }; 1025 1026 tegra_i2s1: i2s@70080400 { 1027 compatible = "nvidia,tegra30-i2s"; 1028 reg = <0x70080400 0x100>; 1029 nvidia,ahub-cif-ids = <5 5>; 1030 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 1031 resets = <&tegra_car 11>; 1032 reset-names = "i2s"; 1033 status = "disabled"; 1034 }; 1035 1036 tegra_i2s2: i2s@70080500 { 1037 compatible = "nvidia,tegra30-i2s"; 1038 reg = <0x70080500 0x100>; 1039 nvidia,ahub-cif-ids = <6 6>; 1040 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 1041 resets = <&tegra_car 18>; 1042 reset-names = "i2s"; 1043 status = "disabled"; 1044 }; 1045 1046 tegra_i2s3: i2s@70080600 { 1047 compatible = "nvidia,tegra30-i2s"; 1048 reg = <0x70080600 0x100>; 1049 nvidia,ahub-cif-ids = <7 7>; 1050 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 1051 resets = <&tegra_car 101>; 1052 reset-names = "i2s"; 1053 status = "disabled"; 1054 }; 1055 1056 tegra_i2s4: i2s@70080700 { 1057 compatible = "nvidia,tegra30-i2s"; 1058 reg = <0x70080700 0x100>; 1059 nvidia,ahub-cif-ids = <8 8>; 1060 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 1061 resets = <&tegra_car 102>; 1062 reset-names = "i2s"; 1063 status = "disabled"; 1064 }; 1065 }; 1066 1067 mmc@78000000 { 1068 compatible = "nvidia,tegra30-sdhci"; 1069 reg = <0x78000000 0x200>; 1070 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 1072 clock-names = "sdhci"; 1073 resets = <&tegra_car 14>; 1074 reset-names = "sdhci"; 1075 power-domains = <&pd_core>; 1076 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 1077 status = "disabled"; 1078 }; 1079 1080 mmc@78000200 { 1081 compatible = "nvidia,tegra30-sdhci"; 1082 reg = <0x78000200 0x200>; 1083 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 1085 clock-names = "sdhci"; 1086 resets = <&tegra_car 9>; 1087 reset-names = "sdhci"; 1088 status = "disabled"; 1089 }; 1090 1091 mmc@78000400 { 1092 compatible = "nvidia,tegra30-sdhci"; 1093 reg = <0x78000400 0x200>; 1094 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 1096 clock-names = "sdhci"; 1097 resets = <&tegra_car 69>; 1098 reset-names = "sdhci"; 1099 power-domains = <&pd_core>; 1100 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1101 status = "disabled"; 1102 }; 1103 1104 mmc@78000600 { 1105 compatible = "nvidia,tegra30-sdhci"; 1106 reg = <0x78000600 0x200>; 1107 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 1109 clock-names = "sdhci"; 1110 resets = <&tegra_car 15>; 1111 reset-names = "sdhci"; 1112 status = "disabled"; 1113 }; 1114 1115 usb@7d000000 { 1116 compatible = "nvidia,tegra30-ehci"; 1117 reg = <0x7d000000 0x4000>; 1118 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1119 phy_type = "utmi"; 1120 clocks = <&tegra_car TEGRA30_CLK_USBD>; 1121 resets = <&tegra_car 22>; 1122 reset-names = "usb"; 1123 nvidia,needs-double-reset; 1124 nvidia,phy = <&phy1>; 1125 power-domains = <&pd_core>; 1126 operating-points-v2 = <&usbd_dvfs_opp_table>; 1127 status = "disabled"; 1128 }; 1129 1130 phy1: usb-phy@7d000000 { 1131 compatible = "nvidia,tegra30-usb-phy"; 1132 reg = <0x7d000000 0x4000>, 1133 <0x7d000000 0x4000>; 1134 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1135 phy_type = "utmi"; 1136 clocks = <&tegra_car TEGRA30_CLK_USBD>, 1137 <&tegra_car TEGRA30_CLK_PLL_U>, 1138 <&tegra_car TEGRA30_CLK_USBD>; 1139 clock-names = "reg", "pll_u", "utmi-pads"; 1140 resets = <&tegra_car 22>, <&tegra_car 22>; 1141 reset-names = "usb", "utmi-pads"; 1142 #phy-cells = <0>; 1143 nvidia,hssync-start-delay = <9>; 1144 nvidia,idle-wait-delay = <17>; 1145 nvidia,elastic-limit = <16>; 1146 nvidia,term-range-adj = <6>; 1147 nvidia,xcvr-setup = <51>; 1148 nvidia,xcvr-setup-use-fuses; 1149 nvidia,xcvr-lsfslew = <1>; 1150 nvidia,xcvr-lsrslew = <1>; 1151 nvidia,xcvr-hsslew = <32>; 1152 nvidia,hssquelch-level = <2>; 1153 nvidia,hsdiscon-level = <5>; 1154 nvidia,has-utmi-pad-registers; 1155 nvidia,pmc = <&tegra_pmc 0>; 1156 status = "disabled"; 1157 }; 1158 1159 usb@7d004000 { 1160 compatible = "nvidia,tegra30-ehci"; 1161 reg = <0x7d004000 0x4000>; 1162 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1163 phy_type = "utmi"; 1164 clocks = <&tegra_car TEGRA30_CLK_USB2>; 1165 resets = <&tegra_car 58>; 1166 reset-names = "usb"; 1167 nvidia,phy = <&phy2>; 1168 power-domains = <&pd_core>; 1169 operating-points-v2 = <&usb2_dvfs_opp_table>; 1170 status = "disabled"; 1171 }; 1172 1173 phy2: usb-phy@7d004000 { 1174 compatible = "nvidia,tegra30-usb-phy"; 1175 reg = <0x7d004000 0x4000>, 1176 <0x7d000000 0x4000>; 1177 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1178 phy_type = "utmi"; 1179 clocks = <&tegra_car TEGRA30_CLK_USB2>, 1180 <&tegra_car TEGRA30_CLK_PLL_U>, 1181 <&tegra_car TEGRA30_CLK_USBD>; 1182 clock-names = "reg", "pll_u", "utmi-pads"; 1183 resets = <&tegra_car 58>, <&tegra_car 22>; 1184 reset-names = "usb", "utmi-pads"; 1185 #phy-cells = <0>; 1186 nvidia,hssync-start-delay = <9>; 1187 nvidia,idle-wait-delay = <17>; 1188 nvidia,elastic-limit = <16>; 1189 nvidia,term-range-adj = <6>; 1190 nvidia,xcvr-setup = <51>; 1191 nvidia,xcvr-setup-use-fuses; 1192 nvidia,xcvr-lsfslew = <2>; 1193 nvidia,xcvr-lsrslew = <2>; 1194 nvidia,xcvr-hsslew = <32>; 1195 nvidia,hssquelch-level = <2>; 1196 nvidia,hsdiscon-level = <5>; 1197 nvidia,pmc = <&tegra_pmc 2>; 1198 status = "disabled"; 1199 }; 1200 1201 usb@7d008000 { 1202 compatible = "nvidia,tegra30-ehci"; 1203 reg = <0x7d008000 0x4000>; 1204 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1205 phy_type = "utmi"; 1206 clocks = <&tegra_car TEGRA30_CLK_USB3>; 1207 resets = <&tegra_car 59>; 1208 reset-names = "usb"; 1209 nvidia,phy = <&phy3>; 1210 power-domains = <&pd_core>; 1211 operating-points-v2 = <&usb3_dvfs_opp_table>; 1212 status = "disabled"; 1213 }; 1214 1215 phy3: usb-phy@7d008000 { 1216 compatible = "nvidia,tegra30-usb-phy"; 1217 reg = <0x7d008000 0x4000>, 1218 <0x7d000000 0x4000>; 1219 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1220 phy_type = "utmi"; 1221 clocks = <&tegra_car TEGRA30_CLK_USB3>, 1222 <&tegra_car TEGRA30_CLK_PLL_U>, 1223 <&tegra_car TEGRA30_CLK_USBD>; 1224 clock-names = "reg", "pll_u", "utmi-pads"; 1225 resets = <&tegra_car 59>, <&tegra_car 22>; 1226 reset-names = "usb", "utmi-pads"; 1227 #phy-cells = <0>; 1228 nvidia,hssync-start-delay = <0>; 1229 nvidia,idle-wait-delay = <17>; 1230 nvidia,elastic-limit = <16>; 1231 nvidia,term-range-adj = <6>; 1232 nvidia,xcvr-setup = <51>; 1233 nvidia,xcvr-setup-use-fuses; 1234 nvidia,xcvr-lsfslew = <2>; 1235 nvidia,xcvr-lsrslew = <2>; 1236 nvidia,xcvr-hsslew = <32>; 1237 nvidia,hssquelch-level = <2>; 1238 nvidia,hsdiscon-level = <5>; 1239 nvidia,pmc = <&tegra_pmc 1>; 1240 status = "disabled"; 1241 }; 1242 1243 cpus { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 1247 cpu0: cpu@0 { 1248 device_type = "cpu"; 1249 compatible = "arm,cortex-a9"; 1250 reg = <0>; 1251 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1252 #cooling-cells = <2>; 1253 }; 1254 1255 cpu1: cpu@1 { 1256 device_type = "cpu"; 1257 compatible = "arm,cortex-a9"; 1258 reg = <1>; 1259 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1260 #cooling-cells = <2>; 1261 }; 1262 1263 cpu2: cpu@2 { 1264 device_type = "cpu"; 1265 compatible = "arm,cortex-a9"; 1266 reg = <2>; 1267 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1268 #cooling-cells = <2>; 1269 }; 1270 1271 cpu3: cpu@3 { 1272 device_type = "cpu"; 1273 compatible = "arm,cortex-a9"; 1274 reg = <3>; 1275 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1276 #cooling-cells = <2>; 1277 }; 1278 }; 1279 1280 pmu { 1281 compatible = "arm,cortex-a9-pmu"; 1282 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1286 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1287 }; 1288 1289 thermal-zones { 1290 tsensor0-thermal { 1291 polling-delay-passive = <1000>; /* milliseconds */ 1292 polling-delay = <5000>; /* milliseconds */ 1293 1294 thermal-sensors = <&tsensor 0>; 1295 1296 trips { 1297 level1_trip: dvfs-alert { 1298 /* throttle at 80C until temperature drops to 79.8C */ 1299 temperature = <80000>; 1300 hysteresis = <200>; 1301 type = "passive"; 1302 }; 1303 1304 level2_trip: cpu-div2-throttle { 1305 /* hardware CPU x2 freq throttle at 85C */ 1306 temperature = <85000>; 1307 hysteresis = <200>; 1308 type = "hot"; 1309 }; 1310 1311 level3_trip: soc-critical { 1312 /* hardware shut down at 90C */ 1313 temperature = <90000>; 1314 hysteresis = <2000>; 1315 type = "critical"; 1316 }; 1317 }; 1318 1319 cooling-maps { 1320 map0 { 1321 trip = <&level1_trip>; 1322 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1323 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1324 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1325 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1326 <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1327 }; 1328 }; 1329 }; 1330 1331 tsensor1-thermal { 1332 status = "disabled"; 1333 1334 polling-delay-passive = <1000>; /* milliseconds */ 1335 polling-delay = <0>; /* milliseconds */ 1336 1337 thermal-sensors = <&tsensor 1>; 1338 1339 trips { 1340 dvfs-alert { 1341 temperature = <80000>; 1342 hysteresis = <200>; 1343 type = "passive"; 1344 }; 1345 }; 1346 }; 1347 }; 1348}; 1349