1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/input/gpio-keys.h>
4#include <dt-bindings/input/input.h>
5#include <dt-bindings/thermal/thermal.h>
6
7#include "tegra30.dtsi"
8#include "tegra30-cpu-opp.dtsi"
9#include "tegra30-cpu-opp-microvolt.dtsi"
10
11/ {
12	chassis-type = "convertible";
13
14	aliases {
15		mmc0 = "/mmc@78000600"; /* eMMC */
16		mmc1 = "/mmc@78000000"; /* uSD slot */
17		mmc2 = "/mmc@78000400"; /* WiFi */
18
19		rtc0 = &pmic;
20		rtc1 = "/rtc@7000e000";
21
22		display0 = &lcd;
23		display1 = &hdmi;
24
25		serial1 = &uartc; /* Bluetooth */
26		serial2 = &uartb; /* GPS */
27	};
28
29	/*
30	 * The decompressor and also some bootloaders rely on a
31	 * pre-existing /chosen node to be available to insert the
32	 * command line and merge other ATAGS info.
33	 */
34	chosen {};
35
36	firmware {
37		trusted-foundations {
38			compatible = "tlm,trusted-foundations";
39			tlm,version-major = <2>;
40			tlm,version-minor = <8>;
41		};
42	};
43
44	memory@80000000 {
45		reg = <0x80000000 0x40000000>;
46	};
47
48	reserved-memory {
49		#address-cells = <1>;
50		#size-cells = <1>;
51		ranges;
52
53		linux,cma@80000000 {
54			compatible = "shared-dma-pool";
55			alloc-ranges = <0x80000000 0x30000000>;
56			size = <0x10000000>;		/* 256MiB */
57			linux,cma-default;
58			reusable;
59		};
60
61		ramoops@beb00000 {
62			compatible = "ramoops";
63			reg = <0xbeb00000 0x10000>;	/* 64kB */
64			console-size = <0x8000>;	/* 32kB */
65			record-size = <0x400>;		/*  1kB */
66			ecc-size = <16>;
67		};
68
69		trustzone@bfe00000 {
70			reg = <0xbfe00000 0x200000>;	/* 2MB */
71			no-map;
72		};
73	};
74
75	host1x@50000000 {
76		hdmi: hdmi@54280000 {
77			status = "okay";
78
79			hdmi-supply = <&hdmi_5v0_sys>;
80			pll-supply = <&vdd_1v8_vio>;
81			vdd-supply = <&vdd_3v3_sys>;
82
83			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
84			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85		};
86	};
87
88	gpio@6000d000 {
89		init-lpm-in-hog {
90			gpio-hog;
91			gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
92				<TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
93			input;
94		};
95
96		init-lpm-out-hog {
97			gpio-hog;
98			gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
99				<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
100			output-low;
101		};
102
103		usb-charge-limit-hog {
104			gpio-hog;
105			gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
106			output-high;
107		};
108	};
109
110	vde@6001a000 {
111		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
112		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
113		assigned-clock-rates = <408000000>;
114	};
115
116	pinmux@70000868 {
117		pinctrl-names = "default";
118		pinctrl-0 = <&state_default>;
119
120		state_default: pinmux {
121			/* SDMMC1 pinmux */
122			sdmmc1_clk {
123				nvidia,pins = "sdmmc1_clk_pz0";
124				nvidia,function = "sdmmc1";
125				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126				nvidia,tristate = <TEGRA_PIN_DISABLE>;
127				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128			};
129
130			sdmmc1_cmd {
131				nvidia,pins = "sdmmc1_dat3_py4",
132						"sdmmc1_dat2_py5",
133						"sdmmc1_dat1_py6",
134						"sdmmc1_dat0_py7",
135						"sdmmc1_cmd_pz1";
136				nvidia,function = "sdmmc1";
137				nvidia,pull = <TEGRA_PIN_PULL_UP>;
138				nvidia,tristate = <TEGRA_PIN_DISABLE>;
139				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140			};
141
142			sdmmc1_cd {
143				nvidia,pins = "gmi_iordy_pi5";
144				nvidia,function = "rsvd1";
145				nvidia,pull = <TEGRA_PIN_PULL_UP>;
146				nvidia,tristate = <TEGRA_PIN_DISABLE>;
147				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148			};
149
150			sdmmc1_wp {
151				nvidia,pins = "vi_d11_pt3";
152				nvidia,function = "rsvd2";
153				nvidia,pull = <TEGRA_PIN_PULL_UP>;
154				nvidia,tristate = <TEGRA_PIN_DISABLE>;
155				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156			};
157
158			/* SDMMC2 pinmux */
159			vi_d1_pd5 {
160				nvidia,pins = "vi_d1_pd5",
161						"vi_d2_pl0",
162						"vi_d3_pl1",
163						"vi_d5_pl3",
164						"vi_d7_pl5";
165				nvidia,function = "sdmmc2";
166				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169			};
170
171			vi_d8_pl6 {
172				nvidia,pins = "vi_d8_pl6",
173						"vi_d9_pl7";
174				nvidia,function = "sdmmc2";
175				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176				nvidia,tristate = <TEGRA_PIN_DISABLE>;
177				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178				nvidia,lock = <0>;
179				nvidia,io-reset = <0>;
180			};
181
182			/* SDMMC3 pinmux */
183			sdmmc3_clk {
184				nvidia,pins = "sdmmc3_clk_pa6";
185				nvidia,function = "sdmmc3";
186				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187				nvidia,tristate = <TEGRA_PIN_DISABLE>;
188				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189			};
190
191			sdmmc3_cmd {
192				nvidia,pins = "sdmmc3_cmd_pa7",
193						"sdmmc3_dat0_pb7",
194						"sdmmc3_dat1_pb6",
195						"sdmmc3_dat2_pb5",
196						"sdmmc3_dat3_pb4",
197						"sdmmc3_dat4_pd1",
198						"sdmmc3_dat5_pd0",
199						"sdmmc3_dat6_pd3",
200						"sdmmc3_dat7_pd4";
201				nvidia,function = "sdmmc3";
202				nvidia,pull = <TEGRA_PIN_PULL_UP>;
203				nvidia,tristate = <TEGRA_PIN_DISABLE>;
204				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
205			};
206
207			/* SDMMC4 pinmux */
208			sdmmc4_clk {
209				nvidia,pins = "sdmmc4_clk_pcc4";
210				nvidia,function = "sdmmc4";
211				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212				nvidia,tristate = <TEGRA_PIN_DISABLE>;
213				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214			};
215
216			sdmmc4_cmd {
217				nvidia,pins = "sdmmc4_cmd_pt7",
218						"sdmmc4_dat0_paa0",
219						"sdmmc4_dat1_paa1",
220						"sdmmc4_dat2_paa2",
221						"sdmmc4_dat3_paa3",
222						"sdmmc4_dat4_paa4",
223						"sdmmc4_dat5_paa5",
224						"sdmmc4_dat6_paa6",
225						"sdmmc4_dat7_paa7";
226				nvidia,function = "sdmmc4";
227				nvidia,pull = <TEGRA_PIN_PULL_UP>;
228				nvidia,tristate = <TEGRA_PIN_DISABLE>;
229				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230			};
231
232			sdmmc4_rst_n {
233				nvidia,pins = "sdmmc4_rst_n_pcc3";
234				nvidia,function = "rsvd2";
235				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
236				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238			};
239
240			cam_mclk {
241				nvidia,pins = "cam_mclk_pcc0";
242				nvidia,function = "vi_alt3";
243				nvidia,pull = <TEGRA_PIN_PULL_UP>;
244				nvidia,tristate = <TEGRA_PIN_DISABLE>;
245				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246			};
247
248			drive_sdmmc4 {
249				nvidia,pins = "drive_gma",
250						"drive_gmb",
251						"drive_gmc",
252						"drive_gmd";
253				nvidia,pull-down-strength = <9>;
254				nvidia,pull-up-strength = <9>;
255				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
256				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
257			};
258
259			/* I2C pinmux */
260			gen1_i2c {
261				nvidia,pins = "gen1_i2c_scl_pc4",
262						"gen1_i2c_sda_pc5";
263				nvidia,function = "i2c1";
264				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265				nvidia,tristate = <TEGRA_PIN_DISABLE>;
266				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
268				nvidia,lock = <0>;
269			};
270
271			gen2_i2c {
272				nvidia,pins = "gen2_i2c_scl_pt5",
273						"gen2_i2c_sda_pt6";
274				nvidia,function = "i2c2";
275				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276				nvidia,tristate = <TEGRA_PIN_DISABLE>;
277				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
279				nvidia,lock = <0>;
280			};
281
282			cam_i2c {
283				nvidia,pins = "cam_i2c_scl_pbb1",
284						"cam_i2c_sda_pbb2";
285				nvidia,function = "i2c3";
286				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
290				nvidia,lock = <0>;
291			};
292
293			ddc_i2c {
294				nvidia,pins = "ddc_scl_pv4",
295						"ddc_sda_pv5";
296				nvidia,function = "i2c4";
297				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298				nvidia,tristate = <TEGRA_PIN_DISABLE>;
299				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
300				nvidia,lock = <0>;
301			};
302
303			pwr_i2c {
304				nvidia,pins = "pwr_i2c_scl_pz6",
305						"pwr_i2c_sda_pz7";
306				nvidia,function = "i2cpwr";
307				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308				nvidia,tristate = <TEGRA_PIN_DISABLE>;
309				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
311				nvidia,lock = <0>;
312			};
313
314			hotplug_i2c {
315				nvidia,pins = "pu4";
316				nvidia,function = "rsvd4";
317				nvidia,pull = <TEGRA_PIN_PULL_UP>;
318				nvidia,tristate = <TEGRA_PIN_DISABLE>;
319				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
320			};
321
322			/* HDMI pinmux */
323			hdmi_cec {
324				nvidia,pins = "hdmi_cec_pee3";
325				nvidia,function = "cec";
326				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327				nvidia,tristate = <TEGRA_PIN_DISABLE>;
328				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330				nvidia,lock = <0>;
331			};
332
333			hdmi_hpd {
334				nvidia,pins = "hdmi_int_pn7";
335				nvidia,function = "hdmi";
336				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
337				nvidia,tristate = <TEGRA_PIN_ENABLE>;
338				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
339			};
340
341			/* UART-A */
342			ulpi_data0_po1 {
343				nvidia,pins = "ulpi_data0_po1";
344				nvidia,function = "uarta";
345				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346				nvidia,tristate = <TEGRA_PIN_DISABLE>;
347				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348			};
349
350			ulpi_data1_po2 {
351				nvidia,pins = "ulpi_data1_po2";
352				nvidia,function = "uarta";
353				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356			};
357
358			ulpi_data5_po6 {
359				nvidia,pins = "ulpi_data5_po6";
360				nvidia,function = "uarta";
361				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362				nvidia,tristate = <TEGRA_PIN_ENABLE>;
363				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364			};
365
366			ulpi_data7_po0 {
367				nvidia,pins = "ulpi_data7_po0",
368						"ulpi_data2_po3",
369						"ulpi_data3_po4",
370						"ulpi_data4_po5",
371						"ulpi_data6_po7";
372				nvidia,function = "uarta";
373				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374				nvidia,tristate = <TEGRA_PIN_DISABLE>;
375				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376			};
377
378			/* UART-B */
379			uartb_txd_rts {
380				nvidia,pins = "uart2_txd_pc2",
381						"uart2_rts_n_pj6";
382				nvidia,function = "uartb";
383				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384				nvidia,tristate = <TEGRA_PIN_DISABLE>;
385				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386			};
387
388			uartb_rxd_cts {
389				nvidia,pins = "uart2_rxd_pc3",
390						"uart2_cts_n_pj5";
391				nvidia,function = "uartb";
392				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395			};
396
397			/* UART-C */
398			uartc_rxd_cts {
399				nvidia,pins = "uart3_cts_n_pa1",
400						"uart3_rxd_pw7";
401				nvidia,function = "uartc";
402				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
405			};
406
407			uartc_txd_rts {
408				nvidia,pins = "uart3_rts_n_pc0",
409						"uart3_txd_pw6";
410				nvidia,function = "uartc";
411				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412				nvidia,tristate = <TEGRA_PIN_DISABLE>;
413				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414			};
415
416			/* UART-D */
417			ulpi_nxt_py2 {
418				nvidia,pins = "ulpi_nxt_py2";
419				nvidia,function = "uartd";
420				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421				nvidia,tristate = <TEGRA_PIN_ENABLE>;
422				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423			};
424
425			ulpi_clk_py0 {
426				nvidia,pins = "ulpi_clk_py0",
427						"ulpi_dir_py1",
428						"ulpi_stp_py3";
429				nvidia,function = "uartd";
430				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431				nvidia,tristate = <TEGRA_PIN_ENABLE>;
432				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433			};
434
435			/* I2S pinmux */
436			dap_i2s0 {
437				nvidia,pins = "dap1_fs_pn0",
438						"dap1_din_pn1",
439						"dap1_dout_pn2",
440						"dap1_sclk_pn3";
441				nvidia,function = "i2s0";
442				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443				nvidia,tristate = <TEGRA_PIN_ENABLE>;
444				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445			};
446
447			dap_i2s1 {
448				nvidia,pins = "dap2_fs_pa2",
449						"dap2_sclk_pa3",
450						"dap2_din_pa4",
451						"dap2_dout_pa5";
452				nvidia,function = "i2s1";
453				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454				nvidia,tristate = <TEGRA_PIN_DISABLE>;
455				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456			};
457
458			dap3_fs {
459				nvidia,pins = "dap3_fs_pp0",
460						"dap3_din_pp1";
461				nvidia,function = "i2s2";
462				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463				nvidia,tristate = <TEGRA_PIN_ENABLE>;
464				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465			};
466
467			dap3_dout {
468				nvidia,pins = "dap3_dout_pp2",
469						"dap3_sclk_pp3";
470				nvidia,function = "i2s2";
471				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472				nvidia,tristate = <TEGRA_PIN_DISABLE>;
473				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474			};
475
476			dap_i2s3 {
477				nvidia,pins = "dap4_fs_pp4",
478						"dap4_din_pp5",
479						"dap4_dout_pp6",
480						"dap4_sclk_pp7";
481				nvidia,function = "i2s3";
482				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483				nvidia,tristate = <TEGRA_PIN_DISABLE>;
484				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
485			};
486
487			/* Sensors pinmux */
488			nct_irq {
489				nvidia,pins = "pcc2";
490				nvidia,function = "i2s4";
491				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
492				nvidia,tristate = <TEGRA_PIN_DISABLE>;
493				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494			};
495
496			/* Asus EC pinmux */
497			ec_irqs {
498				nvidia,pins = "kb_row10_ps2",
499						"kb_row15_ps7";
500				nvidia,function = "kbc";
501				nvidia,pull = <TEGRA_PIN_PULL_UP>;
502				nvidia,tristate = <TEGRA_PIN_DISABLE>;
503				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504			};
505
506			ec_reqs {
507				nvidia,pins = "kb_col1_pq1";
508				nvidia,function = "kbc";
509				nvidia,pull = <TEGRA_PIN_PULL_UP>;
510				nvidia,tristate = <TEGRA_PIN_DISABLE>;
511				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512			};
513
514			/* Memory type bootstrap */
515			mem_boostraps {
516				nvidia,pins = "gmi_ad4_pg4",
517						"gmi_ad5_pg5";
518				nvidia,function = "nand";
519				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520				nvidia,tristate = <TEGRA_PIN_DISABLE>;
521				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522			};
523
524			/* PCI-e pinmux */
525			pex_l2_rst_n {
526				nvidia,pins = "pex_l2_rst_n_pcc6",
527						"pex_l0_rst_n_pdd1",
528						"pex_l1_rst_n_pdd5";
529				nvidia,function = "pcie";
530				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531				nvidia,tristate = <TEGRA_PIN_DISABLE>;
532				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533			};
534
535			pex_l2_clkreq_n {
536				nvidia,pins = "pex_l2_clkreq_n_pcc7",
537						"pex_l0_prsnt_n_pdd0",
538						"pex_l0_clkreq_n_pdd2",
539						"pex_wake_n_pdd3",
540						"pex_l1_prsnt_n_pdd4",
541						"pex_l1_clkreq_n_pdd6",
542						"pex_l2_prsnt_n_pdd7";
543				nvidia,function = "pcie";
544				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545				nvidia,tristate = <TEGRA_PIN_DISABLE>;
546				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547			};
548
549			/* SPI pinmux */
550			spi1_mosi_px4 {
551				nvidia,pins = "spi1_mosi_px4",
552						"spi1_sck_px5",
553						"spi1_cs0_n_px6",
554						"spi1_miso_px7";
555				nvidia,function = "spi1";
556				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557				nvidia,tristate = <TEGRA_PIN_ENABLE>;
558				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
559			};
560
561			hp_detect {
562				nvidia,pins = "spi2_cs1_n_pw2";
563				nvidia,function = "spi2";
564				nvidia,pull = <TEGRA_PIN_PULL_UP>;
565				nvidia,tristate = <TEGRA_PIN_DISABLE>;
566				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567			};
568
569			mic_detect {
570				nvidia,pins = "spi2_sck_px2";
571				nvidia,function = "spi2";
572				nvidia,pull = <TEGRA_PIN_PULL_UP>;
573				nvidia,tristate = <TEGRA_PIN_DISABLE>;
574				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
575			};
576
577			gmi_a17_pb0 {
578				nvidia,pins = "gmi_a17_pb0",
579						"gmi_a16_pj7";
580				nvidia,function = "spi4";
581				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582				nvidia,tristate = <TEGRA_PIN_ENABLE>;
583				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
584			};
585
586			gmi_a18_pb1 {
587				nvidia,pins = "gmi_a18_pb1";
588				nvidia,function = "spi4";
589				nvidia,pull = <TEGRA_PIN_PULL_UP>;
590				nvidia,tristate = <TEGRA_PIN_DISABLE>;
591				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592			};
593
594			gmi_a19_pk7 {
595				nvidia,pins = "gmi_a19_pk7";
596				nvidia,function = "spi4";
597				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598				nvidia,tristate = <TEGRA_PIN_DISABLE>;
599				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600			};
601
602			/* Display A pinmux */
603			lcd_pwr0_pb2 {
604				nvidia,pins = "lcd_pwr0_pb2",
605						"lcd_pclk_pb3",
606						"lcd_pwr1_pc1",
607						"lcd_d0_pe0",
608						"lcd_d1_pe1",
609						"lcd_d2_pe2",
610						"lcd_d3_pe3",
611						"lcd_d4_pe4",
612						"lcd_d5_pe5",
613						"lcd_d6_pe6",
614						"lcd_d7_pe7",
615						"lcd_d8_pf0",
616						"lcd_d9_pf1",
617						"lcd_d10_pf2",
618						"lcd_d11_pf3",
619						"lcd_d12_pf4",
620						"lcd_d13_pf5",
621						"lcd_d14_pf6",
622						"lcd_d15_pf7",
623						"lcd_de_pj1",
624						"lcd_hsync_pj3",
625						"lcd_vsync_pj4",
626						"lcd_d16_pm0",
627						"lcd_d17_pm1",
628						"lcd_d18_pm2",
629						"lcd_d19_pm3",
630						"lcd_d20_pm4",
631						"lcd_d21_pm5",
632						"lcd_d22_pm6",
633						"lcd_d23_pm7",
634						"lcd_dc0_pn6",
635						"lcd_sdin_pz2";
636				nvidia,function = "displaya";
637				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638				nvidia,tristate = <TEGRA_PIN_DISABLE>;
639				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
640			};
641
642			lcd_cs0_n_pn4 {
643				nvidia,pins = "lcd_cs0_n_pn4",
644						"lcd_sdout_pn5",
645						"lcd_wr_n_pz3";
646				nvidia,function = "displaya";
647				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648				nvidia,tristate = <TEGRA_PIN_ENABLE>;
649				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
650			};
651
652			blink {
653				nvidia,pins = "clk_32k_out_pa0";
654				nvidia,function = "blink";
655				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656				nvidia,tristate = <TEGRA_PIN_DISABLE>;
657				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658			};
659
660			/* KBC keys */
661			kb_col0_pq0 {
662				nvidia,pins = "kb_col0_pq0";
663				nvidia,function = "kbc";
664				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665				nvidia,tristate = <TEGRA_PIN_ENABLE>;
666				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
667			};
668
669			kb_col1_pq1 {
670				nvidia,pins = "kb_row1_pr1",
671						"kb_row3_pr3",
672						"kb_row8_ps0",
673						"kb_row14_ps6";
674				nvidia,function = "kbc";
675				nvidia,pull = <TEGRA_PIN_PULL_UP>;
676				nvidia,tristate = <TEGRA_PIN_DISABLE>;
677				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678			};
679
680			kb_col4_pq4 {
681				nvidia,pins = "kb_col4_pq4",
682						"kb_col5_pq5",
683						"kb_col7_pq7",
684						"kb_row2_pr2",
685						"kb_row4_pr4",
686						"kb_row5_pr5",
687						"kb_row12_ps4",
688						"kb_row13_ps5";
689				nvidia,function = "kbc";
690				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
691				nvidia,tristate = <TEGRA_PIN_ENABLE>;
692				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
693			};
694
695			gmi_wp_n_pc7 {
696				nvidia,pins = "gmi_wp_n_pc7",
697						"gmi_wait_pi7",
698						"gmi_cs3_n_pk4";
699				nvidia,function = "rsvd1";
700				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701				nvidia,tristate = <TEGRA_PIN_ENABLE>;
702				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703			};
704
705			gmi_cs0_n_pj0 {
706				nvidia,pins = "gmi_cs0_n_pj0",
707						"gmi_cs1_n_pj2",
708						"gmi_cs2_n_pk3";
709				nvidia,function = "rsvd1";
710				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711				nvidia,tristate = <TEGRA_PIN_ENABLE>;
712				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713			};
714
715			vi_pclk_pt0 {
716				nvidia,pins = "vi_pclk_pt0";
717				nvidia,function = "rsvd1";
718				nvidia,pull = <TEGRA_PIN_PULL_UP>;
719				nvidia,tristate = <TEGRA_PIN_ENABLE>;
720				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721				nvidia,lock = <0>;
722				nvidia,io-reset = <0>;
723			};
724
725			/* GPIO keys pinmux */
726			power_key {
727				nvidia,pins = "pv0";
728				nvidia,function = "rsvd1";
729				nvidia,pull = <TEGRA_PIN_PULL_UP>;
730				nvidia,tristate = <TEGRA_PIN_ENABLE>;
731				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
732			};
733
734			vol_keys {
735				nvidia,pins = "kb_col2_pq2",
736						"kb_col3_pq3";
737				nvidia,function = "rsvd4";
738				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739				nvidia,tristate = <TEGRA_PIN_ENABLE>;
740				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741			};
742
743			/* Bluetooth */
744			bt_shutdown {
745				nvidia,pins = "pu0";
746				nvidia,function = "rsvd4";
747				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748				nvidia,tristate = <TEGRA_PIN_DISABLE>;
749				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
750			};
751
752			bt_dev_wake {
753				nvidia,pins = "pu1";
754				nvidia,function = "rsvd1";
755				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756				nvidia,tristate = <TEGRA_PIN_DISABLE>;
757				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758			};
759
760			bt_host_wake {
761				nvidia,pins = "pu6";
762				nvidia,function = "rsvd4";
763				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764				nvidia,tristate = <TEGRA_PIN_DISABLE>;
765				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766			};
767
768			pu2 {
769				nvidia,pins = "pu2";
770				nvidia,function = "rsvd1";
771				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772				nvidia,tristate = <TEGRA_PIN_DISABLE>;
773				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774			};
775
776			pu3 {
777				nvidia,pins = "pu3";
778				nvidia,function = "rsvd4";
779				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780				nvidia,tristate = <TEGRA_PIN_DISABLE>;
781				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782			};
783
784			pcc1 {
785				nvidia,pins = "pcc1";
786				nvidia,function = "rsvd2";
787				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
788				nvidia,tristate = <TEGRA_PIN_ENABLE>;
789				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
790			};
791
792			pv2 {
793				nvidia,pins = "pv2";
794				nvidia,function = "rsvd2";
795				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796				nvidia,tristate = <TEGRA_PIN_DISABLE>;
797				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798			};
799
800			pv3 {
801				nvidia,pins = "pv3";
802				nvidia,function = "rsvd2";
803				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804				nvidia,tristate = <TEGRA_PIN_ENABLE>;
805				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806			};
807
808			vi_vsync_pd6 {
809				nvidia,pins = "vi_vsync_pd6",
810						"vi_hsync_pd7";
811				nvidia,function = "rsvd2";
812				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813				nvidia,tristate = <TEGRA_PIN_DISABLE>;
814				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815				nvidia,lock = <0>;
816				nvidia,io-reset = <0>;
817			};
818
819			vi_d10_pt2 {
820				nvidia,pins = "vi_d10_pt2",
821						"vi_d0_pt4", "pbb0";
822				nvidia,function = "rsvd2";
823				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824				nvidia,tristate = <TEGRA_PIN_DISABLE>;
825				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826			};
827
828			kb_row0_pr0 {
829				nvidia,pins = "kb_row0_pr0";
830				nvidia,function = "rsvd4";
831				nvidia,pull = <TEGRA_PIN_PULL_UP>;
832				nvidia,tristate = <TEGRA_PIN_DISABLE>;
833				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
834			};
835
836			gmi_ad0_pg0 {
837				nvidia,pins = "gmi_ad0_pg0",
838						"gmi_ad1_pg1",
839						"gmi_ad2_pg2",
840						"gmi_ad3_pg3",
841						"gmi_ad6_pg6",
842						"gmi_ad7_pg7",
843						"gmi_wr_n_pi0",
844						"gmi_oe_n_pi1",
845						"gmi_dqs_pi2",
846						"gmi_adv_n_pk0",
847						"gmi_clk_pk1";
848				nvidia,function = "nand";
849				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850				nvidia,tristate = <TEGRA_PIN_ENABLE>;
851				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
852			};
853
854			gmi_ad13_ph5 {
855				nvidia,pins = "gmi_ad13_ph5";
856				nvidia,function = "nand";
857				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
858				nvidia,tristate = <TEGRA_PIN_DISABLE>;
859				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
860			};
861
862			gmi_ad10_ph2 {
863				nvidia,pins = "gmi_ad10_ph2",
864						"gmi_ad11_ph3",
865						"gmi_ad14_ph6";
866				nvidia,function = "nand";
867				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
868				nvidia,tristate = <TEGRA_PIN_DISABLE>;
869				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
870			};
871
872			gmi_ad12_ph4 {
873				nvidia,pins = "gmi_ad12_ph4",
874						"gmi_rst_n_pi4",
875						"gmi_cs7_n_pi6";
876				nvidia,function = "nand";
877				nvidia,pull = <TEGRA_PIN_PULL_UP>;
878				nvidia,tristate = <TEGRA_PIN_DISABLE>;
879				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
880			};
881
882			/* Vibrator control */
883			vibrator {
884				nvidia,pins = "gmi_ad15_ph7";
885				nvidia,function = "nand";
886				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
887				nvidia,tristate = <TEGRA_PIN_DISABLE>;
888				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
889			};
890
891			/* PWM pimnmux */
892			pwm_0 {
893				nvidia,pins = "gmi_ad8_ph0";
894				nvidia,function = "pwm0";
895				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896				nvidia,tristate = <TEGRA_PIN_DISABLE>;
897				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
898			};
899
900			pwm_2 {
901				nvidia,pins = "pu5";
902				nvidia,function = "pwm2";
903				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904				nvidia,tristate = <TEGRA_PIN_DISABLE>;
905				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906			};
907
908			gmi_cs6_n_pi3 {
909				nvidia,pins = "gmi_cs6_n_pi3";
910				nvidia,function = "gmi";
911				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
912				nvidia,tristate = <TEGRA_PIN_ENABLE>;
913				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
914			};
915
916			/* Spdif pinmux */
917			spdif_out {
918				nvidia,pins = "spdif_out_pk5";
919				nvidia,function = "spdif";
920				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
921				nvidia,tristate = <TEGRA_PIN_ENABLE>;
922				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
923			};
924
925			spdif_in {
926				nvidia,pins = "spdif_in_pk6";
927				nvidia,function = "spdif";
928				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
929				nvidia,tristate = <TEGRA_PIN_ENABLE>;
930				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
931			};
932
933			vi_d4_pl2 {
934				nvidia,pins = "vi_d4_pl2";
935				nvidia,function = "vi";
936				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937				nvidia,tristate = <TEGRA_PIN_DISABLE>;
938				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939			};
940
941			vi_d6_pl4 {
942				nvidia,pins = "vi_d6_pl4";
943				nvidia,function = "vi";
944				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945				nvidia,tristate = <TEGRA_PIN_DISABLE>;
946				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
947				nvidia,lock = <0>;
948				nvidia,io-reset = <0>;
949			};
950
951			vi_mclk_pt1 {
952				nvidia,pins = "vi_mclk_pt1";
953				nvidia,function = "vi";
954				nvidia,pull = <TEGRA_PIN_PULL_UP>;
955				nvidia,tristate = <TEGRA_PIN_DISABLE>;
956				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
957			};
958
959			jtag_rtck {
960				nvidia,pins = "jtag_rtck_pu7";
961				nvidia,function = "rtck";
962				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963				nvidia,tristate = <TEGRA_PIN_DISABLE>;
964				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
965			};
966
967			crt_hsync_pv6 {
968				nvidia,pins = "crt_hsync_pv6",
969						"crt_vsync_pv7";
970				nvidia,function = "crt";
971				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972				nvidia,tristate = <TEGRA_PIN_ENABLE>;
973				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974			};
975
976			clk1_out {
977				nvidia,pins = "clk1_out_pw4";
978				nvidia,function = "extperiph1";
979				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980				nvidia,tristate = <TEGRA_PIN_DISABLE>;
981				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982			};
983
984			clk2_out {
985				nvidia,pins = "clk2_out_pw5";
986				nvidia,function = "extperiph2";
987				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988				nvidia,tristate = <TEGRA_PIN_DISABLE>;
989				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
990			};
991
992			clk3_out {
993				nvidia,pins = "clk3_out_pee0";
994				nvidia,function = "extperiph3";
995				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
996				nvidia,tristate = <TEGRA_PIN_ENABLE>;
997				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
998			};
999
1000			sys_clk_req {
1001				nvidia,pins = "sys_clk_req_pz5";
1002				nvidia,function = "sysclk";
1003				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006			};
1007
1008			pbb4 {
1009				nvidia,pins = "pbb4";
1010				nvidia,function = "vgp4";
1011				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1012				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1013				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1014			};
1015
1016			pbb5 {
1017				nvidia,pins = "pbb5";
1018				nvidia,function = "vgp5";
1019				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1020				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1021				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1022			};
1023
1024			pbb6 {
1025				nvidia,pins = "pbb6";
1026				nvidia,function = "vgp6";
1027				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1028				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1029				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1030			};
1031
1032			clk2_req_pcc5 {
1033				nvidia,pins = "clk2_req_pcc5",
1034						"clk1_req_pee2";
1035				nvidia,function = "dap";
1036				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1037				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1038				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1039			};
1040
1041			clk3_req_pee1 {
1042				nvidia,pins = "clk3_req_pee1";
1043				nvidia,function = "dev3";
1044				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1045				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1046				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047			};
1048
1049			owr {
1050				nvidia,pins = "owr";
1051				nvidia,function = "owr";
1052				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1053				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1054				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1055			};
1056
1057			/* GPIO power/drive control */
1058			drive_dap1 {
1059				nvidia,pins = "drive_dap1",
1060						"drive_dap2",
1061						"drive_dbg",
1062						"drive_at5",
1063						"drive_gme",
1064						"drive_ddc",
1065						"drive_ao1",
1066						"drive_uart3";
1067				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1068				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1069				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1070				nvidia,pull-down-strength = <31>;
1071				nvidia,pull-up-strength = <31>;
1072				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1073				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1074			};
1075
1076			drive_sdio1 {
1077				nvidia,pins = "drive_sdio1",
1078						"drive_sdio3";
1079				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1080				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1081				nvidia,pull-down-strength = <46>;
1082				nvidia,pull-up-strength = <42>;
1083				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1084				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1085			};
1086		};
1087	};
1088
1089	serial@70006040 {
1090		compatible = "nvidia,tegra30-hsuart";
1091		reset-names = "serial";
1092		/delete-property/ reg-shift;
1093		status = "okay";
1094
1095		/* Broadcom GPS BCM47511 */
1096	};
1097
1098	serial@70006200 {
1099		compatible = "nvidia,tegra30-hsuart";
1100		reset-names = "serial";
1101		/delete-property/ reg-shift;
1102		status = "okay";
1103
1104		nvidia,adjust-baud-rates = <0 9600 100>,
1105					   <9600 115200 200>,
1106					   <1000000 4000000 136>;
1107
1108		bluetooth {
1109			max-speed = <4000000>;
1110
1111			clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1112			clock-names = "txco";
1113
1114			interrupt-parent = <&gpio>;
1115			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
1116			interrupt-names = "host-wakeup";
1117
1118			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
1119			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
1120
1121			vbat-supply  = <&vdd_3v3_com>;
1122			vddio-supply = <&vdd_1v8_vio>;
1123		};
1124	};
1125
1126	pwm@7000a000 {
1127		status = "okay";
1128	};
1129
1130	lcd_ddc: i2c@7000c000 {
1131		status = "okay";
1132		clock-frequency = <100000>;
1133	};
1134
1135	i2c@7000c400 {
1136		status = "okay";
1137		clock-frequency = <400000>;
1138	};
1139
1140	i2c@7000c500 {
1141		status = "okay";
1142
1143		/* Aichi AMI306 digital compass */
1144		magnetometer@e {
1145			compatible = "asahi-kasei,ak8974";
1146			reg = <0x0e>;
1147
1148			avdd-supply = <&vdd_3v3_sys>;
1149			dvdd-supply = <&vdd_1v8_vio>;
1150		};
1151
1152		/* Dynaimage ambient light sensor */
1153		light-sensor@1c {
1154			compatible = "dynaimage,al3010";
1155			reg = <0x1c>;
1156
1157			interrupt-parent = <&gpio>;
1158			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
1159
1160			vdd-supply = <&vdd_3v3_sys>;
1161		};
1162
1163		gyroscope@68 {
1164			compatible = "invensense,mpu3050";
1165			reg = <0x68>;
1166
1167			interrupt-parent = <&gpio>;
1168			interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1169
1170			vdd-supply    = <&vdd_3v3_sys>;
1171			vlogic-supply = <&vdd_1v8_vio>;
1172
1173			i2c-gate {
1174				#address-cells = <1>;
1175				#size-cells = <0>;
1176
1177				accelerometer@f {
1178					compatible = "kionix,kxtf9";
1179					reg = <0x0f>;
1180
1181					interrupt-parent = <&gpio>;
1182					interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1183
1184					vdd-supply = <&vdd_1v8_vio>;
1185					vddio-supply = <&vdd_1v8_vio>;
1186				};
1187			};
1188		};
1189	};
1190
1191	hdmi_ddc: i2c@7000c700 {
1192		status = "okay";
1193		clock-frequency = <93750>;
1194	};
1195
1196	i2c@7000d000 {
1197		status = "okay";
1198		clock-frequency = <400000>;
1199
1200		/* Texas Instruments TPS659110 PMIC */
1201		pmic: pmic@2d {
1202			compatible = "ti,tps65911";
1203			reg = <0x2d>;
1204
1205			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1206			#interrupt-cells = <2>;
1207			interrupt-controller;
1208			wakeup-source;
1209
1210			ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1211			ti,system-power-controller;
1212			ti,sleep-keep-ck32k;
1213			ti,sleep-enable;
1214
1215			#gpio-cells = <2>;
1216			gpio-controller;
1217
1218			vcc1-supply = <&vdd_5v0_bat>;
1219			vcc2-supply = <&vdd_5v0_bat>;
1220			vcc3-supply = <&vdd_1v8_vio>;
1221			vcc4-supply = <&vdd_5v0_sys>;
1222			vcc5-supply = <&vdd_5v0_bat>;
1223			vcc6-supply = <&vdd_3v3_sys>;
1224			vcc7-supply = <&vdd_5v0_bat>;
1225			vccio-supply = <&vdd_5v0_bat>;
1226
1227			pmic-sleep-hog {
1228				gpio-hog;
1229				gpios = <2 GPIO_ACTIVE_HIGH>;
1230				output-high;
1231			};
1232
1233			regulators {
1234				/* VDD1 is not used by Transformers */
1235
1236				vddio_ddr: vdd2 {
1237					regulator-name = "vddio_ddr";
1238					regulator-min-microvolt = <1200000>;
1239					regulator-max-microvolt = <1200000>;
1240					regulator-always-on;
1241					regulator-boot-on;
1242				};
1243
1244				vdd_cpu: vddctrl {
1245					regulator-name = "vdd_cpu,vdd_sys";
1246					regulator-min-microvolt = <600000>;
1247					regulator-max-microvolt = <1400000>;
1248					regulator-coupled-with = <&vdd_core>;
1249					regulator-coupled-max-spread = <300000>;
1250					regulator-max-step-microvolt = <100000>;
1251					regulator-always-on;
1252					regulator-boot-on;
1253					ti,regulator-ext-sleep-control = <1>;
1254
1255					nvidia,tegra-cpu-regulator;
1256				};
1257
1258				vdd_1v8_vio: vio {
1259					regulator-name = "vdd_1v8_gen";
1260					/* FIXME: eMMC won't work, if set to 1.8 V */
1261					regulator-min-microvolt = <1500000>;
1262					regulator-max-microvolt = <3300000>;
1263					regulator-always-on;
1264					regulator-boot-on;
1265				};
1266
1267				/* eMMC VDD */
1268				vcore_emmc: ldo1 {
1269					regulator-name = "vdd_emmc_core";
1270					regulator-min-microvolt = <3300000>;
1271					regulator-max-microvolt = <3300000>;
1272					regulator-always-on;
1273				};
1274
1275				/* uSD slot VDD */
1276				vdd_usd: ldo2 {
1277					regulator-name = "vdd_usd";
1278					regulator-min-microvolt = <3100000>;
1279					regulator-max-microvolt = <3100000>;
1280					/* FIXME: Without this, voltage switching fails */
1281					regulator-always-on;
1282				};
1283
1284				/* uSD slot VDDIO */
1285				vddio_usd: ldo3 {
1286					regulator-name = "vddio_usd";
1287					regulator-min-microvolt = <1800000>;
1288					regulator-max-microvolt = <3100000>;
1289				};
1290
1291				ldo4 {
1292					regulator-name = "vdd_rtc";
1293					regulator-min-microvolt = <1200000>;
1294					regulator-max-microvolt = <1200000>;
1295					regulator-always-on;
1296				};
1297
1298				/* LDO5 is not used by Transformers */
1299
1300				ldo6 {
1301					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1302					regulator-min-microvolt = <1200000>;
1303					regulator-max-microvolt = <1200000>;
1304				};
1305
1306				ldo7 {
1307					regulator-name = "vdd_pllm,x,u,a_p_c_s";
1308					regulator-min-microvolt = <1200000>;
1309					regulator-max-microvolt = <1200000>;
1310					regulator-always-on;
1311					regulator-boot-on;
1312					ti,regulator-ext-sleep-control = <8>;
1313				};
1314
1315				ldo8 {
1316					regulator-name = "vdd_ddr_hs";
1317					regulator-min-microvolt = <1000000>;
1318					regulator-max-microvolt = <1000000>;
1319					regulator-always-on;
1320					ti,regulator-ext-sleep-control = <8>;
1321				};
1322			};
1323		};
1324
1325		nct72: temperature-sensor@4c {
1326			compatible = "onnn,nct1008";
1327			reg = <0x4c>;
1328
1329			interrupt-parent = <&gpio>;
1330			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1331
1332			vcc-supply = <&vdd_3v3_sys>;
1333			#thermal-sensor-cells = <1>;
1334		};
1335
1336		vdd_core: core-regulator@60 {
1337			compatible = "ti,tps62361";
1338			reg = <0x60>;
1339
1340			regulator-name = "tps62361-vout";
1341			regulator-min-microvolt = <500000>;
1342			regulator-max-microvolt = <1770000>;
1343			regulator-coupled-with = <&vdd_cpu>;
1344			regulator-coupled-max-spread = <300000>;
1345			regulator-max-step-microvolt = <100000>;
1346			regulator-boot-on;
1347			regulator-always-on;
1348			ti,enable-vout-discharge;
1349			ti,vsel0-state-high;
1350			ti,vsel1-state-high;
1351
1352			nvidia,tegra-core-regulator;
1353		};
1354	};
1355
1356	pmc@7000e400 {
1357		status = "okay";
1358		nvidia,invert-interrupt;
1359		/* FIXME: LP1 doesn't work at the moment */
1360		nvidia,suspend-mode = <2>;
1361		nvidia,cpu-pwr-good-time = <2000>;
1362		nvidia,cpu-pwr-off-time = <200>;
1363		nvidia,core-pwr-good-time = <3845 3845>;
1364		nvidia,core-pwr-off-time = <0>;
1365		nvidia,core-power-req-active-high;
1366		nvidia,sys-clock-req-active-high;
1367		core-supply = <&vdd_core>;
1368
1369		/* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC  */
1370		i2c-thermtrip {
1371			nvidia,i2c-controller-id = <4>;
1372			nvidia,bus-addr = <0x2d>;
1373			nvidia,reg-addr = <0x3f>;
1374			nvidia,reg-data = <0x81>;
1375		};
1376	};
1377
1378	hda@70030000 {
1379		status = "okay";
1380	};
1381
1382	ahub@70080000 {
1383		i2s@70080400 {		/* i2s1 */
1384			status = "okay";
1385		};
1386
1387		/* BT SCO */
1388		i2s@70080600 {		/* i2s3 */
1389			status = "okay";
1390		};
1391	};
1392
1393	mmc@78000000 {
1394		status = "okay";
1395
1396		/* FIXME: Full 208Mhz clock rate doesn't work reliably */
1397		max-frequency = <104000000>;
1398
1399		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1400		bus-width = <4>;
1401
1402		vmmc-supply = <&vdd_usd>;	/* ldo2 */
1403		vqmmc-supply = <&vddio_usd>;	/* ldo3 */
1404	};
1405
1406	mmc@78000400 {
1407		status = "okay";
1408
1409		#address-cells = <1>;
1410		#size-cells = <0>;
1411
1412		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1413		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1414		assigned-clock-rates = <50000000>;
1415
1416		max-frequency = <50000000>;
1417		keep-power-in-suspend;
1418		bus-width = <4>;
1419		non-removable;
1420
1421		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1422		vmmc-supply = <&vdd_3v3_com>;
1423		vqmmc-supply = <&vdd_1v8_vio>;
1424
1425		/* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
1426		wifi@1 {
1427			compatible = "brcm,bcm4329-fmac";
1428			reg = <1>;
1429
1430			interrupt-parent = <&gpio>;
1431			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1432			interrupt-names = "host-wake";
1433		};
1434	};
1435
1436	mmc@78000600 {
1437		status = "okay";
1438		bus-width = <8>;
1439		vmmc-supply = <&vcore_emmc>;
1440		vqmmc-supply = <&vdd_1v8_vio>;
1441		mmc-ddr-3_3v;
1442		non-removable;
1443	};
1444
1445	/* USB via ASUS connector */
1446	usb@7d000000 {
1447		compatible = "nvidia,tegra30-udc";
1448		status = "okay";
1449		dr_mode = "peripheral";
1450	};
1451
1452	usb-phy@7d000000 {
1453		status = "okay";
1454		dr_mode = "peripheral";
1455		nvidia,hssync-start-delay = <0>;
1456		nvidia,xcvr-lsfslew = <2>;
1457		nvidia,xcvr-lsrslew = <2>;
1458		vbus-supply = <&vdd_5v0_sys>;
1459	};
1460
1461	/* Dock's USB port */
1462	usb@7d008000 {
1463		status = "okay";
1464	};
1465
1466	usb-phy@7d008000 {
1467		status = "okay";
1468		vbus-supply = <&vdd_5v0_bat>;
1469	};
1470
1471	mains: ac-adapter-detect {
1472		compatible = "gpio-charger";
1473		charger-type = "mains";
1474		gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1475	};
1476
1477	backlight: backlight {
1478		compatible = "pwm-backlight";
1479
1480		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1481		power-supply = <&vdd_5v0_bl>;
1482		pwms = <&pwm 0 4000000>;
1483
1484		brightness-levels = <1 255>;
1485		num-interpolated-steps = <254>;
1486		default-brightness-level = <40>;
1487	};
1488
1489	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1490	clk32k_in: clock-32k {
1491		compatible = "fixed-clock";
1492		#clock-cells = <0>;
1493		clock-frequency = <32768>;
1494		clock-output-names = "pmic-oscillator";
1495	};
1496
1497	cpus {
1498		cpu0: cpu@0 {
1499			cpu-supply = <&vdd_cpu>;
1500			operating-points-v2 = <&cpu0_opp_table>;
1501			#cooling-cells = <2>;
1502		};
1503		cpu1: cpu@1 {
1504			cpu-supply = <&vdd_cpu>;
1505			operating-points-v2 = <&cpu0_opp_table>;
1506			#cooling-cells = <2>;
1507		};
1508		cpu2: cpu@2 {
1509			cpu-supply = <&vdd_cpu>;
1510			operating-points-v2 = <&cpu0_opp_table>;
1511			#cooling-cells = <2>;
1512		};
1513		cpu3: cpu@3 {
1514			cpu-supply = <&vdd_cpu>;
1515			operating-points-v2 = <&cpu0_opp_table>;
1516			#cooling-cells = <2>;
1517		};
1518	};
1519
1520	extcon-keys {
1521		compatible = "gpio-keys";
1522
1523		switch-dock-hall-sensor {
1524			label = "Lid sensor";
1525			gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1526			linux,input-type = <EV_SW>;
1527			linux,code = <SW_LID>;
1528			debounce-interval = <500>;
1529			wakeup-event-action = <EV_ACT_ASSERTED>;
1530			wakeup-source;
1531		};
1532
1533		switch-lineout-detect {
1534			label = "Audio dock line-out detect";
1535			gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
1536			linux,input-type = <EV_SW>;
1537			linux,code = <SW_LINEOUT_INSERT>;
1538			debounce-interval = <10>;
1539			wakeup-event-action = <EV_ACT_ASSERTED>;
1540			wakeup-source;
1541		};
1542	};
1543
1544	gpio-keys {
1545		compatible = "gpio-keys";
1546
1547		key-power {
1548			label = "Power";
1549			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1550			linux,code = <KEY_POWER>;
1551			debounce-interval = <10>;
1552			wakeup-event-action = <EV_ACT_ASSERTED>;
1553			wakeup-source;
1554		};
1555
1556		key-volume-down {
1557			label = "Volume Down";
1558			gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1559			linux,code = <KEY_VOLUMEDOWN>;
1560			debounce-interval = <10>;
1561			wakeup-event-action = <EV_ACT_ASSERTED>;
1562			wakeup-source;
1563		};
1564
1565		key-volume-up {
1566			label = "Volume Up";
1567			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1568			linux,code = <KEY_VOLUMEUP>;
1569			debounce-interval = <10>;
1570			wakeup-event-action = <EV_ACT_ASSERTED>;
1571			wakeup-source;
1572		};
1573	};
1574
1575	vdd_5v0_bat: regulator-bat {
1576		compatible = "regulator-fixed";
1577		regulator-name = "vdd_ac_bat";
1578		regulator-min-microvolt = <5000000>;
1579		regulator-max-microvolt = <5000000>;
1580		regulator-always-on;
1581		regulator-boot-on;
1582	};
1583
1584	vdd_5v0_cp: regulator-sby {
1585		compatible = "regulator-fixed";
1586		regulator-name = "vdd_5v0_sby";
1587		regulator-min-microvolt = <5000000>;
1588		regulator-max-microvolt = <5000000>;
1589		regulator-always-on;
1590		regulator-boot-on;
1591		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1592		enable-active-high;
1593		vin-supply = <&vdd_5v0_bat>;
1594	};
1595
1596	vdd_5v0_sys: regulator-5v {
1597		compatible = "regulator-fixed";
1598		regulator-name = "vdd_5v0_sys";
1599		regulator-min-microvolt = <5000000>;
1600		regulator-max-microvolt = <5000000>;
1601		regulator-always-on;
1602		regulator-boot-on;
1603		gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1604		enable-active-high;
1605		vin-supply = <&vdd_5v0_bat>;
1606	};
1607
1608	vdd_1v5_ddr: regulator-ddr {
1609		compatible = "regulator-fixed";
1610		regulator-name = "vdd_ddr";
1611		regulator-min-microvolt = <1500000>;
1612		regulator-max-microvolt = <1500000>;
1613		regulator-always-on;
1614		regulator-boot-on;
1615		gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1616		enable-active-high;
1617		vin-supply = <&vdd_5v0_bat>;
1618	};
1619
1620	vdd_3v3_sys: regulator-3v {
1621		compatible = "regulator-fixed";
1622		regulator-name = "vdd_3v3_sys";
1623		regulator-min-microvolt = <3300000>;
1624		regulator-max-microvolt = <3300000>;
1625		regulator-always-on;
1626		regulator-boot-on;
1627		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1628		enable-active-high;
1629		vin-supply = <&vdd_5v0_bat>;
1630	};
1631
1632	vdd_pnl: regulator-panel {
1633		compatible = "regulator-fixed";
1634		regulator-name = "vdd_panel";
1635		regulator-min-microvolt = <3300000>;
1636		regulator-max-microvolt = <3300000>;
1637		regulator-enable-ramp-delay = <20000>;
1638		gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1639		enable-active-high;
1640		vin-supply = <&vdd_3v3_sys>;
1641	};
1642
1643	vdd_3v3_com: regulator-com {
1644		compatible = "regulator-fixed";
1645		regulator-name = "vdd_3v3_com";
1646		regulator-min-microvolt = <3300000>;
1647		regulator-max-microvolt = <3300000>;
1648		regulator-always-on;
1649		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1650		enable-active-high;
1651		vin-supply = <&vdd_3v3_sys>;
1652	};
1653
1654	vdd_5v0_bl: regulator-bl {
1655		compatible = "regulator-fixed";
1656		regulator-name = "vdd_5v0_bl";
1657		regulator-min-microvolt = <5000000>;
1658		regulator-max-microvolt = <5000000>;
1659		regulator-boot-on;
1660		gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1661		enable-active-high;
1662		vin-supply = <&vdd_5v0_bat>;
1663	};
1664
1665	hdmi_5v0_sys: regulator-hdmi {
1666		compatible = "regulator-fixed";
1667		regulator-name = "hdmi_5v0_sys";
1668		regulator-min-microvolt = <5000000>;
1669		regulator-max-microvolt = <5000000>;
1670		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1671		enable-active-high;
1672		vin-supply = <&vdd_5v0_sys>;
1673	};
1674
1675	sound {
1676		nvidia,i2s-controller = <&tegra_i2s1>;
1677
1678		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1679		nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
1680		nvidia,coupled-mic-hp-det;
1681
1682		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1683			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1684			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1685		clock-names = "pll_a", "pll_a_out0", "mclk";
1686
1687		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1688				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1689
1690		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1691					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1692	};
1693
1694	thermal-zones {
1695		/*
1696		 * NCT72 has two sensors:
1697		 *
1698		 *	0: internal that monitors ambient/skin temperature
1699		 *	1: external that is connected to the CPU's diode
1700		 *
1701		 * Ideally we should use userspace thermal governor,
1702		 * but it's a much more complex solution.  The "skin"
1703		 * zone exists as a simpler solution which prevents
1704		 * Transformers from getting too hot from a user's
1705		 * tactile perspective. The CPU zone is intended to
1706		 * protect silicon from damage.
1707		 */
1708
1709		skin-thermal {
1710			polling-delay-passive = <1000>; /* milliseconds */
1711			polling-delay = <5000>; /* milliseconds */
1712
1713			thermal-sensors = <&nct72 0>;
1714
1715			trips {
1716				trip0: skin-alert {
1717					/* throttle at 57C until temperature drops to 56.8C */
1718					temperature = <57000>;
1719					hysteresis = <200>;
1720					type = "passive";
1721				};
1722
1723				trip1: skin-crit {
1724					/* shut down at 65C */
1725					temperature = <65000>;
1726					hysteresis = <2000>;
1727					type = "critical";
1728				};
1729			};
1730
1731			cooling-maps {
1732				map0 {
1733					trip = <&trip0>;
1734					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1736							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1737							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1738							 <&actmon THERMAL_NO_LIMIT
1739								  THERMAL_NO_LIMIT>;
1740				};
1741			};
1742		};
1743
1744		cpu-thermal {
1745			polling-delay-passive = <1000>; /* milliseconds */
1746			polling-delay = <5000>; /* milliseconds */
1747
1748			thermal-sensors = <&nct72 1>;
1749
1750			trips {
1751				trip2: cpu-alert {
1752					/* throttle at 75C until temperature drops to 74.8C */
1753					temperature = <75000>;
1754					hysteresis = <200>;
1755					type = "passive";
1756				};
1757
1758				trip3: cpu-crit {
1759					/* shut down at 90C */
1760					temperature = <90000>;
1761					hysteresis = <2000>;
1762					type = "critical";
1763				};
1764			};
1765
1766			cooling-maps {
1767				map1 {
1768					trip = <&trip2>;
1769					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1772							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1773							 <&actmon THERMAL_NO_LIMIT
1774								  THERMAL_NO_LIMIT>;
1775				};
1776			};
1777		};
1778	};
1779
1780	brcm_wifi_pwrseq: wifi-pwrseq {
1781		compatible = "mmc-pwrseq-simple";
1782
1783		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1784		clock-names = "ext_clock";
1785
1786		reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1787		post-power-on-delay-ms = <300>;
1788		power-off-delay-us = <300>;
1789	};
1790};
1791