1// SPDX-License-Identifier: GPL-2.0
2#include "tegra30.dtsi"
3
4/*
5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
7 */
8/ {
9	memory@80000000 {
10		reg = <0x80000000 0x40000000>;
11	};
12
13	pcie@3000 {
14		status = "okay";
15		avdd-pexa-supply = <&vdd2_reg>;
16		avdd-pexb-supply = <&vdd2_reg>;
17		avdd-pex-pll-supply = <&vdd2_reg>;
18		avdd-plle-supply = <&ldo6_reg>;
19		hvdd-pex-supply = <&reg_module_3v3>;
20		vddio-pex-ctl-supply = <&reg_module_3v3>;
21		vdd-pexa-supply = <&vdd2_reg>;
22		vdd-pexb-supply = <&vdd2_reg>;
23
24		/* Apalis type specific */
25		pci@1,0 {
26			nvidia,num-lanes = <4>;
27		};
28
29		/* Apalis PCIe */
30		pci@2,0 {
31			nvidia,num-lanes = <1>;
32		};
33
34		/* I210/I211 Gigabit Ethernet Controller (on-module) */
35		pci@3,0 {
36			status = "okay";
37			nvidia,num-lanes = <1>;
38
39			ethernet@0,0 {
40				reg = <0 0 0 0 0>;
41				local-mac-address = [00 00 00 00 00 00];
42			};
43		};
44	};
45
46	host1x@50000000 {
47		hdmi@54280000 {
48			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
49			nvidia,hpd-gpio =
50				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
51			pll-supply = <&reg_1v8_avdd_hdmi_pll>;
52			vdd-supply = <&reg_3v3_avdd_hdmi>;
53		};
54	};
55
56	pinmux@70000868 {
57		pinctrl-names = "default";
58		pinctrl-0 = <&state_default>;
59
60		state_default: pinmux {
61			/* Analogue Audio (On-module) */
62			clk1-out-pw4 {
63				nvidia,pins = "clk1_out_pw4";
64				nvidia,function = "extperiph1";
65				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
66				nvidia,tristate = <TEGRA_PIN_DISABLE>;
67				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68			};
69			dap3-fs-pp0 {
70				nvidia,pins = "dap3_fs_pp0",
71					      "dap3_sclk_pp3",
72					      "dap3_din_pp1",
73					      "dap3_dout_pp2";
74				nvidia,function = "i2s2";
75				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
76				nvidia,tristate = <TEGRA_PIN_DISABLE>;
77			};
78
79			/* Apalis BKL1_ON */
80			pv2 {
81				nvidia,pins = "pv2";
82				nvidia,function = "rsvd4";
83				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84				nvidia,tristate = <TEGRA_PIN_DISABLE>;
85				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
86			};
87
88			/* Apalis BKL1_PWM */
89			uart3-rts-n-pc0 {
90				nvidia,pins = "uart3_rts_n_pc0";
91				nvidia,function = "pwm0";
92				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93				nvidia,tristate = <TEGRA_PIN_DISABLE>;
94				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95			};
96			/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
97			uart3-cts-n-pa1 {
98				nvidia,pins = "uart3_cts_n_pa1";
99				nvidia,function = "rsvd2";
100				nvidia,pull = <TEGRA_PIN_PULL_UP>;
101				nvidia,tristate = <TEGRA_PIN_DISABLE>;
102				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
103			};
104
105			/* Apalis CAN1 on SPI6 */
106			spi2-cs0-n-px3 {
107				nvidia,pins = "spi2_cs0_n_px3",
108					      "spi2_miso_px1",
109					      "spi2_mosi_px0",
110					      "spi2_sck_px2";
111				nvidia,function = "spi6";
112				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113				nvidia,tristate = <TEGRA_PIN_DISABLE>;
114			};
115			/* CAN_INT1 */
116			spi2-cs1-n-pw2 {
117				nvidia,pins = "spi2_cs1_n_pw2";
118				nvidia,function = "spi3";
119				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120				nvidia,tristate = <TEGRA_PIN_DISABLE>;
121				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122			};
123
124			/* Apalis CAN2 on SPI4 */
125			gmi-a16-pj7 {
126				nvidia,pins = "gmi_a16_pj7",
127					      "gmi_a17_pb0",
128					      "gmi_a18_pb1",
129					      "gmi_a19_pk7";
130				nvidia,function = "spi4";
131				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132				nvidia,tristate = <TEGRA_PIN_DISABLE>;
133				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
134			};
135			/* CAN_INT2 */
136			spi2-cs2-n-pw3 {
137				nvidia,pins = "spi2_cs2_n_pw3";
138				nvidia,function = "spi3";
139				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140				nvidia,tristate = <TEGRA_PIN_DISABLE>;
141				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142			};
143
144			/* Apalis Digital Audio */
145			clk1-req-pee2 {
146				nvidia,pins = "clk1_req_pee2";
147				nvidia,function = "hda";
148				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149				nvidia,tristate = <TEGRA_PIN_DISABLE>;
150			};
151			clk2-out-pw5 {
152				nvidia,pins = "clk2_out_pw5";
153				nvidia,function = "extperiph2";
154				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155				nvidia,tristate = <TEGRA_PIN_DISABLE>;
156				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
157			};
158			dap1-fs-pn0 {
159				nvidia,pins = "dap1_fs_pn0",
160					      "dap1_din_pn1",
161					      "dap1_dout_pn2",
162					      "dap1_sclk_pn3";
163				nvidia,function = "hda";
164				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165				nvidia,tristate = <TEGRA_PIN_DISABLE>;
166			};
167
168			/* Apalis GPIO */
169			kb-col0-pq0 {
170				nvidia,pins = "kb_col0_pq0",
171					      "kb_col1_pq1",
172					      "kb_row10_ps2",
173					      "kb_row11_ps3",
174					      "kb_row12_ps4",
175					      "kb_row13_ps5",
176					      "kb_row14_ps6",
177					      "kb_row15_ps7";
178				nvidia,function = "kbc";
179				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180				nvidia,tristate = <TEGRA_PIN_DISABLE>;
181				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182			};
183			/* Multiplexed and therefore disabled */
184			owr {
185				nvidia,pins = "owr";
186				nvidia,function = "rsvd3";
187				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
188				nvidia,tristate = <TEGRA_PIN_ENABLE>;
189				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
190			};
191
192			/* Apalis HDMI1 */
193			hdmi-cec-pee3 {
194				nvidia,pins = "hdmi_cec_pee3";
195				nvidia,function = "cec";
196				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197				nvidia,tristate = <TEGRA_PIN_DISABLE>;
198				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
199				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
200			};
201			hdmi-int-pn7 {
202				nvidia,pins = "hdmi_int_pn7";
203				nvidia,function = "hdmi";
204				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205				nvidia,tristate = <TEGRA_PIN_ENABLE>;
206				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207			};
208
209			/* Apalis I2C1 */
210			gen1-i2c-scl-pc4 {
211				nvidia,pins = "gen1_i2c_scl_pc4",
212					      "gen1_i2c_sda_pc5";
213				nvidia,function = "i2c1";
214				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215				nvidia,tristate = <TEGRA_PIN_DISABLE>;
216				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
218			};
219
220			/* Apalis I2C2 (DDC) */
221			ddc-scl-pv4 {
222				nvidia,pins = "ddc_scl_pv4",
223					      "ddc_sda_pv5";
224				nvidia,function = "i2c4";
225				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226				nvidia,tristate = <TEGRA_PIN_DISABLE>;
227				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228			};
229
230			/* Apalis I2C3 (CAM) */
231			cam-i2c-scl-pbb1 {
232				nvidia,pins = "cam_i2c_scl_pbb1",
233					      "cam_i2c_sda_pbb2";
234				nvidia,function = "i2c3";
235				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
239			};
240
241			/* Apalis LCD1 */
242			lcd-d0-pe0 {
243				nvidia,pins = "lcd_d0_pe0",
244					      "lcd_d1_pe1",
245					      "lcd_d2_pe2",
246					      "lcd_d3_pe3",
247					      "lcd_d4_pe4",
248					      "lcd_d5_pe5",
249					      "lcd_d6_pe6",
250					      "lcd_d7_pe7",
251					      "lcd_d8_pf0",
252					      "lcd_d9_pf1",
253					      "lcd_d10_pf2",
254					      "lcd_d11_pf3",
255					      "lcd_d12_pf4",
256					      "lcd_d13_pf5",
257					      "lcd_d14_pf6",
258					      "lcd_d15_pf7",
259					      "lcd_d16_pm0",
260					      "lcd_d17_pm1",
261					      "lcd_d18_pm2",
262					      "lcd_d19_pm3",
263					      "lcd_d20_pm4",
264					      "lcd_d21_pm5",
265					      "lcd_d22_pm6",
266					      "lcd_d23_pm7",
267					      "lcd_de_pj1",
268					      "lcd_hsync_pj3",
269					      "lcd_pclk_pb3",
270					      "lcd_vsync_pj4";
271				nvidia,function = "displaya";
272				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273				nvidia,tristate = <TEGRA_PIN_DISABLE>;
274				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
275			};
276
277			/* Apalis MMC1 */
278			sdmmc3-clk-pa6 {
279				nvidia,pins = "sdmmc3_clk_pa6";
280				nvidia,function = "sdmmc3";
281				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282				nvidia,tristate = <TEGRA_PIN_DISABLE>;
283			};
284			sdmmc3-dat0-pb7 {
285				nvidia,pins = "sdmmc3_cmd_pa7",
286					      "sdmmc3_dat0_pb7",
287					      "sdmmc3_dat1_pb6",
288					      "sdmmc3_dat2_pb5",
289					      "sdmmc3_dat3_pb4",
290					      "sdmmc3_dat4_pd1",
291					      "sdmmc3_dat5_pd0",
292					      "sdmmc3_dat6_pd3",
293					      "sdmmc3_dat7_pd4";
294				nvidia,function = "sdmmc3";
295				nvidia,pull = <TEGRA_PIN_PULL_UP>;
296				nvidia,tristate = <TEGRA_PIN_DISABLE>;
297			};
298			/* Apalis MMC1_CD# */
299			pv3 {
300				nvidia,pins = "pv3";
301				nvidia,function = "rsvd2";
302				nvidia,pull = <TEGRA_PIN_PULL_UP>;
303				nvidia,tristate = <TEGRA_PIN_DISABLE>;
304				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305			};
306
307			/* Apalis Parallel Camera */
308			cam-mclk-pcc0 {
309				nvidia,pins = "cam_mclk_pcc0";
310				nvidia,function = "vi_alt3";
311				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312				nvidia,tristate = <TEGRA_PIN_DISABLE>;
313				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
314			};
315			vi-vsync-pd6 {
316				nvidia,pins = "vi_d0_pt4",
317					      "vi_d1_pd5",
318					      "vi_d2_pl0",
319					      "vi_d3_pl1",
320					      "vi_d4_pl2",
321					      "vi_d5_pl3",
322					      "vi_d6_pl4",
323					      "vi_d7_pl5",
324					      "vi_d8_pl6",
325					      "vi_d9_pl7",
326					      "vi_d10_pt2",
327					      "vi_d11_pt3",
328					      "vi_hsync_pd7",
329					      "vi_pclk_pt0",
330					      "vi_vsync_pd6";
331				nvidia,function = "vi";
332				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333				nvidia,tristate = <TEGRA_PIN_DISABLE>;
334				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
335			};
336			/* Multiplexed and therefore disabled */
337			kb-col2-pq2 {
338				nvidia,pins = "kb_col2_pq2",
339					      "kb_col3_pq3",
340					      "kb_col4_pq4",
341					      "kb_row4_pr4";
342				nvidia,function = "rsvd4";
343				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
344				nvidia,tristate = <TEGRA_PIN_ENABLE>;
345				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
346			};
347			kb-row0-pr0 {
348				nvidia,pins = "kb_row0_pr0",
349					      "kb_row1_pr1",
350					      "kb_row2_pr2",
351					      "kb_row3_pr3";
352				nvidia,function = "rsvd3";
353				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356			};
357			kb-row5-pr5 {
358				nvidia,pins = "kb_row5_pr5",
359					      "kb_row6_pr6",
360					      "kb_row7_pr7";
361				nvidia,function = "kbc";
362				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
363				nvidia,tristate = <TEGRA_PIN_ENABLE>;
364				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
365			};
366			/*
367			 * VI level-shifter direction
368			 * (pull-down => default direction input)
369			 */
370			vi-mclk-pt1 {
371				nvidia,pins = "vi_mclk_pt1";
372				nvidia,function = "vi_alt3";
373				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
374				nvidia,tristate = <TEGRA_PIN_ENABLE>;
375				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
376			};
377
378			/* Apalis PWM1 */
379			pu6 {
380				nvidia,pins = "pu6";
381				nvidia,function = "pwm3";
382				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
383				nvidia,tristate = <TEGRA_PIN_DISABLE>;
384			};
385
386			/* Apalis PWM2 */
387			pu5 {
388				nvidia,pins = "pu5";
389				nvidia,function = "pwm2";
390				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391				nvidia,tristate = <TEGRA_PIN_DISABLE>;
392			};
393
394			/* Apalis PWM3 */
395			pu4 {
396				nvidia,pins = "pu4";
397				nvidia,function = "pwm1";
398				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399				nvidia,tristate = <TEGRA_PIN_DISABLE>;
400			};
401
402			/* Apalis PWM4 */
403			pu3 {
404				nvidia,pins = "pu3";
405				nvidia,function = "pwm0";
406				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407				nvidia,tristate = <TEGRA_PIN_DISABLE>;
408			};
409
410			/* Apalis RESET_MOCI# */
411			gmi-rst-n-pi4 {
412				nvidia,pins = "gmi_rst_n_pi4";
413				nvidia,function = "gmi";
414				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415				nvidia,tristate = <TEGRA_PIN_DISABLE>;
416			};
417
418			/* Apalis SATA1_ACT# */
419			pex-l0-prsnt-n-pdd0 {
420				nvidia,pins = "pex_l0_prsnt_n_pdd0";
421				nvidia,function = "rsvd3";
422				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423				nvidia,tristate = <TEGRA_PIN_DISABLE>;
424				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425			};
426
427			/* Apalis SD1 */
428			sdmmc1-clk-pz0 {
429				nvidia,pins = "sdmmc1_clk_pz0";
430				nvidia,function = "sdmmc1";
431				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
432				nvidia,tristate = <TEGRA_PIN_DISABLE>;
433			};
434			sdmmc1-cmd-pz1 {
435				nvidia,pins = "sdmmc1_cmd_pz1",
436					      "sdmmc1_dat0_py7",
437					      "sdmmc1_dat1_py6",
438					      "sdmmc1_dat2_py5",
439					      "sdmmc1_dat3_py4";
440				nvidia,function = "sdmmc1";
441				nvidia,pull = <TEGRA_PIN_PULL_UP>;
442				nvidia,tristate = <TEGRA_PIN_DISABLE>;
443			};
444			/* Apalis SD1_CD# */
445			clk2-req-pcc5 {
446				nvidia,pins = "clk2_req_pcc5";
447				nvidia,function = "rsvd2";
448				nvidia,pull = <TEGRA_PIN_PULL_UP>;
449				nvidia,tristate = <TEGRA_PIN_DISABLE>;
450				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451			};
452
453			/* Apalis SPDIF1 */
454			spdif-out-pk5 {
455				nvidia,pins = "spdif_out_pk5",
456					      "spdif_in_pk6";
457				nvidia,function = "spdif";
458				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459				nvidia,tristate = <TEGRA_PIN_DISABLE>;
460				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
461			};
462
463			/* Apalis SPI1 */
464			spi1-sck-px5 {
465				nvidia,pins = "spi1_sck_px5",
466					      "spi1_mosi_px4",
467					      "spi1_miso_px7",
468					      "spi1_cs0_n_px6";
469				nvidia,function = "spi1";
470				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
471				nvidia,tristate = <TEGRA_PIN_DISABLE>;
472			};
473
474			/* Apalis SPI2 */
475			lcd-sck-pz4 {
476				nvidia,pins = "lcd_sck_pz4",
477					      "lcd_sdout_pn5",
478					      "lcd_sdin_pz2",
479					      "lcd_cs0_n_pn4";
480				nvidia,function = "spi5";
481				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482				nvidia,tristate = <TEGRA_PIN_DISABLE>;
483			};
484
485			/*
486			 * Apalis TS (Low-speed type specific)
487			 * pins may be used as GPIOs
488			 */
489			kb-col5-pq5 {
490				nvidia,pins = "kb_col5_pq5";
491				nvidia,function = "rsvd4";
492				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
493				nvidia,tristate = <TEGRA_PIN_DISABLE>;
494				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495			};
496			kb-col6-pq6 {
497				nvidia,pins = "kb_col6_pq6",
498					      "kb_col7_pq7",
499					      "kb_row8_ps0",
500					      "kb_row9_ps1";
501				nvidia,function = "kbc";
502				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503				nvidia,tristate = <TEGRA_PIN_DISABLE>;
504				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505			};
506
507			/* Apalis UART1 */
508			ulpi-data0 {
509				nvidia,pins = "ulpi_data0_po1",
510					      "ulpi_data1_po2",
511					      "ulpi_data2_po3",
512					      "ulpi_data3_po4",
513					      "ulpi_data4_po5",
514					      "ulpi_data5_po6",
515					      "ulpi_data6_po7",
516					      "ulpi_data7_po0";
517				nvidia,function = "uarta";
518				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
519				nvidia,tristate = <TEGRA_PIN_DISABLE>;
520			};
521
522			/* Apalis UART2 */
523			ulpi-clk-py0 {
524				nvidia,pins = "ulpi_clk_py0",
525					      "ulpi_dir_py1",
526					      "ulpi_nxt_py2",
527					      "ulpi_stp_py3";
528				nvidia,function = "uartd";
529				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
530				nvidia,tristate = <TEGRA_PIN_DISABLE>;
531			};
532
533			/* Apalis UART3 */
534			uart2-rxd-pc3 {
535				nvidia,pins = "uart2_rxd_pc3",
536					      "uart2_txd_pc2";
537				nvidia,function = "uartb";
538				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
539				nvidia,tristate = <TEGRA_PIN_DISABLE>;
540			};
541
542			/* Apalis UART4 */
543			uart3-rxd-pw7 {
544				nvidia,pins = "uart3_rxd_pw7",
545					      "uart3_txd_pw6";
546				nvidia,function = "uartc";
547				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548				nvidia,tristate = <TEGRA_PIN_DISABLE>;
549			};
550
551			/* Apalis USBH_EN */
552			pex-l0-rst-n-pdd1 {
553				nvidia,pins = "pex_l0_rst_n_pdd1";
554				nvidia,function = "rsvd3";
555				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556				nvidia,tristate = <TEGRA_PIN_DISABLE>;
557				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
558			};
559
560			/* Apalis USBH_OC# */
561			pex-l0-clkreq-n-pdd2 {
562				nvidia,pins = "pex_l0_clkreq_n_pdd2";
563				nvidia,function = "rsvd3";
564				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565				nvidia,tristate = <TEGRA_PIN_DISABLE>;
566				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567			};
568
569			/* Apalis USBO1_EN */
570			gen2-i2c-scl-pt5 {
571				nvidia,pins = "gen2_i2c_scl_pt5";
572				nvidia,function = "rsvd4";
573				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
574				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575				nvidia,tristate = <TEGRA_PIN_DISABLE>;
576			};
577
578			/* Apalis USBO1_OC# */
579			gen2-i2c-sda-pt6 {
580				nvidia,pins = "gen2_i2c_sda_pt6";
581				nvidia,function = "rsvd4";
582				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
583				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584				nvidia,tristate = <TEGRA_PIN_DISABLE>;
585				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586			};
587
588			/* Apalis VGA1 not supported and therefore disabled */
589			crt-hsync-pv6 {
590				nvidia,pins = "crt_hsync_pv6",
591					      "crt_vsync_pv7";
592				nvidia,function = "rsvd2";
593				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
594				nvidia,tristate = <TEGRA_PIN_ENABLE>;
595				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
596			};
597
598			/* Apalis WAKE1_MICO */
599			pv1 {
600				nvidia,pins = "pv1";
601				nvidia,function = "rsvd1";
602				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
603				nvidia,tristate = <TEGRA_PIN_DISABLE>;
604				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
605			};
606
607			/* eMMC (On-module) */
608			sdmmc4-clk-pcc4 {
609				nvidia,pins = "sdmmc4_clk_pcc4",
610					      "sdmmc4_cmd_pt7",
611					      "sdmmc4_rst_n_pcc3";
612				nvidia,function = "sdmmc4";
613				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
614				nvidia,tristate = <TEGRA_PIN_DISABLE>;
615				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
616			};
617			sdmmc4-dat0-paa0 {
618				nvidia,pins = "sdmmc4_dat0_paa0",
619					      "sdmmc4_dat1_paa1",
620					      "sdmmc4_dat2_paa2",
621					      "sdmmc4_dat3_paa3",
622					      "sdmmc4_dat4_paa4",
623					      "sdmmc4_dat5_paa5",
624					      "sdmmc4_dat6_paa6",
625					      "sdmmc4_dat7_paa7";
626				nvidia,function = "sdmmc4";
627				nvidia,pull = <TEGRA_PIN_PULL_UP>;
628				nvidia,tristate = <TEGRA_PIN_DISABLE>;
629				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630			};
631
632			/* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
633			pex-l2-prsnt-n-pdd7 {
634				nvidia,pins = "pex_l2_prsnt_n_pdd7",
635					      "pex_l2_rst_n_pcc6";
636				nvidia,function = "pcie";
637				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638				nvidia,tristate = <TEGRA_PIN_DISABLE>;
639				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640			};
641			/* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
642			pex-wake-n-pdd3 {
643				nvidia,pins = "pex_wake_n_pdd3",
644					      "pex_l2_clkreq_n_pcc7";
645				nvidia,function = "pcie";
646				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647				nvidia,tristate = <TEGRA_PIN_DISABLE>;
648				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
649			};
650			/* LAN i210/i211 SMB_ALERT_N (On-module) */
651			sys-clk-req-pz5 {
652				nvidia,pins = "sys_clk_req_pz5";
653				nvidia,function = "rsvd2";
654				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655				nvidia,tristate = <TEGRA_PIN_DISABLE>;
656				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
657			};
658
659			/* LVDS Transceiver Configuration */
660			pbb0 {
661				nvidia,pins = "pbb0",
662					      "pbb7",
663					      "pcc1",
664					      "pcc2";
665				nvidia,function = "rsvd2";
666				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
667				nvidia,tristate = <TEGRA_PIN_DISABLE>;
668				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
669			};
670			pbb3 {
671				nvidia,pins = "pbb3",
672					      "pbb4",
673					      "pbb5",
674					      "pbb6";
675				nvidia,function = "displayb";
676				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677				nvidia,tristate = <TEGRA_PIN_DISABLE>;
678				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679			};
680
681			/* Not connected and therefore disabled */
682			clk-32k-out-pa0 {
683				nvidia,pins = "clk3_out_pee0",
684					      "clk3_req_pee1",
685					      "clk_32k_out_pa0",
686					      "dap4_din_pp5",
687					      "dap4_dout_pp6",
688					      "dap4_fs_pp4",
689					      "dap4_sclk_pp7";
690				nvidia,function = "rsvd2";
691				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
692				nvidia,tristate = <TEGRA_PIN_ENABLE>;
693				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694			};
695			dap2-fs-pa2 {
696				nvidia,pins = "dap2_fs_pa2",
697					      "dap2_sclk_pa3",
698					      "dap2_din_pa4",
699					      "dap2_dout_pa5",
700					      "lcd_dc0_pn6",
701					      "lcd_m1_pw1",
702					      "lcd_pwr1_pc1",
703					      "pex_l1_clkreq_n_pdd6",
704					      "pex_l1_prsnt_n_pdd4",
705					      "pex_l1_rst_n_pdd5";
706				nvidia,function = "rsvd3";
707				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
708				nvidia,tristate = <TEGRA_PIN_ENABLE>;
709				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710			};
711			gmi-ad0-pg0 {
712				nvidia,pins = "gmi_ad0_pg0",
713					      "gmi_ad2_pg2",
714					      "gmi_ad3_pg3",
715					      "gmi_ad4_pg4",
716					      "gmi_ad5_pg5",
717					      "gmi_ad6_pg6",
718					      "gmi_ad7_pg7",
719					      "gmi_ad8_ph0",
720					      "gmi_ad9_ph1",
721					      "gmi_ad10_ph2",
722					      "gmi_ad11_ph3",
723					      "gmi_ad12_ph4",
724					      "gmi_ad13_ph5",
725					      "gmi_ad14_ph6",
726					      "gmi_ad15_ph7",
727					      "gmi_adv_n_pk0",
728					      "gmi_clk_pk1",
729					      "gmi_cs4_n_pk2",
730					      "gmi_cs2_n_pk3",
731					      "gmi_dqs_pi2",
732					      "gmi_iordy_pi5",
733					      "gmi_oe_n_pi1",
734					      "gmi_wait_pi7",
735					      "gmi_wr_n_pi0",
736					      "lcd_cs1_n_pw0",
737					      "pu0",
738					      "pu1",
739					      "pu2";
740				nvidia,function = "rsvd4";
741				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
742				nvidia,tristate = <TEGRA_PIN_ENABLE>;
743				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
744			};
745			gmi-cs0-n-pj0 {
746				nvidia,pins = "gmi_cs0_n_pj0",
747					      "gmi_cs1_n_pj2",
748					      "gmi_cs3_n_pk4";
749				nvidia,function = "rsvd1";
750				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
751				nvidia,tristate = <TEGRA_PIN_ENABLE>;
752				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
753			};
754			gmi-cs6-n-pi3 {
755				nvidia,pins = "gmi_cs6_n_pi3";
756				nvidia,function = "sata";
757				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
758				nvidia,tristate = <TEGRA_PIN_ENABLE>;
759				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
760			};
761			gmi-cs7-n-pi6 {
762				nvidia,pins = "gmi_cs7_n_pi6";
763				nvidia,function = "gmi_alt";
764				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
765				nvidia,tristate = <TEGRA_PIN_ENABLE>;
766				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
767			};
768			lcd-pwr0-pb2 {
769				nvidia,pins = "lcd_pwr0_pb2",
770					      "lcd_pwr2_pc6",
771					      "lcd_wr_n_pz3";
772				nvidia,function = "hdcp";
773				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
774				nvidia,tristate = <TEGRA_PIN_ENABLE>;
775				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
776			};
777			uart2-cts-n-pj5 {
778				nvidia,pins = "uart2_cts_n_pj5",
779					      "uart2_rts_n_pj6";
780				nvidia,function = "gmi";
781				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
782				nvidia,tristate = <TEGRA_PIN_ENABLE>;
783				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
784			};
785
786			/* Power I2C (On-module) */
787			pwr-i2c-scl-pz6 {
788				nvidia,pins = "pwr_i2c_scl_pz6",
789					      "pwr_i2c_sda_pz7";
790				nvidia,function = "i2cpwr";
791				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
792				nvidia,tristate = <TEGRA_PIN_DISABLE>;
793				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
795			};
796
797			/*
798			 * THERMD_ALERT#, unlatched I2C address pin of LM95245
799			 * temperature sensor therefore requires disabling for
800			 * now
801			 */
802			lcd-dc1-pd2 {
803				nvidia,pins = "lcd_dc1_pd2";
804				nvidia,function = "rsvd3";
805				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
806				nvidia,tristate = <TEGRA_PIN_ENABLE>;
807				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
808			};
809
810			/* TOUCH_PEN_INT# (On-module) */
811			pv0 {
812				nvidia,pins = "pv0";
813				nvidia,function = "rsvd1";
814				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
815				nvidia,tristate = <TEGRA_PIN_DISABLE>;
816				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
817			};
818		};
819	};
820
821	serial@70006040 {
822		compatible = "nvidia,tegra30-hsuart";
823		reset-names = "serial";
824		/delete-property/ reg-shift;
825	};
826
827	serial@70006200 {
828		compatible = "nvidia,tegra30-hsuart";
829		reset-names = "serial";
830		/delete-property/ reg-shift;
831	};
832
833	serial@70006300 {
834		compatible = "nvidia,tegra30-hsuart";
835		reset-names = "serial";
836		/delete-property/ reg-shift;
837	};
838
839	hdmi_ddc: i2c@7000c700 {
840		clock-frequency = <10000>;
841	};
842
843	/*
844	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
845	 * touch screen controller
846	 */
847	i2c@7000d000 {
848		status = "okay";
849		clock-frequency = <100000>;
850
851		/* SGTL5000 audio codec */
852		sgtl5000: codec@a {
853			compatible = "fsl,sgtl5000";
854			reg = <0x0a>;
855			#sound-dai-cells = <0>;
856			VDDA-supply = <&reg_module_3v3_audio>;
857			VDDD-supply = <&reg_1v8_vio>;
858			VDDIO-supply = <&reg_module_3v3>;
859			clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
860		};
861
862		pmic: pmic@2d {
863			compatible = "ti,tps65911";
864			reg = <0x2d>;
865
866			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
867			#interrupt-cells = <2>;
868			interrupt-controller;
869			wakeup-source;
870
871			ti,system-power-controller;
872
873			#gpio-cells = <2>;
874			gpio-controller;
875
876			vcc1-supply = <&reg_module_3v3>;
877			vcc2-supply = <&reg_module_3v3>;
878			vcc3-supply = <&reg_1v8_vio>;
879			vcc4-supply = <&reg_module_3v3>;
880			vcc5-supply = <&reg_module_3v3>;
881			vcc6-supply = <&reg_1v8_vio>;
882			vcc7-supply = <&reg_5v0_charge_pump>;
883			vccio-supply = <&reg_module_3v3>;
884
885			regulators {
886				vdd1_reg: vdd1 {
887					regulator-name = "+V1.35_VDDIO_DDR";
888					regulator-min-microvolt = <1350000>;
889					regulator-max-microvolt = <1350000>;
890					regulator-always-on;
891				};
892
893				vdd2_reg: vdd2 {
894					regulator-name = "+V1.05";
895					regulator-min-microvolt = <1050000>;
896					regulator-max-microvolt = <1050000>;
897				};
898
899				vddctrl_reg: vddctrl {
900					regulator-name = "+V1.0_VDD_CPU";
901					regulator-min-microvolt = <1150000>;
902					regulator-max-microvolt = <1150000>;
903					regulator-always-on;
904				};
905
906				reg_1v8_vio: vio {
907					regulator-name = "+V1.8";
908					regulator-min-microvolt = <1800000>;
909					regulator-max-microvolt = <1800000>;
910					regulator-always-on;
911				};
912
913				/* LDO1: unused */
914
915				/*
916				 * EN_+V3.3 switching via FET:
917				 * +V3.3_AUDIO_AVDD_S, +V3.3
918				 * see also +V3.3 fixed supply
919				 */
920				ldo2_reg: ldo2 {
921					regulator-name = "EN_+V3.3";
922					regulator-min-microvolt = <3300000>;
923					regulator-max-microvolt = <3300000>;
924					regulator-always-on;
925				};
926
927				ldo3_reg: ldo3 {
928					regulator-name = "+V1.2_CSI";
929					regulator-min-microvolt = <1200000>;
930					regulator-max-microvolt = <1200000>;
931				};
932
933				ldo4_reg: ldo4 {
934					regulator-name = "+V1.2_VDD_RTC";
935					regulator-min-microvolt = <1200000>;
936					regulator-max-microvolt = <1200000>;
937					regulator-always-on;
938				};
939
940				/*
941				 * +V2.8_AVDD_VDAC:
942				 * only required for (unsupported) analog RGB
943				 */
944				ldo5_reg: ldo5 {
945					regulator-name = "+V2.8_AVDD_VDAC";
946					regulator-min-microvolt = <2800000>;
947					regulator-max-microvolt = <2800000>;
948					regulator-always-on;
949				};
950
951				/*
952				 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
953				 * but LDO6 can't set voltage in 50mV
954				 * granularity
955				 */
956				ldo6_reg: ldo6 {
957					regulator-name = "+V1.05_AVDD_PLLE";
958					regulator-min-microvolt = <1100000>;
959					regulator-max-microvolt = <1100000>;
960				};
961
962				ldo7_reg: ldo7 {
963					regulator-name = "+V1.2_AVDD_PLL";
964					regulator-min-microvolt = <1200000>;
965					regulator-max-microvolt = <1200000>;
966					regulator-always-on;
967				};
968
969				ldo8_reg: ldo8 {
970					regulator-name = "+V1.0_VDD_DDR_HS";
971					regulator-min-microvolt = <1000000>;
972					regulator-max-microvolt = <1000000>;
973					regulator-always-on;
974				};
975			};
976		};
977
978		/* STMPE811 touch screen controller */
979		touchscreen@41 {
980			compatible = "st,stmpe811";
981			reg = <0x41>;
982			irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
983			id = <0>;
984			blocks = <0x5>;
985			irq-trigger = <0x1>;
986			/* 3.25 MHz ADC clock speed */
987			st,adc-freq = <1>;
988			/* 12-bit ADC */
989			st,mod-12b = <1>;
990			/* internal ADC reference */
991			st,ref-sel = <0>;
992			/* ADC converstion time: 80 clocks */
993			st,sample-time = <4>;
994
995			stmpe_adc {
996				compatible = "st,stmpe-adc";
997				/* forbid to use ADC channels 3-0 (touch) */
998				st,norequest-mask = <0x0F>;
999			};
1000
1001			stmpe_touchscreen {
1002				compatible = "st,stmpe-ts";
1003				/* 8 sample average control */
1004				st,ave-ctrl = <3>;
1005				/* 7 length fractional part in z */
1006				st,fraction-z = <7>;
1007				/*
1008				 * 50 mA typical 80 mA max touchscreen drivers
1009				 * current limit value
1010				 */
1011				st,i-drive = <1>;
1012				/* 1 ms panel driver settling time */
1013				st,settling = <3>;
1014				/* 5 ms touch detect interrupt delay */
1015				st,touch-det-delay = <5>;
1016			};
1017		};
1018
1019		/*
1020		 * LM95245 temperature sensor
1021		 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1022		 */
1023		temp-sensor@4c {
1024			compatible = "national,lm95245";
1025			reg = <0x4c>;
1026		};
1027
1028		/* SW: +V1.2_VDD_CORE */
1029		regulator@60 {
1030			compatible = "ti,tps62362";
1031			reg = <0x60>;
1032
1033			regulator-name = "tps62362-vout";
1034			regulator-min-microvolt = <900000>;
1035			regulator-max-microvolt = <1400000>;
1036			regulator-boot-on;
1037			regulator-always-on;
1038		};
1039	};
1040
1041	/* SPI4: CAN2 */
1042	spi@7000da00 {
1043		status = "okay";
1044		spi-max-frequency = <10000000>;
1045
1046		can@1 {
1047			compatible = "microchip,mcp2515";
1048			reg = <1>;
1049			clocks = <&clk16m>;
1050			interrupt-parent = <&gpio>;
1051			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1052			spi-max-frequency = <10000000>;
1053		};
1054	};
1055
1056	/* SPI6: CAN1 */
1057	spi@7000de00 {
1058		status = "okay";
1059		spi-max-frequency = <10000000>;
1060
1061		can@0 {
1062			compatible = "microchip,mcp2515";
1063			reg = <0>;
1064			clocks = <&clk16m>;
1065			interrupt-parent = <&gpio>;
1066			interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1067			spi-max-frequency = <10000000>;
1068		};
1069	};
1070
1071	pmc@7000e400 {
1072		nvidia,invert-interrupt;
1073		nvidia,suspend-mode = <1>;
1074		nvidia,cpu-pwr-good-time = <5000>;
1075		nvidia,cpu-pwr-off-time = <5000>;
1076		nvidia,core-pwr-good-time = <3845 3845>;
1077		nvidia,core-pwr-off-time = <0>;
1078		nvidia,core-power-req-active-high;
1079		nvidia,sys-clock-req-active-high;
1080
1081		/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1082		i2c-thermtrip {
1083			nvidia,i2c-controller-id = <4>;
1084			nvidia,bus-addr = <0x2d>;
1085			nvidia,reg-addr = <0x3f>;
1086			nvidia,reg-data = <0x1>;
1087		};
1088	};
1089
1090	hda@70030000 {
1091		status = "okay";
1092	};
1093
1094	ahub@70080000 {
1095		i2s@70080500 {
1096			status = "okay";
1097		};
1098	};
1099
1100	/* eMMC */
1101	mmc@78000600 {
1102		status = "okay";
1103		bus-width = <8>;
1104		non-removable;
1105		vmmc-supply = <&reg_module_3v3>; /* VCC */
1106		vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
1107		mmc-ddr-1_8v;
1108	};
1109
1110	clk16m: clock-osc4 {
1111		compatible = "fixed-clock";
1112		#clock-cells = <0>;
1113		clock-frequency = <16000000>;
1114	};
1115
1116	clk32k_in: clock-xtal1 {
1117		compatible = "fixed-clock";
1118		#clock-cells = <0>;
1119		clock-frequency = <32768>;
1120	};
1121
1122	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1123		compatible = "regulator-fixed";
1124		regulator-name = "+V1.8_AVDD_HDMI_PLL";
1125		regulator-min-microvolt = <1800000>;
1126		regulator-max-microvolt = <1800000>;
1127		enable-active-high;
1128		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1129		vin-supply = <&reg_1v8_vio>;
1130	};
1131
1132	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1133		compatible = "regulator-fixed";
1134		regulator-name = "+V3.3_AVDD_HDMI";
1135		regulator-min-microvolt = <3300000>;
1136		regulator-max-microvolt = <3300000>;
1137		enable-active-high;
1138		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1139		vin-supply = <&reg_module_3v3>;
1140	};
1141
1142	reg_5v0_charge_pump: regulator-5v0-charge-pump {
1143		compatible = "regulator-fixed";
1144		regulator-name = "+V5.0";
1145		regulator-min-microvolt = <5000000>;
1146		regulator-max-microvolt = <5000000>;
1147		regulator-always-on;
1148	};
1149
1150	reg_module_3v3: regulator-module-3v3 {
1151		compatible = "regulator-fixed";
1152		regulator-name = "+V3.3";
1153		regulator-min-microvolt = <3300000>;
1154		regulator-max-microvolt = <3300000>;
1155		regulator-always-on;
1156	};
1157
1158	reg_module_3v3_audio: regulator-module-3v3-audio {
1159		compatible = "regulator-fixed";
1160		regulator-name = "+V3.3_AUDIO_AVDD_S";
1161		regulator-min-microvolt = <3300000>;
1162		regulator-max-microvolt = <3300000>;
1163		regulator-always-on;
1164	};
1165
1166	sound {
1167		compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1168			     "nvidia,tegra-audio-sgtl5000";
1169		nvidia,model = "Toradex Apalis T30";
1170		nvidia,audio-routing =
1171			"Headphone Jack", "HP_OUT",
1172			"LINE_IN", "Line In Jack",
1173			"MIC_IN", "Mic Jack";
1174		nvidia,i2s-controller = <&tegra_i2s2>;
1175		nvidia,audio-codec = <&sgtl5000>;
1176		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1177			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1178			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1179		clock-names = "pll_a", "pll_a_out0", "mclk";
1180
1181		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1182				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1183
1184		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1185					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1186	};
1187};
1188