1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5/dts-v1/;
6#include "nuvoton-npcm750.dtsi"
7#include "dt-bindings/gpio/gpio.h"
8#include "nuvoton-npcm750-pincfg-evb.dtsi"
9
10/ {
11	model = "Nuvoton npcm750 Development Board (Device Tree)";
12	compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
13
14	aliases {
15		ethernet2 = &gmac0;
16		ethernet3 = &gmac1;
17		serial0 = &serial0;
18		serial1 = &serial1;
19		serial2 = &serial2;
20		serial3 = &serial3;
21		i2c0 = &i2c0;
22		i2c1 = &i2c1;
23		i2c2 = &i2c2;
24		i2c3 = &i2c3;
25		i2c4 = &i2c4;
26		i2c5 = &i2c5;
27		i2c6 = &i2c6;
28		i2c7 = &i2c7;
29		i2c8 = &i2c8;
30		i2c9 = &i2c9;
31		i2c10 = &i2c10;
32		i2c11 = &i2c11;
33		i2c12 = &i2c12;
34		i2c13 = &i2c13;
35		i2c14 = &i2c14;
36		i2c15 = &i2c15;
37		spi0 = &spi0;
38		spi1 = &spi1;
39		fiu0 = &fiu0;
40		fiu1 = &fiu3;
41		fiu2 = &fiux;
42	};
43
44	chosen {
45		stdout-path = &serial3;
46		bootargs = "console=ttyS0,115200";
47	};
48
49	memory {
50		device_type = "memory";
51		reg = <0x0 0x20000000>;
52	};
53};
54
55&gmac0 {
56	phy-mode = "rgmii-id";
57	status = "okay";
58};
59
60&gmac1 {
61	phy-mode = "rgmii-id";
62	status = "okay";
63};
64
65&ehci1 {
66	status = "okay";
67};
68
69&fiu0 {
70	status = "okay";
71	flash@0 {
72		compatible = "jedec,spi-nor";
73		#address-cells = <1>;
74		#size-cells = <1>;
75		spi-rx-bus-width = <2>;
76		reg = <0>;
77		spi-max-frequency = <5000000>;
78		partitions {
79			compatible = "fixed-partitions";
80			#address-cells = <1>;
81			#size-cells = <1>;
82			bbuboot1@0 {
83				label = "bb-uboot-1";
84				reg = <0x0000000 0x80000>;
85				read-only;
86				};
87			bbuboot2@80000 {
88				label = "bb-uboot-2";
89				reg = <0x0080000 0x80000>;
90				read-only;
91				};
92			envparam@100000 {
93				label = "env-param";
94				reg = <0x0100000 0x40000>;
95				read-only;
96				};
97			spare@140000 {
98				label = "spare";
99				reg = <0x0140000 0xC0000>;
100				};
101			kernel@200000 {
102				label = "kernel";
103				reg = <0x0200000 0x400000>;
104				};
105			rootfs@600000 {
106				label = "rootfs";
107				reg = <0x0600000 0x700000>;
108				};
109			spare1@d00000 {
110				label = "spare1";
111				reg = <0x0D00000 0x200000>;
112				};
113			spare2@f00000 {
114				label = "spare2";
115				reg = <0x0F00000 0x200000>;
116				};
117			spare3@1100000 {
118				label = "spare3";
119				reg = <0x1100000 0x200000>;
120				};
121			spare4@1300000 {
122				label = "spare4";
123				reg = <0x1300000 0x0>;
124			};
125		};
126	};
127};
128
129&fiu3 {
130	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
131	status = "okay";
132	flash@0 {
133		compatible = "jedec,spi-nor";
134		#address-cells = <1>;
135		#size-cells = <1>;
136		spi-rx-bus-width = <2>;
137		reg = <0>;
138		spi-max-frequency = <5000000>;
139		partitions {
140			compatible = "fixed-partitions";
141			#address-cells = <1>;
142			#size-cells = <1>;
143			system1@0 {
144				label = "spi3-system1";
145				reg = <0x0 0x0>;
146			};
147		};
148	};
149};
150
151&fiux {
152	spix-mode;
153};
154
155&watchdog1 {
156	status = "okay";
157};
158
159&rng {
160	status = "okay";
161};
162
163&serial0 {
164	status = "okay";
165};
166
167&serial1 {
168	status = "okay";
169};
170
171&serial2 {
172	status = "okay";
173};
174
175&serial3 {
176	status = "okay";
177};
178
179&adc {
180	status = "okay";
181};
182
183&lpc_kcs {
184	kcs1: kcs1@0 {
185		status = "okay";
186	};
187
188	kcs2: kcs2@0 {
189		status = "okay";
190	};
191
192	kcs3: kcs3@0 {
193		status = "okay";
194	};
195};
196
197/* lm75 on SVB */
198&i2c0 {
199	clock-frequency = <100000>;
200	status = "okay";
201	lm75@48 {
202		compatible = "lm75";
203		reg = <0x48>;
204		status = "okay";
205	};
206};
207
208/* lm75 on EB */
209&i2c1 {
210	clock-frequency = <100000>;
211	status = "okay";
212	lm75@48 {
213		compatible = "lm75";
214		reg = <0x48>;
215		status = "okay";
216	};
217};
218
219/* tmp100 on EB */
220&i2c2 {
221	clock-frequency = <100000>;
222	status = "okay";
223	tmp100@48 {
224		compatible = "tmp100";
225		reg = <0x48>;
226		status = "okay";
227	};
228};
229
230&i2c3 {
231	clock-frequency = <100000>;
232	status = "okay";
233};
234
235&i2c5 {
236	clock-frequency = <100000>;
237	status = "okay";
238};
239
240/* tmp100 on SVB */
241&i2c6 {
242	clock-frequency = <100000>;
243	status = "okay";
244	tmp100@48 {
245		compatible = "tmp100";
246		reg = <0x48>;
247		status = "okay";
248	};
249};
250
251&i2c7 {
252	clock-frequency = <100000>;
253	status = "okay";
254};
255
256&i2c8 {
257	clock-frequency = <100000>;
258	status = "okay";
259};
260
261&i2c9 {
262	clock-frequency = <100000>;
263	status = "okay";
264};
265
266&i2c10 {
267	clock-frequency = <100000>;
268	status = "okay";
269};
270
271&i2c11 {
272	clock-frequency = <100000>;
273	status = "okay";
274};
275
276&i2c14 {
277	clock-frequency = <100000>;
278	status = "okay";
279};
280
281&pwm_fan {
282	status = "okay";
283	fan@0 {
284		reg = <0x00>;
285		fan-tach-ch = /bits/ 8 <0x00 0x01>;
286		cooling-levels = <127 255>;
287	};
288	fan@1 {
289		reg = <0x01>;
290		fan-tach-ch = /bits/ 8 <0x02 0x03>;
291		cooling-levels = /bits/ 8 <127 255>;
292	};
293	fan@2 {
294		reg = <0x02>;
295		fan-tach-ch = /bits/ 8 <0x04 0x05>;
296		cooling-levels = /bits/ 8 <127 255>;
297	};
298	fan@3 {
299		reg = <0x03>;
300		fan-tach-ch = /bits/ 8 <0x06 0x07>;
301		cooling-levels = /bits/ 8 <127 255>;
302	};
303	fan@4 {
304		reg = <0x04>;
305		fan-tach-ch = /bits/ 8 <0x08 0x09>;
306		cooling-levels = /bits/ 8 <127 255>;
307	};
308	fan@5 {
309		reg = <0x05>;
310		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
311		cooling-levels = /bits/ 8 <127 255>;
312	};
313	fan@6 {
314		reg = <0x06>;
315		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
316		cooling-levels = /bits/ 8 <127 255>;
317	};
318	fan@7 {
319		reg = <0x07>;
320		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
321		cooling-levels = /bits/ 8 <127 255>;
322	};
323};
324
325&spi0 {
326	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
327	status = "okay";
328	flash@0 {
329		compatible = "winbond,w25q128",
330		"jedec,spi-nor";
331		reg = <0x0>;
332		#address-cells = <1>;
333		#size-cells = <1>;
334		spi-max-frequency = <5000000>;
335		partition@0 {
336			label = "spi0_spare1";
337			reg = <0x0000000 0x800000>;
338		};
339		partition@1 {
340			label = "spi0_spare2";
341			reg = <0x800000 0x0>;
342		};
343	};
344};
345
346&spi1 {
347	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
348	status = "okay";
349	flash@0 {
350		compatible = "winbond,w25q128fw",
351		"jedec,spi-nor";
352		reg = <0x0>;
353		#address-cells = <1>;
354		#size-cells = <1>;
355		spi-max-frequency = <5000000>;
356		partition@0 {
357			label = "spi1_spare1";
358			reg = <0x0000000 0x800000>;
359		};
360		partition@1 {
361			label = "spi1_spare2";
362			reg = <0x800000 0x0>;
363		};
364	};
365};
366
367&pinctrl {
368	pinctrl-names = "default";
369	pinctrl-0 = <	&iox1_pins
370			&pin8_input
371			&pin9_output_high
372			&pin10_input
373			&pin11_output_high
374			&pin16_input
375			&pin24_output_high
376			&pin25_output_low
377			&pin32_output_high
378			&jtag2_pins
379			&pin61_output_high
380			&pin62_output_high
381			&pin63_output_high
382			&lpc_pins
383			&pin160_input
384			&pin162_input
385			&pin168_input
386			&pin169_input
387			&pin170_input
388			&pin187_output_high
389			&pin190_input
390			&pin191_output_high
391			&pin192_output_high
392			&pin197_output_low
393			&ddc_pins
394			&pin218_input
395			&pin219_output_low
396			&pin220_output_low
397			&pin221_output_high
398			&pin222_input
399			&pin223_output_low
400			&spix_pins
401			&pin228_output_low
402			&pin231_output_high
403			&pin255_input>;
404};
405
406