1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/boot/nspire.dtsi 4 * 5 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> 6 */ 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&intc>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "arm,arm926ej-s"; 19 device_type = "cpu"; 20 reg = <0>; 21 }; 22 }; 23 24 bootrom: bootrom@0 { 25 reg = <0x00000000 0x80000>; 26 }; 27 28 sram: sram@a4000000 { 29 device = "memory"; 30 reg = <0xa4000000 0x20000>; 31 }; 32 33 timer_clk: timer_clk { 34 #clock-cells = <0>; 35 compatible = "fixed-clock"; 36 clock-frequency = <32768>; 37 }; 38 39 base_clk: base_clk { 40 #clock-cells = <0>; 41 reg = <0x900b0024 0x4>; 42 }; 43 44 ahb_clk: ahb_clk { 45 #clock-cells = <0>; 46 reg = <0x900b0024 0x4>; 47 clocks = <&base_clk>; 48 }; 49 50 apb_pclk: apb_pclk { 51 #clock-cells = <0>; 52 compatible = "fixed-factor-clock"; 53 clock-div = <2>; 54 clock-mult = <1>; 55 clocks = <&ahb_clk>; 56 }; 57 58 usb_phy: usb_phy { 59 compatible = "usb-nop-xceiv"; 60 #phy-cells = <0>; 61 }; 62 63 vbus_reg: vbus_reg { 64 compatible = "regulator-fixed"; 65 66 regulator-name = "USB VBUS output"; 67 regulator-type = "voltage"; 68 69 regulator-min-microvolt = <5000000>; 70 regulator-max-microvolt = <5000000>; 71 }; 72 73 ahb { 74 compatible = "simple-bus"; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges; 78 79 spi: spi@a9000000 { 80 reg = <0xa9000000 0x1000>; 81 }; 82 83 usb0: usb@b0000000 { 84 compatible = "lsi,zevio-usb"; 85 reg = <0xb0000000 0x1000>; 86 interrupts = <8>; 87 88 usb-phy = <&usb_phy>; 89 vbus-supply = <&vbus_reg>; 90 }; 91 92 usb1: usb@b4000000 { 93 reg = <0xb4000000 0x1000>; 94 interrupts = <9>; 95 status = "disabled"; 96 }; 97 98 lcd: lcd@c0000000 { 99 compatible = "arm,pl111", "arm,primecell"; 100 reg = <0xc0000000 0x1000>; 101 interrupts = <21>; 102 103 /* 104 * We assume the same clock is fed to APB and CLCDCLK. 105 * There is some code to scale the clock down by a factor 106 * 48 for the display so likely the frequency to the 107 * display is 1MHz and the CLCDCLK is 48 MHz. 108 */ 109 clocks = <&apb_pclk>, <&apb_pclk>; 110 clock-names = "clcdclk", "apb_pclk"; 111 }; 112 113 adc: adc@c4000000 { 114 reg = <0xc4000000 0x1000>; 115 interrupts = <11>; 116 }; 117 118 tdes: crypto@c8010000 { 119 reg = <0xc8010000 0x1000>; 120 }; 121 122 sha256: crypto@cc000000 { 123 reg = <0xcc000000 0x1000>; 124 }; 125 126 apb@90000000 { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 clock-ranges; 131 ranges; 132 133 gpio: gpio@90000000 { 134 compatible = "lsi,zevio-gpio"; 135 reg = <0x90000000 0x1000>; 136 interrupts = <7>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 }; 140 141 fast_timer: timer@90010000 { 142 reg = <0x90010000 0x1000>; 143 interrupts = <17>; 144 }; 145 146 uart: serial@90020000 { 147 reg = <0x90020000 0x1000>; 148 interrupts = <1>; 149 }; 150 151 timer0: timer@900c0000 { 152 reg = <0x900c0000 0x1000>; 153 clocks = <&timer_clk>, <&timer_clk>, 154 <&timer_clk>; 155 clock-names = "timer0clk", "timer1clk", 156 "apb_pclk"; 157 }; 158 159 timer1: timer@900d0000 { 160 reg = <0x900d0000 0x1000>; 161 interrupts = <19>; 162 clocks = <&timer_clk>, <&timer_clk>, 163 <&timer_clk>; 164 clock-names = "timer0clk", "timer1clk", 165 "apb_pclk"; 166 }; 167 168 watchdog: watchdog@90060000 { 169 compatible = "arm,amba-primecell"; 170 reg = <0x90060000 0x1000>; 171 interrupts = <3>; 172 }; 173 174 rtc: rtc@90090000 { 175 reg = <0x90090000 0x1000>; 176 interrupts = <4>; 177 }; 178 179 misc: misc@900a0000 { 180 compatible = "ti,nspire-misc", "syscon", "simple-mfd"; 181 reg = <0x900a0000 0x1000>; 182 183 reboot { 184 compatible = "syscon-reboot"; 185 offset = <0x08>; 186 value = <0x02>; 187 }; 188 }; 189 190 pwr: pwr@900b0000 { 191 reg = <0x900b0000 0x1000>; 192 interrupts = <15>; 193 }; 194 195 keypad: input@900e0000 { 196 compatible = "ti,nspire-keypad"; 197 reg = <0x900e0000 0x1000>; 198 interrupts = <16>; 199 200 scan-interval = <1000>; 201 row-delay = <200>; 202 203 clocks = <&apb_pclk>; 204 }; 205 206 contrast: contrast@900f0000 { 207 reg = <0x900f0000 0x1000>; 208 }; 209 210 led: led@90110000 { 211 reg = <0x90110000 0x1000>; 212 }; 213 }; 214 }; 215}; 216