1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
8 */
9
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/clock/at91.h>
15#include <dt-bindings/mfd/at91-usart.h>
16#include <dt-bindings/mfd/atmel-flexcom.h>
17
18/ {
19	#address-cells = <1>;
20	#size-cells = <1>;
21	model = "Microchip SAM9X60 SoC";
22	compatible = "microchip,sam9x60";
23	interrupt-parent = <&aic>;
24
25	aliases {
26		serial0 = &dbgu;
27		gpio0 = &pioA;
28		gpio1 = &pioB;
29		gpio2 = &pioC;
30		gpio3 = &pioD;
31		tcb0 = &tcb0;
32		tcb1 = &tcb1;
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		cpu@0 {
40			compatible = "arm,arm926ej-s";
41			device_type = "cpu";
42			reg = <0>;
43		};
44	};
45
46	memory@20000000 {
47		device_type = "memory";
48		reg = <0x20000000 0x10000000>;
49	};
50
51	clocks {
52		slow_xtal: slow_xtal {
53			compatible = "fixed-clock";
54			#clock-cells = <0>;
55		};
56
57		main_xtal: main_xtal {
58			compatible = "fixed-clock";
59			#clock-cells = <0>;
60		};
61	};
62
63	sram: sram@300000 {
64		compatible = "mmio-sram";
65		reg = <0x00300000 0x100000>;
66		#address-cells = <1>;
67		#size-cells = <1>;
68		ranges = <0 0x00300000 0x100000>;
69	};
70
71	ahb {
72		compatible = "simple-bus";
73		#address-cells = <1>;
74		#size-cells = <1>;
75		ranges;
76
77		usb0: gadget@500000 {
78			#address-cells = <1>;
79			#size-cells = <0>;
80			compatible = "microchip,sam9x60-udc";
81			reg = <0x00500000 0x100000
82				0xf803c000 0x400>;
83			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
84			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
85			clock-names = "pclk", "hclk";
86			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87			assigned-clock-rates = <480000000>;
88			status = "disabled";
89		};
90
91		usb1: ohci@600000 {
92			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93			reg = <0x00600000 0x100000>;
94			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
95			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
96			clock-names = "ohci_clk", "hclk", "uhpck";
97			status = "disabled";
98		};
99
100		usb2: ehci@700000 {
101			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102			reg = <0x00700000 0x100000>;
103			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
104			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
105			clock-names = "usb_clk", "ehci_clk";
106			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107			assigned-clock-rates = <480000000>;
108			status = "disabled";
109		};
110
111		ebi: ebi@10000000 {
112			compatible = "microchip,sam9x60-ebi";
113			#address-cells = <2>;
114			#size-cells = <1>;
115			atmel,smc = <&smc>;
116			microchip,sfr = <&sfr>;
117			reg = <0x10000000 0x60000000>;
118			ranges = <0x0 0x0 0x10000000 0x10000000
119				  0x1 0x0 0x20000000 0x10000000
120				  0x2 0x0 0x30000000 0x10000000
121				  0x3 0x0 0x40000000 0x10000000
122				  0x4 0x0 0x50000000 0x10000000
123				  0x5 0x0 0x60000000 0x10000000>;
124			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
125			status = "disabled";
126
127			nand_controller: nand-controller {
128				compatible = "microchip,sam9x60-nand-controller";
129				ecc-engine = <&pmecc>;
130				#address-cells = <2>;
131				#size-cells = <1>;
132				ranges;
133				status = "disabled";
134			};
135		};
136
137		sdmmc0: sdio-host@80000000 {
138			compatible = "microchip,sam9x60-sdhci";
139			reg = <0x80000000 0x300>;
140			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
141			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
142			clock-names = "hclock", "multclk";
143			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144			assigned-clock-rates = <100000000>;
145			status = "disabled";
146		};
147
148		sdmmc1: sdio-host@90000000 {
149			compatible = "microchip,sam9x60-sdhci";
150			reg = <0x90000000 0x300>;
151			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
152			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
153			clock-names = "hclock", "multclk";
154			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155			assigned-clock-rates = <100000000>;
156			status = "disabled";
157		};
158
159		apb {
160			compatible = "simple-bus";
161			#address-cells = <1>;
162			#size-cells = <1>;
163			ranges;
164
165			flx4: flexcom@f0000000 {
166				compatible = "atmel,sama5d2-flexcom";
167				reg = <0xf0000000 0x200>;
168				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
169				#address-cells = <1>;
170				#size-cells = <1>;
171				ranges = <0x0 0xf0000000 0x800>;
172				status = "disabled";
173
174				uart4: serial@200 {
175					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
176					reg = <0x200 0x200>;
177					interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
178					dmas = <&dma0
179						(AT91_XDMAC_DT_MEM_IF(0) |
180						 AT91_XDMAC_DT_PER_IF(1) |
181						 AT91_XDMAC_DT_PERID(8))>,
182						<&dma0
183						(AT91_XDMAC_DT_MEM_IF(0) |
184						 AT91_XDMAC_DT_PER_IF(1) |
185						 AT91_XDMAC_DT_PERID(9))>;
186					dma-names = "tx", "rx";
187					clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
188					clock-names = "usart";
189					atmel,use-dma-rx;
190					atmel,use-dma-tx;
191					atmel,fifo-size = <16>;
192					status = "disabled";
193				};
194
195				spi4: spi@400 {
196					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
197					reg = <0x400 0x200>;
198					interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
199					clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
200					clock-names = "spi_clk";
201					dmas = <&dma0
202						(AT91_XDMAC_DT_MEM_IF(0) |
203						 AT91_XDMAC_DT_PER_IF(1) |
204						 AT91_XDMAC_DT_PERID(8))>,
205						<&dma0
206						(AT91_XDMAC_DT_MEM_IF(0) |
207						 AT91_XDMAC_DT_PER_IF(1) |
208						 AT91_XDMAC_DT_PERID(9))>;
209					dma-names = "tx", "rx";
210					atmel,fifo-size = <16>;
211					status = "disabled";
212				};
213
214				i2c4: i2c@600 {
215					compatible = "microchip,sam9x60-i2c";
216					reg = <0x600 0x200>;
217					interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
218					clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
219					dmas = <&dma0
220						(AT91_XDMAC_DT_MEM_IF(0) |
221						 AT91_XDMAC_DT_PER_IF(1) |
222						 AT91_XDMAC_DT_PERID(8))>,
223						<&dma0
224						(AT91_XDMAC_DT_MEM_IF(0) |
225						 AT91_XDMAC_DT_PER_IF(1) |
226						 AT91_XDMAC_DT_PERID(9))>;
227					dma-names = "tx", "rx";
228					atmel,fifo-size = <16>;
229					status = "disabled";
230				};
231			};
232
233			flx5: flexcom@f0004000 {
234				compatible = "atmel,sama5d2-flexcom";
235				reg = <0xf0004000 0x200>;
236				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
237				#address-cells = <1>;
238				#size-cells = <1>;
239				ranges = <0x0 0xf0004000 0x800>;
240				status = "disabled";
241
242				uart5: serial@200 {
243					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
244					reg = <0x200 0x200>;
245					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
246					interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
247					dmas = <&dma0
248						(AT91_XDMAC_DT_MEM_IF(0) |
249						 AT91_XDMAC_DT_PER_IF(1) |
250						 AT91_XDMAC_DT_PERID(10))>,
251						<&dma0
252						(AT91_XDMAC_DT_MEM_IF(0) |
253						 AT91_XDMAC_DT_PER_IF(1) |
254						 AT91_XDMAC_DT_PERID(11))>;
255					dma-names = "tx", "rx";
256					clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
257					clock-names = "usart";
258					atmel,use-dma-rx;
259					atmel,use-dma-tx;
260					atmel,fifo-size = <16>;
261					status = "disabled";
262				};
263
264				spi5: spi@400 {
265					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
266					reg = <0x400 0x200>;
267					interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
268					clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
269					clock-names = "spi_clk";
270					dmas = <&dma0
271						(AT91_XDMAC_DT_MEM_IF(0) |
272						 AT91_XDMAC_DT_PER_IF(1) |
273						 AT91_XDMAC_DT_PERID(10))>,
274						<&dma0
275						(AT91_XDMAC_DT_MEM_IF(0) |
276						 AT91_XDMAC_DT_PER_IF(1) |
277						 AT91_XDMAC_DT_PERID(11))>;
278					dma-names = "tx", "rx";
279					atmel,fifo-size = <16>;
280					status = "disabled";
281				};
282
283				i2c5: i2c@600 {
284					compatible = "microchip,sam9x60-i2c";
285					reg = <0x600 0x200>;
286					interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
287					clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
288					dmas = <&dma0
289						(AT91_XDMAC_DT_MEM_IF(0) |
290						 AT91_XDMAC_DT_PER_IF(1) |
291						 AT91_XDMAC_DT_PERID(10))>,
292						<&dma0
293						(AT91_XDMAC_DT_MEM_IF(0) |
294						 AT91_XDMAC_DT_PER_IF(1) |
295						 AT91_XDMAC_DT_PERID(11))>;
296					dma-names = "tx", "rx";
297					atmel,fifo-size = <16>;
298					status = "disabled";
299				};
300			};
301
302			dma0: dma-controller@f0008000 {
303				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
304				reg = <0xf0008000 0x1000>;
305				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
306				#dma-cells = <1>;
307				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
308				clock-names = "dma_clk";
309			};
310
311			ssc: ssc@f0010000 {
312				compatible = "atmel,at91sam9g45-ssc";
313				reg = <0xf0010000 0x4000>;
314				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
315				dmas = <&dma0
316					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
317					 AT91_XDMAC_DT_PERID(38))>,
318				       <&dma0
319					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
320					 AT91_XDMAC_DT_PERID(39))>;
321				dma-names = "tx", "rx";
322				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
323				clock-names = "pclk";
324				status = "disabled";
325			};
326
327			qspi: spi@f0014000 {
328				compatible = "microchip,sam9x60-qspi";
329				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
330				reg-names = "qspi_base", "qspi_mmap";
331				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
332				dmas = <&dma0
333					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
334					 AT91_XDMAC_DT_PERID(26))>,
335				       <&dma0
336					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
337					 AT91_XDMAC_DT_PERID(27))>;
338				dma-names = "tx", "rx";
339				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
340				clock-names = "pclk", "qspick";
341				atmel,pmc = <&pmc>;
342				#address-cells = <1>;
343				#size-cells = <0>;
344				status = "disabled";
345			};
346
347			i2s: i2s@f001c000 {
348				compatible = "microchip,sam9x60-i2smcc";
349				reg = <0xf001c000 0x100>;
350				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
351				dmas = <&dma0
352					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
353					 AT91_XDMAC_DT_PERID(36))>,
354				       <&dma0
355					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
356					 AT91_XDMAC_DT_PERID(37))>;
357				dma-names = "tx", "rx";
358				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
359				clock-names = "pclk", "gclk";
360				status = "disabled";
361			};
362
363			flx11: flexcom@f0020000 {
364				compatible = "atmel,sama5d2-flexcom";
365				reg = <0xf0020000 0x200>;
366				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
367				#address-cells = <1>;
368				#size-cells = <1>;
369				ranges = <0x0 0xf0020000 0x800>;
370				status = "disabled";
371
372				uart11: serial@200 {
373					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
374					reg = <0x200 0x200>;
375					interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
376					dmas = <&dma0
377						(AT91_XDMAC_DT_MEM_IF(0) |
378						 AT91_XDMAC_DT_PER_IF(1) |
379						 AT91_XDMAC_DT_PERID(22))>,
380						<&dma0
381						(AT91_XDMAC_DT_MEM_IF(0) |
382						 AT91_XDMAC_DT_PER_IF(1) |
383						 AT91_XDMAC_DT_PERID(23))>;
384					dma-names = "tx", "rx";
385					clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
386					clock-names = "usart";
387					atmel,use-dma-rx;
388					atmel,use-dma-tx;
389					atmel,fifo-size = <16>;
390					status = "disabled";
391				};
392
393				i2c11: i2c@600 {
394					compatible = "microchip,sam9x60-i2c";
395					reg = <0x600 0x200>;
396					interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
397					clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
398					dmas = <&dma0
399						(AT91_XDMAC_DT_MEM_IF(0) |
400						 AT91_XDMAC_DT_PER_IF(1) |
401						 AT91_XDMAC_DT_PERID(22))>,
402						<&dma0
403						(AT91_XDMAC_DT_MEM_IF(0) |
404						 AT91_XDMAC_DT_PER_IF(1) |
405						 AT91_XDMAC_DT_PERID(23))>;
406					dma-names = "tx", "rx";
407					atmel,fifo-size = <16>;
408					status = "disabled";
409				};
410			};
411
412			flx12: flexcom@f0024000 {
413				compatible = "atmel,sama5d2-flexcom";
414				reg = <0xf0024000 0x200>;
415				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
416				#address-cells = <1>;
417				#size-cells = <1>;
418				ranges = <0x0 0xf0024000 0x800>;
419				status = "disabled";
420
421				uart12: serial@200 {
422					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
423					reg = <0x200 0x200>;
424					interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
425					dmas = <&dma0
426						(AT91_XDMAC_DT_MEM_IF(0) |
427						 AT91_XDMAC_DT_PER_IF(1) |
428						 AT91_XDMAC_DT_PERID(24))>,
429						<&dma0
430						(AT91_XDMAC_DT_MEM_IF(0) |
431						 AT91_XDMAC_DT_PER_IF(1) |
432						 AT91_XDMAC_DT_PERID(25))>;
433					dma-names = "tx", "rx";
434					clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
435					clock-names = "usart";
436					atmel,use-dma-rx;
437					atmel,use-dma-tx;
438					atmel,fifo-size = <16>;
439					status = "disabled";
440				};
441
442				i2c12: i2c@600 {
443					compatible = "microchip,sam9x60-i2c";
444					reg = <0x600 0x200>;
445					interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
446					clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
447					dmas = <&dma0
448						(AT91_XDMAC_DT_MEM_IF(0) |
449						 AT91_XDMAC_DT_PER_IF(1) |
450						 AT91_XDMAC_DT_PERID(24))>,
451						<&dma0
452						(AT91_XDMAC_DT_MEM_IF(0) |
453						 AT91_XDMAC_DT_PER_IF(1) |
454						 AT91_XDMAC_DT_PERID(25))>;
455					dma-names = "tx", "rx";
456					atmel,fifo-size = <16>;
457					status = "disabled";
458				};
459			};
460
461			pit64b: timer@f0028000 {
462				compatible = "microchip,sam9x60-pit64b";
463				reg = <0xf0028000 0x100>;
464				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
465				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
466				clock-names = "pclk", "gclk";
467			};
468
469			sha: crypto@f002c000 {
470				compatible = "atmel,at91sam9g46-sha";
471				reg = <0xf002c000 0x100>;
472				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
473				dmas = <&dma0
474					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
475					 AT91_XDMAC_DT_PERID(34))>;
476				dma-names = "tx";
477				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
478				clock-names = "sha_clk";
479			};
480
481			trng: trng@f0030000 {
482				compatible = "microchip,sam9x60-trng";
483				reg = <0xf0030000 0x100>;
484				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
485				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
486			};
487
488			aes: crypto@f0034000 {
489				compatible = "atmel,at91sam9g46-aes";
490				reg = <0xf0034000 0x100>;
491				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
492				dmas = <&dma0
493					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
494					 AT91_XDMAC_DT_PERID(32))>,
495				       <&dma0
496					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
497					 AT91_XDMAC_DT_PERID(33))>;
498				dma-names = "tx", "rx";
499				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
500				clock-names = "aes_clk";
501			};
502
503			tdes: crypto@f0038000 {
504				compatible = "atmel,at91sam9g46-tdes";
505				reg = <0xf0038000 0x100>;
506				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
507				dmas = <&dma0
508					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
509					 AT91_XDMAC_DT_PERID(31))>,
510				       <&dma0
511					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
512					 AT91_XDMAC_DT_PERID(30))>;
513				dma-names = "tx", "rx";
514				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
515				clock-names = "tdes_clk";
516			};
517
518			classd: classd@f003c000 {
519				compatible = "atmel,sama5d2-classd";
520				reg = <0xf003c000 0x100>;
521				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
522				dmas = <&dma0
523					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
524					 AT91_XDMAC_DT_PERID(35))>;
525				dma-names = "tx";
526				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
527				clock-names = "pclk", "gclk";
528				status = "disabled";
529			};
530
531			can0: can@f8000000 {
532				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
533				reg = <0xf8000000 0x300>;
534				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
535				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
536				clock-names = "can_clk";
537				status = "disabled";
538			};
539
540			can1: can@f8004000 {
541				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
542				reg = <0xf8004000 0x300>;
543				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
544				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
545				clock-names = "can_clk";
546				status = "disabled";
547			};
548
549			tcb0: timer@f8008000 {
550				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
551				#address-cells = <1>;
552				#size-cells = <0>;
553				reg = <0xf8008000 0x100>;
554				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
555				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
556				clock-names = "t0_clk", "slow_clk";
557			};
558
559			tcb1: timer@f800c000 {
560				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
561				#address-cells = <1>;
562				#size-cells = <0>;
563				reg = <0xf800c000 0x100>;
564				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
565				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
566				clock-names = "t0_clk", "slow_clk";
567			};
568
569			flx6: flexcom@f8010000 {
570				compatible = "atmel,sama5d2-flexcom";
571				reg = <0xf8010000 0x200>;
572				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
573				#address-cells = <1>;
574				#size-cells = <1>;
575				ranges = <0x0 0xf8010000 0x800>;
576				status = "disabled";
577
578				uart6: serial@200 {
579					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
580					reg = <0x200 0x200>;
581					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
582					dmas = <&dma0
583						(AT91_XDMAC_DT_MEM_IF(0) |
584						 AT91_XDMAC_DT_PER_IF(1) |
585						 AT91_XDMAC_DT_PERID(12))>,
586						<&dma0
587						(AT91_XDMAC_DT_MEM_IF(0) |
588						 AT91_XDMAC_DT_PER_IF(1) |
589						 AT91_XDMAC_DT_PERID(13))>;
590					dma-names = "tx", "rx";
591					clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
592					clock-names = "usart";
593					atmel,use-dma-rx;
594					atmel,use-dma-tx;
595					atmel,fifo-size = <16>;
596					status = "disabled";
597				};
598
599				i2c6: i2c@600 {
600					compatible = "microchip,sam9x60-i2c";
601					reg = <0x600 0x200>;
602					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
603					clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
604					dmas = <&dma0
605						(AT91_XDMAC_DT_MEM_IF(0) |
606						 AT91_XDMAC_DT_PER_IF(1) |
607						 AT91_XDMAC_DT_PERID(12))>,
608						<&dma0
609						(AT91_XDMAC_DT_MEM_IF(0) |
610						 AT91_XDMAC_DT_PER_IF(1) |
611						 AT91_XDMAC_DT_PERID(13))>;
612					dma-names = "tx", "rx";
613					atmel,fifo-size = <16>;
614					status = "disabled";
615				};
616			};
617
618			flx7: flexcom@f8014000 {
619				compatible = "atmel,sama5d2-flexcom";
620				reg = <0xf8014000 0x200>;
621				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
622				#address-cells = <1>;
623				#size-cells = <1>;
624				ranges = <0x0 0xf8014000 0x800>;
625				status = "disabled";
626
627				uart7: serial@200 {
628					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
629					reg = <0x200 0x200>;
630					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
631					dmas = <&dma0
632						(AT91_XDMAC_DT_MEM_IF(0) |
633						 AT91_XDMAC_DT_PER_IF(1) |
634						 AT91_XDMAC_DT_PERID(14))>,
635						<&dma0
636						(AT91_XDMAC_DT_MEM_IF(0) |
637						 AT91_XDMAC_DT_PER_IF(1) |
638						 AT91_XDMAC_DT_PERID(15))>;
639					dma-names = "tx", "rx";
640					clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
641					clock-names = "usart";
642					atmel,use-dma-rx;
643					atmel,use-dma-tx;
644					atmel,fifo-size = <16>;
645					status = "disabled";
646				};
647
648				i2c7: i2c@600 {
649					compatible = "microchip,sam9x60-i2c";
650					reg = <0x600 0x200>;
651					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
652					clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
653					dmas = <&dma0
654						(AT91_XDMAC_DT_MEM_IF(0) |
655						 AT91_XDMAC_DT_PER_IF(1) |
656						 AT91_XDMAC_DT_PERID(14))>,
657						<&dma0
658						(AT91_XDMAC_DT_MEM_IF(0) |
659						 AT91_XDMAC_DT_PER_IF(1) |
660						 AT91_XDMAC_DT_PERID(15))>;
661					dma-names = "tx", "rx";
662					atmel,fifo-size = <16>;
663					status = "disabled";
664				};
665			};
666
667			flx8: flexcom@f8018000 {
668				compatible = "atmel,sama5d2-flexcom";
669				reg = <0xf8018000 0x200>;
670				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
671				#address-cells = <1>;
672				#size-cells = <1>;
673				ranges = <0x0 0xf8018000 0x800>;
674				status = "disabled";
675
676				uart8: serial@200 {
677					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
678					reg = <0x200 0x200>;
679					interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
680					dmas = <&dma0
681						(AT91_XDMAC_DT_MEM_IF(0) |
682						 AT91_XDMAC_DT_PER_IF(1) |
683						 AT91_XDMAC_DT_PERID(16))>,
684						<&dma0
685						(AT91_XDMAC_DT_MEM_IF(0) |
686						 AT91_XDMAC_DT_PER_IF(1) |
687						 AT91_XDMAC_DT_PERID(17))>;
688					dma-names = "tx", "rx";
689					clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
690					clock-names = "usart";
691					atmel,use-dma-rx;
692					atmel,use-dma-tx;
693					atmel,fifo-size = <16>;
694					status = "disabled";
695				};
696
697				i2c8: i2c@600 {
698					compatible = "microchip,sam9x60-i2c";
699					reg = <0x600 0x200>;
700					interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
701					clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
702					dmas = <&dma0
703						(AT91_XDMAC_DT_MEM_IF(0) |
704						 AT91_XDMAC_DT_PER_IF(1) |
705						 AT91_XDMAC_DT_PERID(16))>,
706						<&dma0
707						(AT91_XDMAC_DT_MEM_IF(0) |
708						 AT91_XDMAC_DT_PER_IF(1) |
709						 AT91_XDMAC_DT_PERID(17))>;
710					dma-names = "tx", "rx";
711					atmel,fifo-size = <16>;
712					status = "disabled";
713				};
714			};
715
716			flx0: flexcom@f801c000 {
717				compatible = "atmel,sama5d2-flexcom";
718				reg = <0xf801c000 0x200>;
719				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
720				#address-cells = <1>;
721				#size-cells = <1>;
722				ranges = <0x0 0xf801c000 0x800>;
723				status = "disabled";
724
725				uart0: serial@200 {
726					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
727					reg = <0x200 0x200>;
728					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
729					dmas = <&dma0
730						(AT91_XDMAC_DT_MEM_IF(0) |
731						 AT91_XDMAC_DT_PER_IF(1) |
732						 AT91_XDMAC_DT_PERID(0))>,
733						<&dma0
734						(AT91_XDMAC_DT_MEM_IF(0) |
735						 AT91_XDMAC_DT_PER_IF(1) |
736						 AT91_XDMAC_DT_PERID(1))>;
737					dma-names = "tx", "rx";
738					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
739					clock-names = "usart";
740					atmel,use-dma-rx;
741					atmel,use-dma-tx;
742					atmel,fifo-size = <16>;
743					status = "disabled";
744				};
745
746				spi0: spi@400 {
747					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
748					reg = <0x400 0x200>;
749					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
750					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
751					clock-names = "spi_clk";
752					dmas = <&dma0
753						(AT91_XDMAC_DT_MEM_IF(0) |
754						 AT91_XDMAC_DT_PER_IF(1) |
755						 AT91_XDMAC_DT_PERID(0))>,
756						<&dma0
757						(AT91_XDMAC_DT_MEM_IF(0) |
758						 AT91_XDMAC_DT_PER_IF(1) |
759						 AT91_XDMAC_DT_PERID(1))>;
760					dma-names = "tx", "rx";
761					atmel,fifo-size = <16>;
762					status = "disabled";
763				};
764
765				i2c0: i2c@600 {
766					compatible = "microchip,sam9x60-i2c";
767					reg = <0x600 0x200>;
768					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
769					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
770					dmas = <&dma0
771						(AT91_XDMAC_DT_MEM_IF(0) |
772						 AT91_XDMAC_DT_PER_IF(1) |
773						 AT91_XDMAC_DT_PERID(0))>,
774						<&dma0
775						(AT91_XDMAC_DT_MEM_IF(0) |
776						 AT91_XDMAC_DT_PER_IF(1) |
777						 AT91_XDMAC_DT_PERID(1))>;
778					dma-names = "tx", "rx";
779					atmel,fifo-size = <16>;
780					status = "disabled";
781				};
782			};
783
784			flx1: flexcom@f8020000 {
785				compatible = "atmel,sama5d2-flexcom";
786				reg = <0xf8020000 0x200>;
787				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
788				#address-cells = <1>;
789				#size-cells = <1>;
790				ranges = <0x0 0xf8020000 0x800>;
791				status = "disabled";
792
793				uart1: serial@200 {
794					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
795					reg = <0x200 0x200>;
796					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
797					dmas = <&dma0
798						(AT91_XDMAC_DT_MEM_IF(0) |
799						 AT91_XDMAC_DT_PER_IF(1) |
800						 AT91_XDMAC_DT_PERID(2))>,
801						<&dma0
802						(AT91_XDMAC_DT_MEM_IF(0) |
803						 AT91_XDMAC_DT_PER_IF(1) |
804						 AT91_XDMAC_DT_PERID(3))>;
805					dma-names = "tx", "rx";
806					clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
807					clock-names = "usart";
808					atmel,use-dma-rx;
809					atmel,use-dma-tx;
810					atmel,fifo-size = <16>;
811					status = "disabled";
812				};
813
814				spi1: spi@400 {
815					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
816					reg = <0x400 0x200>;
817					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
818					clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
819					clock-names = "spi_clk";
820					dmas = <&dma0
821						(AT91_XDMAC_DT_MEM_IF(0) |
822						 AT91_XDMAC_DT_PER_IF(1) |
823						 AT91_XDMAC_DT_PERID(2))>,
824						<&dma0
825						(AT91_XDMAC_DT_MEM_IF(0) |
826						 AT91_XDMAC_DT_PER_IF(1) |
827						 AT91_XDMAC_DT_PERID(3))>;
828					dma-names = "tx", "rx";
829					atmel,fifo-size = <16>;
830					status = "disabled";
831				};
832
833				i2c1: i2c@600 {
834					compatible = "microchip,sam9x60-i2c";
835					reg = <0x600 0x200>;
836					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
837					clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
838					dmas = <&dma0
839						(AT91_XDMAC_DT_MEM_IF(0) |
840						 AT91_XDMAC_DT_PER_IF(1) |
841						 AT91_XDMAC_DT_PERID(2))>,
842						<&dma0
843						(AT91_XDMAC_DT_MEM_IF(0) |
844						 AT91_XDMAC_DT_PER_IF(1) |
845						 AT91_XDMAC_DT_PERID(3))>;
846					dma-names = "tx", "rx";
847					atmel,fifo-size = <16>;
848					status = "disabled";
849				};
850			};
851
852			flx2: flexcom@f8024000 {
853				compatible = "atmel,sama5d2-flexcom";
854				reg = <0xf8024000 0x200>;
855				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
856				#address-cells = <1>;
857				#size-cells = <1>;
858				ranges = <0x0 0xf8024000 0x800>;
859				status = "disabled";
860
861				uart2: serial@200 {
862					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
863					reg = <0x200 0x200>;
864					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
865					dmas = <&dma0
866						(AT91_XDMAC_DT_MEM_IF(0) |
867						 AT91_XDMAC_DT_PER_IF(1) |
868						 AT91_XDMAC_DT_PERID(4))>,
869						<&dma0
870						(AT91_XDMAC_DT_MEM_IF(0) |
871						 AT91_XDMAC_DT_PER_IF(1) |
872						 AT91_XDMAC_DT_PERID(5))>;
873					dma-names = "tx", "rx";
874					clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
875					clock-names = "usart";
876					atmel,use-dma-rx;
877					atmel,use-dma-tx;
878					atmel,fifo-size = <16>;
879					status = "disabled";
880				};
881
882				spi2: spi@400 {
883					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
884					reg = <0x400 0x200>;
885					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
886					clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
887					clock-names = "spi_clk";
888					dmas = <&dma0
889						(AT91_XDMAC_DT_MEM_IF(0) |
890						 AT91_XDMAC_DT_PER_IF(1) |
891						 AT91_XDMAC_DT_PERID(4))>,
892						<&dma0
893						(AT91_XDMAC_DT_MEM_IF(0) |
894						 AT91_XDMAC_DT_PER_IF(1) |
895						 AT91_XDMAC_DT_PERID(5))>;
896					dma-names = "tx", "rx";
897					atmel,fifo-size = <16>;
898					status = "disabled";
899				};
900
901				i2c2: i2c@600 {
902					compatible = "microchip,sam9x60-i2c";
903					reg = <0x600 0x200>;
904					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
905					clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
906					dmas = <&dma0
907						(AT91_XDMAC_DT_MEM_IF(0) |
908						 AT91_XDMAC_DT_PER_IF(1) |
909						 AT91_XDMAC_DT_PERID(4))>,
910						<&dma0
911						(AT91_XDMAC_DT_MEM_IF(0) |
912						 AT91_XDMAC_DT_PER_IF(1) |
913						 AT91_XDMAC_DT_PERID(5))>;
914					dma-names = "tx", "rx";
915					atmel,fifo-size = <16>;
916					status = "disabled";
917				};
918			};
919
920			flx3: flexcom@f8028000 {
921				compatible = "atmel,sama5d2-flexcom";
922				reg = <0xf8028000 0x200>;
923				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
924				#address-cells = <1>;
925				#size-cells = <1>;
926				ranges = <0x0 0xf8028000 0x800>;
927				status = "disabled";
928
929				uart3: serial@200 {
930					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
931					reg = <0x200 0x200>;
932					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
933					dmas = <&dma0
934						(AT91_XDMAC_DT_MEM_IF(0) |
935						 AT91_XDMAC_DT_PER_IF(1) |
936						 AT91_XDMAC_DT_PERID(6))>,
937						<&dma0
938						(AT91_XDMAC_DT_MEM_IF(0) |
939						 AT91_XDMAC_DT_PER_IF(1) |
940						 AT91_XDMAC_DT_PERID(7))>;
941					dma-names = "tx", "rx";
942					clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
943					clock-names = "usart";
944					atmel,use-dma-rx;
945					atmel,use-dma-tx;
946					atmel,fifo-size = <16>;
947					status = "disabled";
948				};
949
950				spi3: spi@400 {
951					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
952					reg = <0x400 0x200>;
953					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
954					clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
955					clock-names = "spi_clk";
956					dmas = <&dma0
957						(AT91_XDMAC_DT_MEM_IF(0) |
958						 AT91_XDMAC_DT_PER_IF(1) |
959						 AT91_XDMAC_DT_PERID(6))>,
960						<&dma0
961						(AT91_XDMAC_DT_MEM_IF(0) |
962						 AT91_XDMAC_DT_PER_IF(1) |
963						 AT91_XDMAC_DT_PERID(7))>;
964					dma-names = "tx", "rx";
965					atmel,fifo-size = <16>;
966					status = "disabled";
967				};
968
969				i2c3: i2c@600 {
970					compatible = "microchip,sam9x60-i2c";
971					reg = <0x600 0x200>;
972					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
973					clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
974					dmas = <&dma0
975						(AT91_XDMAC_DT_MEM_IF(0) |
976						 AT91_XDMAC_DT_PER_IF(1) |
977						 AT91_XDMAC_DT_PERID(6))>,
978						<&dma0
979						(AT91_XDMAC_DT_MEM_IF(0) |
980						 AT91_XDMAC_DT_PER_IF(1) |
981						 AT91_XDMAC_DT_PERID(7))>;
982					dma-names = "tx", "rx";
983					atmel,fifo-size = <16>;
984					status = "disabled";
985				};
986			};
987
988			macb0: ethernet@f802c000 {
989				compatible = "cdns,sam9x60-macb", "cdns,macb";
990				reg = <0xf802c000 0x1000>;
991				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
992				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
993				clock-names = "hclk", "pclk";
994				status = "disabled";
995			};
996
997			macb1: ethernet@f8030000 {
998				compatible = "cdns,sam9x60-macb", "cdns,macb";
999				reg = <0xf8030000 0x1000>;
1000				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
1001				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
1002				clock-names = "hclk", "pclk";
1003				status = "disabled";
1004			};
1005
1006			pwm0: pwm@f8034000 {
1007				compatible = "microchip,sam9x60-pwm";
1008				reg = <0xf8034000 0x300>;
1009				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
1010				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1011				#pwm-cells = <3>;
1012				status = "disabled";
1013			};
1014
1015			hlcdc: hlcdc@f8038000 {
1016				compatible = "microchip,sam9x60-hlcdc";
1017				reg = <0xf8038000 0x4000>;
1018				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1019				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
1020				clock-names = "periph_clk","sys_clk", "slow_clk";
1021				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
1022				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
1023				status = "disabled";
1024
1025				hlcdc-display-controller {
1026					compatible = "atmel,hlcdc-display-controller";
1027					#address-cells = <1>;
1028					#size-cells = <0>;
1029
1030					port@0 {
1031						#address-cells = <1>;
1032						#size-cells = <0>;
1033						reg = <0>;
1034					};
1035				};
1036
1037				hlcdc_pwm: hlcdc-pwm {
1038					compatible = "atmel,hlcdc-pwm";
1039					#pwm-cells = <3>;
1040				};
1041			};
1042
1043			flx9: flexcom@f8040000 {
1044				compatible = "atmel,sama5d2-flexcom";
1045				reg = <0xf8040000 0x200>;
1046				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1047				#address-cells = <1>;
1048				#size-cells = <1>;
1049				ranges = <0x0 0xf8040000 0x800>;
1050				status = "disabled";
1051
1052				uart9: serial@200 {
1053					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1054					reg = <0x200 0x200>;
1055					interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
1056					dmas = <&dma0
1057						(AT91_XDMAC_DT_MEM_IF(0) |
1058						 AT91_XDMAC_DT_PER_IF(1) |
1059						 AT91_XDMAC_DT_PERID(18))>,
1060						<&dma0
1061						(AT91_XDMAC_DT_MEM_IF(0) |
1062						 AT91_XDMAC_DT_PER_IF(1) |
1063						 AT91_XDMAC_DT_PERID(19))>;
1064					dma-names = "tx", "rx";
1065					clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1066					clock-names = "usart";
1067					atmel,use-dma-rx;
1068					atmel,use-dma-tx;
1069					atmel,fifo-size = <16>;
1070					status = "disabled";
1071				};
1072
1073				i2c9: i2c@600 {
1074					compatible = "microchip,sam9x60-i2c";
1075					reg = <0x600 0x200>;
1076					interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
1077					clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
1078					dmas = <&dma0
1079						(AT91_XDMAC_DT_MEM_IF(0) |
1080						 AT91_XDMAC_DT_PER_IF(1) |
1081						 AT91_XDMAC_DT_PERID(18))>,
1082						<&dma0
1083						(AT91_XDMAC_DT_MEM_IF(0) |
1084						 AT91_XDMAC_DT_PER_IF(1) |
1085						 AT91_XDMAC_DT_PERID(19))>;
1086					dma-names = "tx", "rx";
1087					atmel,fifo-size = <16>;
1088					status = "disabled";
1089				};
1090			};
1091
1092			flx10: flexcom@f8044000 {
1093				compatible = "atmel,sama5d2-flexcom";
1094				reg = <0xf8044000 0x200>;
1095				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1096				#address-cells = <1>;
1097				#size-cells = <1>;
1098				ranges = <0x0 0xf8044000 0x800>;
1099				status = "disabled";
1100
1101				uart10: serial@200 {
1102					compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1103					reg = <0x200 0x200>;
1104					interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
1105					dmas = <&dma0
1106						(AT91_XDMAC_DT_MEM_IF(0) |
1107						 AT91_XDMAC_DT_PER_IF(1) |
1108						 AT91_XDMAC_DT_PERID(20))>,
1109						<&dma0
1110						(AT91_XDMAC_DT_MEM_IF(0) |
1111						 AT91_XDMAC_DT_PER_IF(1) |
1112						 AT91_XDMAC_DT_PERID(21))>;
1113					dma-names = "tx", "rx";
1114					clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1115					clock-names = "usart";
1116					atmel,use-dma-rx;
1117					atmel,use-dma-tx;
1118					atmel,fifo-size = <16>;
1119					status = "disabled";
1120				};
1121
1122				i2c10: i2c@600 {
1123					compatible = "microchip,sam9x60-i2c";
1124					reg = <0x600 0x200>;
1125					interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
1126					clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
1127					dmas = <&dma0
1128						(AT91_XDMAC_DT_MEM_IF(0) |
1129						 AT91_XDMAC_DT_PER_IF(1) |
1130						 AT91_XDMAC_DT_PERID(20))>,
1131						<&dma0
1132						(AT91_XDMAC_DT_MEM_IF(0) |
1133						 AT91_XDMAC_DT_PER_IF(1) |
1134						 AT91_XDMAC_DT_PERID(21))>;
1135					dma-names = "tx", "rx";
1136					atmel,fifo-size = <16>;
1137					status = "disabled";
1138				};
1139			};
1140
1141			isi: isi@f8048000 {
1142				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
1143				reg = <0xf8048000 0x100>;
1144				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
1145				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
1146				clock-names = "isi_clk";
1147				status = "disabled";
1148				port {
1149					#address-cells = <1>;
1150					#size-cells = <0>;
1151				};
1152			};
1153
1154			adc: adc@f804c000 {
1155				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
1156				reg = <0xf804c000 0x100>;
1157				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
1158				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
1159				clock-names = "adc_clk";
1160				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1161				dma-names = "rx";
1162				atmel,min-sample-rate-hz = <200000>;
1163				atmel,max-sample-rate-hz = <20000000>;
1164				atmel,startup-time-ms = <4>;
1165				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1166				#io-channel-cells = <1>;
1167				status = "disabled";
1168			};
1169
1170			sfr: sfr@f8050000 {
1171				compatible = "microchip,sam9x60-sfr", "syscon";
1172				reg = <0xf8050000 0x100>;
1173			};
1174
1175			matrix: matrix@ffffde00 {
1176				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
1177				reg = <0xffffde00 0x200>;
1178			};
1179
1180			pmecc: ecc-engine@ffffe000 {
1181				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
1182				reg = <0xffffe000 0x300>,
1183				      <0xffffe600 0x100>;
1184			};
1185
1186			mpddrc: mpddrc@ffffe800 {
1187				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
1188				reg = <0xffffe800 0x200>;
1189				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
1190				clock-names = "ddrck", "mpddr";
1191			};
1192
1193			smc: smc@ffffea00 {
1194				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
1195				reg = <0xffffea00 0x100>;
1196			};
1197
1198			aic: interrupt-controller@fffff100 {
1199				compatible = "microchip,sam9x60-aic";
1200				#interrupt-cells = <3>;
1201				interrupt-controller;
1202				reg = <0xfffff100 0x100>;
1203				atmel,external-irqs = <31>;
1204			};
1205
1206			dbgu: serial@fffff200 {
1207				compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1208				reg = <0xfffff200 0x200>;
1209				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1210				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
1211				dmas = <&dma0
1212					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1213					 AT91_XDMAC_DT_PERID(28))>,
1214				       <&dma0
1215					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1216					 AT91_XDMAC_DT_PERID(29))>;
1217				dma-names = "tx", "rx";
1218				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1219				clock-names = "usart";
1220				status = "disabled";
1221			};
1222
1223			pinctrl: pinctrl@fffff400 {
1224				#address-cells = <1>;
1225				#size-cells = <1>;
1226				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1227				ranges = <0xfffff400 0xfffff400 0x800>;
1228
1229				/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
1230				atmel,mux-mask = <
1231						 /*	A	B	C	*/
1232						 0xffffffff 0xffe03fff 0xef00019d	/* pioA */
1233						 0x03ffffff 0x02fc7e7f 0x00780000	/* pioB */
1234						 0xffffffff 0xffffffff 0xf83fffff	/* pioC */
1235						 0x003fffff 0x003f8000 0x00000000	/* pioD */
1236						 >;
1237
1238				pioA: gpio@fffff400 {
1239					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1240					reg = <0xfffff400 0x200>;
1241					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
1242					#gpio-cells = <2>;
1243					gpio-controller;
1244					interrupt-controller;
1245					#interrupt-cells = <2>;
1246					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
1247				};
1248
1249				pioB: gpio@fffff600 {
1250					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1251					reg = <0xfffff600 0x200>;
1252					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
1253					#gpio-cells = <2>;
1254					gpio-controller;
1255					#gpio-lines = <26>;
1256					interrupt-controller;
1257					#interrupt-cells = <2>;
1258					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
1259				};
1260
1261				pioC: gpio@fffff800 {
1262					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1263					reg = <0xfffff800 0x200>;
1264					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
1265					#gpio-cells = <2>;
1266					gpio-controller;
1267					interrupt-controller;
1268					#interrupt-cells = <2>;
1269					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
1270				};
1271
1272				pioD: gpio@fffffa00 {
1273					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1274					reg = <0xfffffa00 0x200>;
1275					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
1276					#gpio-cells = <2>;
1277					gpio-controller;
1278					#gpio-lines = <22>;
1279					interrupt-controller;
1280					#interrupt-cells = <2>;
1281					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
1282				};
1283			};
1284
1285			pmc: clock-controller@fffffc00 {
1286				compatible = "microchip,sam9x60-pmc", "syscon";
1287				reg = <0xfffffc00 0x200>;
1288				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1289				#clock-cells = <2>;
1290				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1291				clock-names = "td_slck", "md_slck", "main_xtal";
1292			};
1293
1294			reset_controller: reset-controller@fffffe00 {
1295				compatible = "microchip,sam9x60-rstc";
1296				reg = <0xfffffe00 0x10>;
1297				clocks = <&clk32k 0>;
1298			};
1299
1300			shutdown_controller: poweroff@fffffe10 {
1301				compatible = "microchip,sam9x60-shdwc";
1302				reg = <0xfffffe10 0x10>;
1303				clocks = <&clk32k 0>;
1304				#address-cells = <1>;
1305				#size-cells = <0>;
1306				atmel,wakeup-rtc-timer;
1307				atmel,wakeup-rtt-timer;
1308				status = "disabled";
1309			};
1310
1311			rtt: rtc@fffffe20 {
1312				compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1313				reg = <0xfffffe20 0x20>;
1314				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1315				clocks = <&clk32k 0>;
1316			};
1317
1318			pit: timer@fffffe40 {
1319				compatible = "atmel,at91sam9260-pit";
1320				reg = <0xfffffe40 0x10>;
1321				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1322				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
1323			};
1324
1325			clk32k: clock-controller@fffffe50 {
1326				compatible = "microchip,sam9x60-sckc";
1327				reg = <0xfffffe50 0x4>;
1328				clocks = <&slow_xtal>;
1329				#clock-cells = <1>;
1330			};
1331
1332			gpbr: syscon@fffffe60 {
1333				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
1334				reg = <0xfffffe60 0x10>;
1335			};
1336
1337			rtc: rtc@fffffea8 {
1338				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
1339				reg = <0xfffffea8 0x100>;
1340				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1341				clocks = <&clk32k 0>;
1342			};
1343
1344			watchdog: watchdog@ffffff80 {
1345				compatible = "microchip,sam9x60-wdt";
1346				reg = <0xffffff80 0x24>;
1347				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1348				clocks = <&clk32k 0>;
1349				status = "disabled";
1350			};
1351		};
1352	};
1353};
1354