1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> 8 */ 9 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Microchip SAM9X60 SoC"; 22 compatible = "microchip,sam9x60"; 23 interrupt-parent = <&aic>; 24 25 aliases { 26 serial0 = &dbgu; 27 gpio0 = &pioA; 28 gpio1 = &pioB; 29 gpio2 = &pioC; 30 gpio3 = &pioD; 31 tcb0 = &tcb0; 32 tcb1 = &tcb1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm926ej-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@20000000 { 47 device_type = "memory"; 48 reg = <0x20000000 0x10000000>; 49 }; 50 51 clocks { 52 slow_xtal: slow_xtal { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 }; 56 57 main_xtal: main_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 sram: sram@300000 { 64 compatible = "mmio-sram"; 65 reg = <0x00300000 0x100000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0 0x00300000 0x100000>; 69 }; 70 71 ahb { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 usb0: gadget@500000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 compatible = "microchip,sam9x60-udc"; 81 reg = <0x00500000 0x100000 82 0xf803c000 0x400>; 83 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 84 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 85 clock-names = "pclk", "hclk"; 86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 87 assigned-clock-rates = <480000000>; 88 status = "disabled"; 89 }; 90 91 usb1: ohci@600000 { 92 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 93 reg = <0x00600000 0x100000>; 94 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 95 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 96 clock-names = "ohci_clk", "hclk", "uhpck"; 97 status = "disabled"; 98 }; 99 100 usb2: ehci@700000 { 101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 102 reg = <0x00700000 0x100000>; 103 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 104 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 105 clock-names = "usb_clk", "ehci_clk"; 106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 107 assigned-clock-rates = <480000000>; 108 status = "disabled"; 109 }; 110 111 ebi: ebi@10000000 { 112 compatible = "microchip,sam9x60-ebi"; 113 #address-cells = <2>; 114 #size-cells = <1>; 115 atmel,smc = <&smc>; 116 microchip,sfr = <&sfr>; 117 reg = <0x10000000 0x60000000>; 118 ranges = <0x0 0x0 0x10000000 0x10000000 119 0x1 0x0 0x20000000 0x10000000 120 0x2 0x0 0x30000000 0x10000000 121 0x3 0x0 0x40000000 0x10000000 122 0x4 0x0 0x50000000 0x10000000 123 0x5 0x0 0x60000000 0x10000000>; 124 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 125 status = "disabled"; 126 127 nand_controller: nand-controller { 128 compatible = "microchip,sam9x60-nand-controller"; 129 ecc-engine = <&pmecc>; 130 #address-cells = <2>; 131 #size-cells = <1>; 132 ranges; 133 status = "disabled"; 134 }; 135 }; 136 137 sdmmc0: sdio-host@80000000 { 138 compatible = "microchip,sam9x60-sdhci"; 139 reg = <0x80000000 0x300>; 140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 141 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 142 clock-names = "hclock", "multclk"; 143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 144 assigned-clock-rates = <100000000>; 145 status = "disabled"; 146 }; 147 148 sdmmc1: sdio-host@90000000 { 149 compatible = "microchip,sam9x60-sdhci"; 150 reg = <0x90000000 0x300>; 151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 152 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 153 clock-names = "hclock", "multclk"; 154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 155 assigned-clock-rates = <100000000>; 156 status = "disabled"; 157 }; 158 159 apb { 160 compatible = "simple-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 165 flx4: flexcom@f0000000 { 166 compatible = "atmel,sama5d2-flexcom"; 167 reg = <0xf0000000 0x200>; 168 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0x0 0xf0000000 0x800>; 172 status = "disabled"; 173 174 uart4: serial@200 { 175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 176 reg = <0x200 0x200>; 177 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 178 dmas = <&dma0 179 (AT91_XDMAC_DT_MEM_IF(0) | 180 AT91_XDMAC_DT_PER_IF(1) | 181 AT91_XDMAC_DT_PERID(8))>, 182 <&dma0 183 (AT91_XDMAC_DT_MEM_IF(0) | 184 AT91_XDMAC_DT_PER_IF(1) | 185 AT91_XDMAC_DT_PERID(9))>; 186 dma-names = "tx", "rx"; 187 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 188 clock-names = "usart"; 189 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 190 atmel,use-dma-rx; 191 atmel,use-dma-tx; 192 atmel,fifo-size = <16>; 193 status = "disabled"; 194 }; 195 196 spi4: spi@400 { 197 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 198 reg = <0x400 0x200>; 199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 201 clock-names = "spi_clk"; 202 dmas = <&dma0 203 (AT91_XDMAC_DT_MEM_IF(0) | 204 AT91_XDMAC_DT_PER_IF(1) | 205 AT91_XDMAC_DT_PERID(8))>, 206 <&dma0 207 (AT91_XDMAC_DT_MEM_IF(0) | 208 AT91_XDMAC_DT_PER_IF(1) | 209 AT91_XDMAC_DT_PERID(9))>; 210 dma-names = "tx", "rx"; 211 atmel,fifo-size = <16>; 212 status = "disabled"; 213 }; 214 215 i2c4: i2c@600 { 216 compatible = "microchip,sam9x60-i2c"; 217 reg = <0x600 0x200>; 218 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 219 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 220 dmas = <&dma0 221 (AT91_XDMAC_DT_MEM_IF(0) | 222 AT91_XDMAC_DT_PER_IF(1) | 223 AT91_XDMAC_DT_PERID(8))>, 224 <&dma0 225 (AT91_XDMAC_DT_MEM_IF(0) | 226 AT91_XDMAC_DT_PER_IF(1) | 227 AT91_XDMAC_DT_PERID(9))>; 228 dma-names = "tx", "rx"; 229 atmel,fifo-size = <16>; 230 status = "disabled"; 231 }; 232 }; 233 234 flx5: flexcom@f0004000 { 235 compatible = "atmel,sama5d2-flexcom"; 236 reg = <0xf0004000 0x200>; 237 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 ranges = <0x0 0xf0004000 0x800>; 241 status = "disabled"; 242 243 uart5: serial@200 { 244 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 245 reg = <0x200 0x200>; 246 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 247 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 248 dmas = <&dma0 249 (AT91_XDMAC_DT_MEM_IF(0) | 250 AT91_XDMAC_DT_PER_IF(1) | 251 AT91_XDMAC_DT_PERID(10))>, 252 <&dma0 253 (AT91_XDMAC_DT_MEM_IF(0) | 254 AT91_XDMAC_DT_PER_IF(1) | 255 AT91_XDMAC_DT_PERID(11))>; 256 dma-names = "tx", "rx"; 257 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 258 clock-names = "usart"; 259 atmel,use-dma-rx; 260 atmel,use-dma-tx; 261 atmel,fifo-size = <16>; 262 status = "disabled"; 263 }; 264 265 spi5: spi@400 { 266 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 267 reg = <0x400 0x200>; 268 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 269 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 270 clock-names = "spi_clk"; 271 dmas = <&dma0 272 (AT91_XDMAC_DT_MEM_IF(0) | 273 AT91_XDMAC_DT_PER_IF(1) | 274 AT91_XDMAC_DT_PERID(10))>, 275 <&dma0 276 (AT91_XDMAC_DT_MEM_IF(0) | 277 AT91_XDMAC_DT_PER_IF(1) | 278 AT91_XDMAC_DT_PERID(11))>; 279 dma-names = "tx", "rx"; 280 atmel,fifo-size = <16>; 281 status = "disabled"; 282 }; 283 284 i2c5: i2c@600 { 285 compatible = "microchip,sam9x60-i2c"; 286 reg = <0x600 0x200>; 287 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 288 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 289 dmas = <&dma0 290 (AT91_XDMAC_DT_MEM_IF(0) | 291 AT91_XDMAC_DT_PER_IF(1) | 292 AT91_XDMAC_DT_PERID(10))>, 293 <&dma0 294 (AT91_XDMAC_DT_MEM_IF(0) | 295 AT91_XDMAC_DT_PER_IF(1) | 296 AT91_XDMAC_DT_PERID(11))>; 297 dma-names = "tx", "rx"; 298 atmel,fifo-size = <16>; 299 status = "disabled"; 300 }; 301 }; 302 303 dma0: dma-controller@f0008000 { 304 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; 305 reg = <0xf0008000 0x1000>; 306 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 307 #dma-cells = <1>; 308 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 309 clock-names = "dma_clk"; 310 }; 311 312 ssc: ssc@f0010000 { 313 compatible = "atmel,at91sam9g45-ssc"; 314 reg = <0xf0010000 0x4000>; 315 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 316 dmas = <&dma0 317 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 318 AT91_XDMAC_DT_PERID(38))>, 319 <&dma0 320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 321 AT91_XDMAC_DT_PERID(39))>; 322 dma-names = "tx", "rx"; 323 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 324 clock-names = "pclk"; 325 status = "disabled"; 326 }; 327 328 qspi: spi@f0014000 { 329 compatible = "microchip,sam9x60-qspi"; 330 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 331 reg-names = "qspi_base", "qspi_mmap"; 332 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 333 dmas = <&dma0 334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 335 AT91_XDMAC_DT_PERID(26))>, 336 <&dma0 337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 338 AT91_XDMAC_DT_PERID(27))>; 339 dma-names = "tx", "rx"; 340 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; 341 clock-names = "pclk", "qspick"; 342 atmel,pmc = <&pmc>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 status = "disabled"; 346 }; 347 348 i2s: i2s@f001c000 { 349 compatible = "microchip,sam9x60-i2smcc"; 350 reg = <0xf001c000 0x100>; 351 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 352 dmas = <&dma0 353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 354 AT91_XDMAC_DT_PERID(36))>, 355 <&dma0 356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 357 AT91_XDMAC_DT_PERID(37))>; 358 dma-names = "tx", "rx"; 359 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 360 clock-names = "pclk", "gclk"; 361 status = "disabled"; 362 }; 363 364 flx11: flexcom@f0020000 { 365 compatible = "atmel,sama5d2-flexcom"; 366 reg = <0xf0020000 0x200>; 367 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 ranges = <0x0 0xf0020000 0x800>; 371 status = "disabled"; 372 373 uart11: serial@200 { 374 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 375 reg = <0x200 0x200>; 376 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 377 dmas = <&dma0 378 (AT91_XDMAC_DT_MEM_IF(0) | 379 AT91_XDMAC_DT_PER_IF(1) | 380 AT91_XDMAC_DT_PERID(22))>, 381 <&dma0 382 (AT91_XDMAC_DT_MEM_IF(0) | 383 AT91_XDMAC_DT_PER_IF(1) | 384 AT91_XDMAC_DT_PERID(23))>; 385 dma-names = "tx", "rx"; 386 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 387 clock-names = "usart"; 388 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 389 atmel,use-dma-rx; 390 atmel,use-dma-tx; 391 atmel,fifo-size = <16>; 392 status = "disabled"; 393 }; 394 395 i2c11: i2c@600 { 396 compatible = "microchip,sam9x60-i2c"; 397 reg = <0x600 0x200>; 398 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 399 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 400 dmas = <&dma0 401 (AT91_XDMAC_DT_MEM_IF(0) | 402 AT91_XDMAC_DT_PER_IF(1) | 403 AT91_XDMAC_DT_PERID(22))>, 404 <&dma0 405 (AT91_XDMAC_DT_MEM_IF(0) | 406 AT91_XDMAC_DT_PER_IF(1) | 407 AT91_XDMAC_DT_PERID(23))>; 408 dma-names = "tx", "rx"; 409 atmel,fifo-size = <16>; 410 status = "disabled"; 411 }; 412 }; 413 414 flx12: flexcom@f0024000 { 415 compatible = "atmel,sama5d2-flexcom"; 416 reg = <0xf0024000 0x200>; 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0x0 0xf0024000 0x800>; 421 status = "disabled"; 422 423 uart12: serial@200 { 424 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 425 reg = <0x200 0x200>; 426 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 427 dmas = <&dma0 428 (AT91_XDMAC_DT_MEM_IF(0) | 429 AT91_XDMAC_DT_PER_IF(1) | 430 AT91_XDMAC_DT_PERID(24))>, 431 <&dma0 432 (AT91_XDMAC_DT_MEM_IF(0) | 433 AT91_XDMAC_DT_PER_IF(1) | 434 AT91_XDMAC_DT_PERID(25))>; 435 dma-names = "tx", "rx"; 436 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 437 clock-names = "usart"; 438 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 439 atmel,use-dma-rx; 440 atmel,use-dma-tx; 441 atmel,fifo-size = <16>; 442 status = "disabled"; 443 }; 444 445 i2c12: i2c@600 { 446 compatible = "microchip,sam9x60-i2c"; 447 reg = <0x600 0x200>; 448 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 449 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 450 dmas = <&dma0 451 (AT91_XDMAC_DT_MEM_IF(0) | 452 AT91_XDMAC_DT_PER_IF(1) | 453 AT91_XDMAC_DT_PERID(24))>, 454 <&dma0 455 (AT91_XDMAC_DT_MEM_IF(0) | 456 AT91_XDMAC_DT_PER_IF(1) | 457 AT91_XDMAC_DT_PERID(25))>; 458 dma-names = "tx", "rx"; 459 atmel,fifo-size = <16>; 460 status = "disabled"; 461 }; 462 }; 463 464 pit64b: timer@f0028000 { 465 compatible = "microchip,sam9x60-pit64b"; 466 reg = <0xf0028000 0x100>; 467 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 468 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 469 clock-names = "pclk", "gclk"; 470 }; 471 472 sha: crypto@f002c000 { 473 compatible = "atmel,at91sam9g46-sha"; 474 reg = <0xf002c000 0x100>; 475 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 476 dmas = <&dma0 477 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 478 AT91_XDMAC_DT_PERID(34))>; 479 dma-names = "tx"; 480 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 481 clock-names = "sha_clk"; 482 }; 483 484 trng: trng@f0030000 { 485 compatible = "microchip,sam9x60-trng"; 486 reg = <0xf0030000 0x100>; 487 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 488 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 489 }; 490 491 aes: crypto@f0034000 { 492 compatible = "atmel,at91sam9g46-aes"; 493 reg = <0xf0034000 0x100>; 494 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 495 dmas = <&dma0 496 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 497 AT91_XDMAC_DT_PERID(32))>, 498 <&dma0 499 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 500 AT91_XDMAC_DT_PERID(33))>; 501 dma-names = "tx", "rx"; 502 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 503 clock-names = "aes_clk"; 504 }; 505 506 tdes: crypto@f0038000 { 507 compatible = "atmel,at91sam9g46-tdes"; 508 reg = <0xf0038000 0x100>; 509 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 510 dmas = <&dma0 511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 512 AT91_XDMAC_DT_PERID(31))>, 513 <&dma0 514 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 515 AT91_XDMAC_DT_PERID(30))>; 516 dma-names = "tx", "rx"; 517 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 518 clock-names = "tdes_clk"; 519 }; 520 521 classd: classd@f003c000 { 522 compatible = "atmel,sama5d2-classd"; 523 reg = <0xf003c000 0x100>; 524 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 525 dmas = <&dma0 526 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 527 AT91_XDMAC_DT_PERID(35))>; 528 dma-names = "tx"; 529 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 530 clock-names = "pclk", "gclk"; 531 status = "disabled"; 532 }; 533 534 can0: can@f8000000 { 535 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 536 reg = <0xf8000000 0x300>; 537 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 538 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 539 clock-names = "can_clk"; 540 status = "disabled"; 541 }; 542 543 can1: can@f8004000 { 544 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 545 reg = <0xf8004000 0x300>; 546 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 547 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 548 clock-names = "can_clk"; 549 status = "disabled"; 550 }; 551 552 tcb0: timer@f8008000 { 553 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 reg = <0xf8008000 0x100>; 557 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 558 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; 559 clock-names = "t0_clk", "slow_clk"; 560 }; 561 562 tcb1: timer@f800c000 { 563 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0xf800c000 0x100>; 567 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; 569 clock-names = "t0_clk", "slow_clk"; 570 }; 571 572 flx6: flexcom@f8010000 { 573 compatible = "atmel,sama5d2-flexcom"; 574 reg = <0xf8010000 0x200>; 575 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 576 #address-cells = <1>; 577 #size-cells = <1>; 578 ranges = <0x0 0xf8010000 0x800>; 579 status = "disabled"; 580 581 uart6: serial@200 { 582 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 583 reg = <0x200 0x200>; 584 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 585 dmas = <&dma0 586 (AT91_XDMAC_DT_MEM_IF(0) | 587 AT91_XDMAC_DT_PER_IF(1) | 588 AT91_XDMAC_DT_PERID(12))>, 589 <&dma0 590 (AT91_XDMAC_DT_MEM_IF(0) | 591 AT91_XDMAC_DT_PER_IF(1) | 592 AT91_XDMAC_DT_PERID(13))>; 593 dma-names = "tx", "rx"; 594 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 595 clock-names = "usart"; 596 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 597 atmel,use-dma-rx; 598 atmel,use-dma-tx; 599 atmel,fifo-size = <16>; 600 status = "disabled"; 601 }; 602 603 i2c6: i2c@600 { 604 compatible = "microchip,sam9x60-i2c"; 605 reg = <0x600 0x200>; 606 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 607 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 608 dmas = <&dma0 609 (AT91_XDMAC_DT_MEM_IF(0) | 610 AT91_XDMAC_DT_PER_IF(1) | 611 AT91_XDMAC_DT_PERID(12))>, 612 <&dma0 613 (AT91_XDMAC_DT_MEM_IF(0) | 614 AT91_XDMAC_DT_PER_IF(1) | 615 AT91_XDMAC_DT_PERID(13))>; 616 dma-names = "tx", "rx"; 617 atmel,fifo-size = <16>; 618 status = "disabled"; 619 }; 620 }; 621 622 flx7: flexcom@f8014000 { 623 compatible = "atmel,sama5d2-flexcom"; 624 reg = <0xf8014000 0x200>; 625 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges = <0x0 0xf8014000 0x800>; 629 status = "disabled"; 630 631 uart7: serial@200 { 632 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 633 reg = <0x200 0x200>; 634 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 635 dmas = <&dma0 636 (AT91_XDMAC_DT_MEM_IF(0) | 637 AT91_XDMAC_DT_PER_IF(1) | 638 AT91_XDMAC_DT_PERID(14))>, 639 <&dma0 640 (AT91_XDMAC_DT_MEM_IF(0) | 641 AT91_XDMAC_DT_PER_IF(1) | 642 AT91_XDMAC_DT_PERID(15))>; 643 dma-names = "tx", "rx"; 644 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 645 clock-names = "usart"; 646 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 647 atmel,use-dma-rx; 648 atmel,use-dma-tx; 649 atmel,fifo-size = <16>; 650 status = "disabled"; 651 }; 652 653 i2c7: i2c@600 { 654 compatible = "microchip,sam9x60-i2c"; 655 reg = <0x600 0x200>; 656 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 657 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 658 dmas = <&dma0 659 (AT91_XDMAC_DT_MEM_IF(0) | 660 AT91_XDMAC_DT_PER_IF(1) | 661 AT91_XDMAC_DT_PERID(14))>, 662 <&dma0 663 (AT91_XDMAC_DT_MEM_IF(0) | 664 AT91_XDMAC_DT_PER_IF(1) | 665 AT91_XDMAC_DT_PERID(15))>; 666 dma-names = "tx", "rx"; 667 atmel,fifo-size = <16>; 668 status = "disabled"; 669 }; 670 }; 671 672 flx8: flexcom@f8018000 { 673 compatible = "atmel,sama5d2-flexcom"; 674 reg = <0xf8018000 0x200>; 675 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0x0 0xf8018000 0x800>; 679 status = "disabled"; 680 681 uart8: serial@200 { 682 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 683 reg = <0x200 0x200>; 684 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 685 dmas = <&dma0 686 (AT91_XDMAC_DT_MEM_IF(0) | 687 AT91_XDMAC_DT_PER_IF(1) | 688 AT91_XDMAC_DT_PERID(16))>, 689 <&dma0 690 (AT91_XDMAC_DT_MEM_IF(0) | 691 AT91_XDMAC_DT_PER_IF(1) | 692 AT91_XDMAC_DT_PERID(17))>; 693 dma-names = "tx", "rx"; 694 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 695 clock-names = "usart"; 696 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 697 atmel,use-dma-rx; 698 atmel,use-dma-tx; 699 atmel,fifo-size = <16>; 700 status = "disabled"; 701 }; 702 703 i2c8: i2c@600 { 704 compatible = "microchip,sam9x60-i2c"; 705 reg = <0x600 0x200>; 706 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 707 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 708 dmas = <&dma0 709 (AT91_XDMAC_DT_MEM_IF(0) | 710 AT91_XDMAC_DT_PER_IF(1) | 711 AT91_XDMAC_DT_PERID(16))>, 712 <&dma0 713 (AT91_XDMAC_DT_MEM_IF(0) | 714 AT91_XDMAC_DT_PER_IF(1) | 715 AT91_XDMAC_DT_PERID(17))>; 716 dma-names = "tx", "rx"; 717 atmel,fifo-size = <16>; 718 status = "disabled"; 719 }; 720 }; 721 722 flx0: flexcom@f801c000 { 723 compatible = "atmel,sama5d2-flexcom"; 724 reg = <0xf801c000 0x200>; 725 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 726 #address-cells = <1>; 727 #size-cells = <1>; 728 ranges = <0x0 0xf801c000 0x800>; 729 status = "disabled"; 730 731 uart0: serial@200 { 732 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 733 reg = <0x200 0x200>; 734 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 735 dmas = <&dma0 736 (AT91_XDMAC_DT_MEM_IF(0) | 737 AT91_XDMAC_DT_PER_IF(1) | 738 AT91_XDMAC_DT_PERID(0))>, 739 <&dma0 740 (AT91_XDMAC_DT_MEM_IF(0) | 741 AT91_XDMAC_DT_PER_IF(1) | 742 AT91_XDMAC_DT_PERID(1))>; 743 dma-names = "tx", "rx"; 744 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 745 clock-names = "usart"; 746 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 747 atmel,use-dma-rx; 748 atmel,use-dma-tx; 749 atmel,fifo-size = <16>; 750 status = "disabled"; 751 }; 752 753 spi0: spi@400 { 754 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 755 reg = <0x400 0x200>; 756 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 757 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 758 clock-names = "spi_clk"; 759 dmas = <&dma0 760 (AT91_XDMAC_DT_MEM_IF(0) | 761 AT91_XDMAC_DT_PER_IF(1) | 762 AT91_XDMAC_DT_PERID(0))>, 763 <&dma0 764 (AT91_XDMAC_DT_MEM_IF(0) | 765 AT91_XDMAC_DT_PER_IF(1) | 766 AT91_XDMAC_DT_PERID(1))>; 767 dma-names = "tx", "rx"; 768 atmel,fifo-size = <16>; 769 status = "disabled"; 770 }; 771 772 i2c0: i2c@600 { 773 compatible = "microchip,sam9x60-i2c"; 774 reg = <0x600 0x200>; 775 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 777 dmas = <&dma0 778 (AT91_XDMAC_DT_MEM_IF(0) | 779 AT91_XDMAC_DT_PER_IF(1) | 780 AT91_XDMAC_DT_PERID(0))>, 781 <&dma0 782 (AT91_XDMAC_DT_MEM_IF(0) | 783 AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(1))>; 785 dma-names = "tx", "rx"; 786 atmel,fifo-size = <16>; 787 status = "disabled"; 788 }; 789 }; 790 791 flx1: flexcom@f8020000 { 792 compatible = "atmel,sama5d2-flexcom"; 793 reg = <0xf8020000 0x200>; 794 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 ranges = <0x0 0xf8020000 0x800>; 798 status = "disabled"; 799 800 uart1: serial@200 { 801 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 802 reg = <0x200 0x200>; 803 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 804 dmas = <&dma0 805 (AT91_XDMAC_DT_MEM_IF(0) | 806 AT91_XDMAC_DT_PER_IF(1) | 807 AT91_XDMAC_DT_PERID(2))>, 808 <&dma0 809 (AT91_XDMAC_DT_MEM_IF(0) | 810 AT91_XDMAC_DT_PER_IF(1) | 811 AT91_XDMAC_DT_PERID(3))>; 812 dma-names = "tx", "rx"; 813 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 814 clock-names = "usart"; 815 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 816 atmel,use-dma-rx; 817 atmel,use-dma-tx; 818 atmel,fifo-size = <16>; 819 status = "disabled"; 820 }; 821 822 spi1: spi@400 { 823 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 824 reg = <0x400 0x200>; 825 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 826 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 827 clock-names = "spi_clk"; 828 dmas = <&dma0 829 (AT91_XDMAC_DT_MEM_IF(0) | 830 AT91_XDMAC_DT_PER_IF(1) | 831 AT91_XDMAC_DT_PERID(2))>, 832 <&dma0 833 (AT91_XDMAC_DT_MEM_IF(0) | 834 AT91_XDMAC_DT_PER_IF(1) | 835 AT91_XDMAC_DT_PERID(3))>; 836 dma-names = "tx", "rx"; 837 atmel,fifo-size = <16>; 838 status = "disabled"; 839 }; 840 841 i2c1: i2c@600 { 842 compatible = "microchip,sam9x60-i2c"; 843 reg = <0x600 0x200>; 844 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 845 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 846 dmas = <&dma0 847 (AT91_XDMAC_DT_MEM_IF(0) | 848 AT91_XDMAC_DT_PER_IF(1) | 849 AT91_XDMAC_DT_PERID(2))>, 850 <&dma0 851 (AT91_XDMAC_DT_MEM_IF(0) | 852 AT91_XDMAC_DT_PER_IF(1) | 853 AT91_XDMAC_DT_PERID(3))>; 854 dma-names = "tx", "rx"; 855 atmel,fifo-size = <16>; 856 status = "disabled"; 857 }; 858 }; 859 860 flx2: flexcom@f8024000 { 861 compatible = "atmel,sama5d2-flexcom"; 862 reg = <0xf8024000 0x200>; 863 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 ranges = <0x0 0xf8024000 0x800>; 867 status = "disabled"; 868 869 uart2: serial@200 { 870 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 871 reg = <0x200 0x200>; 872 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 873 dmas = <&dma0 874 (AT91_XDMAC_DT_MEM_IF(0) | 875 AT91_XDMAC_DT_PER_IF(1) | 876 AT91_XDMAC_DT_PERID(4))>, 877 <&dma0 878 (AT91_XDMAC_DT_MEM_IF(0) | 879 AT91_XDMAC_DT_PER_IF(1) | 880 AT91_XDMAC_DT_PERID(5))>; 881 dma-names = "tx", "rx"; 882 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 883 clock-names = "usart"; 884 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 885 atmel,use-dma-rx; 886 atmel,use-dma-tx; 887 atmel,fifo-size = <16>; 888 status = "disabled"; 889 }; 890 891 spi2: spi@400 { 892 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 893 reg = <0x400 0x200>; 894 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 895 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 896 clock-names = "spi_clk"; 897 dmas = <&dma0 898 (AT91_XDMAC_DT_MEM_IF(0) | 899 AT91_XDMAC_DT_PER_IF(1) | 900 AT91_XDMAC_DT_PERID(4))>, 901 <&dma0 902 (AT91_XDMAC_DT_MEM_IF(0) | 903 AT91_XDMAC_DT_PER_IF(1) | 904 AT91_XDMAC_DT_PERID(5))>; 905 dma-names = "tx", "rx"; 906 atmel,fifo-size = <16>; 907 status = "disabled"; 908 }; 909 910 i2c2: i2c@600 { 911 compatible = "microchip,sam9x60-i2c"; 912 reg = <0x600 0x200>; 913 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 914 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 915 dmas = <&dma0 916 (AT91_XDMAC_DT_MEM_IF(0) | 917 AT91_XDMAC_DT_PER_IF(1) | 918 AT91_XDMAC_DT_PERID(4))>, 919 <&dma0 920 (AT91_XDMAC_DT_MEM_IF(0) | 921 AT91_XDMAC_DT_PER_IF(1) | 922 AT91_XDMAC_DT_PERID(5))>; 923 dma-names = "tx", "rx"; 924 atmel,fifo-size = <16>; 925 status = "disabled"; 926 }; 927 }; 928 929 flx3: flexcom@f8028000 { 930 compatible = "atmel,sama5d2-flexcom"; 931 reg = <0xf8028000 0x200>; 932 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 933 #address-cells = <1>; 934 #size-cells = <1>; 935 ranges = <0x0 0xf8028000 0x800>; 936 status = "disabled"; 937 938 uart3: serial@200 { 939 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 940 reg = <0x200 0x200>; 941 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 942 dmas = <&dma0 943 (AT91_XDMAC_DT_MEM_IF(0) | 944 AT91_XDMAC_DT_PER_IF(1) | 945 AT91_XDMAC_DT_PERID(6))>, 946 <&dma0 947 (AT91_XDMAC_DT_MEM_IF(0) | 948 AT91_XDMAC_DT_PER_IF(1) | 949 AT91_XDMAC_DT_PERID(7))>; 950 dma-names = "tx", "rx"; 951 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 952 clock-names = "usart"; 953 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 954 atmel,use-dma-rx; 955 atmel,use-dma-tx; 956 atmel,fifo-size = <16>; 957 status = "disabled"; 958 }; 959 960 spi3: spi@400 { 961 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 962 reg = <0x400 0x200>; 963 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 964 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 965 clock-names = "spi_clk"; 966 dmas = <&dma0 967 (AT91_XDMAC_DT_MEM_IF(0) | 968 AT91_XDMAC_DT_PER_IF(1) | 969 AT91_XDMAC_DT_PERID(6))>, 970 <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(7))>; 974 dma-names = "tx", "rx"; 975 atmel,fifo-size = <16>; 976 status = "disabled"; 977 }; 978 979 i2c3: i2c@600 { 980 compatible = "microchip,sam9x60-i2c"; 981 reg = <0x600 0x200>; 982 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 983 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 984 dmas = <&dma0 985 (AT91_XDMAC_DT_MEM_IF(0) | 986 AT91_XDMAC_DT_PER_IF(1) | 987 AT91_XDMAC_DT_PERID(6))>, 988 <&dma0 989 (AT91_XDMAC_DT_MEM_IF(0) | 990 AT91_XDMAC_DT_PER_IF(1) | 991 AT91_XDMAC_DT_PERID(7))>; 992 dma-names = "tx", "rx"; 993 atmel,fifo-size = <16>; 994 status = "disabled"; 995 }; 996 }; 997 998 macb0: ethernet@f802c000 { 999 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1000 reg = <0xf802c000 0x1000>; 1001 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 1002 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 1003 clock-names = "hclk", "pclk"; 1004 status = "disabled"; 1005 }; 1006 1007 macb1: ethernet@f8030000 { 1008 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1009 reg = <0xf8030000 0x1000>; 1010 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; 1011 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; 1012 clock-names = "hclk", "pclk"; 1013 status = "disabled"; 1014 }; 1015 1016 pwm0: pwm@f8034000 { 1017 compatible = "microchip,sam9x60-pwm"; 1018 reg = <0xf8034000 0x300>; 1019 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 1020 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1021 #pwm-cells = <3>; 1022 status = "disabled"; 1023 }; 1024 1025 hlcdc: hlcdc@f8038000 { 1026 compatible = "microchip,sam9x60-hlcdc"; 1027 reg = <0xf8038000 0x4000>; 1028 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 1029 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 1030 clock-names = "periph_clk","sys_clk", "slow_clk"; 1031 assigned-clocks = <&pmc PMC_TYPE_GCK 25>; 1032 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; 1033 status = "disabled"; 1034 1035 hlcdc-display-controller { 1036 compatible = "atmel,hlcdc-display-controller"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 port@0 { 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 reg = <0>; 1044 }; 1045 }; 1046 1047 hlcdc_pwm: hlcdc-pwm { 1048 compatible = "atmel,hlcdc-pwm"; 1049 #pwm-cells = <3>; 1050 }; 1051 }; 1052 1053 flx9: flexcom@f8040000 { 1054 compatible = "atmel,sama5d2-flexcom"; 1055 reg = <0xf8040000 0x200>; 1056 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1057 #address-cells = <1>; 1058 #size-cells = <1>; 1059 ranges = <0x0 0xf8040000 0x800>; 1060 status = "disabled"; 1061 1062 uart9: serial@200 { 1063 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1064 reg = <0x200 0x200>; 1065 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1066 dmas = <&dma0 1067 (AT91_XDMAC_DT_MEM_IF(0) | 1068 AT91_XDMAC_DT_PER_IF(1) | 1069 AT91_XDMAC_DT_PERID(18))>, 1070 <&dma0 1071 (AT91_XDMAC_DT_MEM_IF(0) | 1072 AT91_XDMAC_DT_PER_IF(1) | 1073 AT91_XDMAC_DT_PERID(19))>; 1074 dma-names = "tx", "rx"; 1075 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1076 clock-names = "usart"; 1077 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1078 atmel,use-dma-rx; 1079 atmel,use-dma-tx; 1080 atmel,fifo-size = <16>; 1081 status = "disabled"; 1082 }; 1083 1084 i2c9: i2c@600 { 1085 compatible = "microchip,sam9x60-i2c"; 1086 reg = <0x600 0x200>; 1087 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1088 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1089 dmas = <&dma0 1090 (AT91_XDMAC_DT_MEM_IF(0) | 1091 AT91_XDMAC_DT_PER_IF(1) | 1092 AT91_XDMAC_DT_PERID(18))>, 1093 <&dma0 1094 (AT91_XDMAC_DT_MEM_IF(0) | 1095 AT91_XDMAC_DT_PER_IF(1) | 1096 AT91_XDMAC_DT_PERID(19))>; 1097 dma-names = "tx", "rx"; 1098 atmel,fifo-size = <16>; 1099 status = "disabled"; 1100 }; 1101 }; 1102 1103 flx10: flexcom@f8044000 { 1104 compatible = "atmel,sama5d2-flexcom"; 1105 reg = <0xf8044000 0x200>; 1106 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1107 #address-cells = <1>; 1108 #size-cells = <1>; 1109 ranges = <0x0 0xf8044000 0x800>; 1110 status = "disabled"; 1111 1112 uart10: serial@200 { 1113 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1114 reg = <0x200 0x200>; 1115 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1116 dmas = <&dma0 1117 (AT91_XDMAC_DT_MEM_IF(0) | 1118 AT91_XDMAC_DT_PER_IF(1) | 1119 AT91_XDMAC_DT_PERID(20))>, 1120 <&dma0 1121 (AT91_XDMAC_DT_MEM_IF(0) | 1122 AT91_XDMAC_DT_PER_IF(1) | 1123 AT91_XDMAC_DT_PERID(21))>; 1124 dma-names = "tx", "rx"; 1125 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1126 clock-names = "usart"; 1127 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1128 atmel,use-dma-rx; 1129 atmel,use-dma-tx; 1130 atmel,fifo-size = <16>; 1131 status = "disabled"; 1132 }; 1133 1134 i2c10: i2c@600 { 1135 compatible = "microchip,sam9x60-i2c"; 1136 reg = <0x600 0x200>; 1137 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1138 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1139 dmas = <&dma0 1140 (AT91_XDMAC_DT_MEM_IF(0) | 1141 AT91_XDMAC_DT_PER_IF(1) | 1142 AT91_XDMAC_DT_PERID(20))>, 1143 <&dma0 1144 (AT91_XDMAC_DT_MEM_IF(0) | 1145 AT91_XDMAC_DT_PER_IF(1) | 1146 AT91_XDMAC_DT_PERID(21))>; 1147 dma-names = "tx", "rx"; 1148 atmel,fifo-size = <16>; 1149 status = "disabled"; 1150 }; 1151 }; 1152 1153 isi: isi@f8048000 { 1154 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; 1155 reg = <0xf8048000 0x100>; 1156 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; 1157 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 1158 clock-names = "isi_clk"; 1159 status = "disabled"; 1160 port { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 }; 1164 }; 1165 1166 adc: adc@f804c000 { 1167 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; 1168 reg = <0xf804c000 0x100>; 1169 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 1170 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 1171 clock-names = "adc_clk"; 1172 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; 1173 dma-names = "rx"; 1174 atmel,min-sample-rate-hz = <200000>; 1175 atmel,max-sample-rate-hz = <20000000>; 1176 atmel,startup-time-ms = <4>; 1177 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1178 #io-channel-cells = <1>; 1179 status = "disabled"; 1180 }; 1181 1182 sfr: sfr@f8050000 { 1183 compatible = "microchip,sam9x60-sfr", "syscon"; 1184 reg = <0xf8050000 0x100>; 1185 }; 1186 1187 matrix: matrix@ffffde00 { 1188 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1189 reg = <0xffffde00 0x200>; 1190 }; 1191 1192 pmecc: ecc-engine@ffffe000 { 1193 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; 1194 reg = <0xffffe000 0x300>, 1195 <0xffffe600 0x100>; 1196 }; 1197 1198 mpddrc: mpddrc@ffffe800 { 1199 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; 1200 reg = <0xffffe800 0x200>; 1201 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; 1202 clock-names = "ddrck", "mpddr"; 1203 }; 1204 1205 smc: smc@ffffea00 { 1206 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; 1207 reg = <0xffffea00 0x100>; 1208 }; 1209 1210 aic: interrupt-controller@fffff100 { 1211 compatible = "microchip,sam9x60-aic"; 1212 #interrupt-cells = <3>; 1213 interrupt-controller; 1214 reg = <0xfffff100 0x100>; 1215 atmel,external-irqs = <31>; 1216 }; 1217 1218 dbgu: serial@fffff200 { 1219 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 1220 reg = <0xfffff200 0x200>; 1221 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1222 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1223 dmas = <&dma0 1224 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1225 AT91_XDMAC_DT_PERID(28))>, 1226 <&dma0 1227 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1228 AT91_XDMAC_DT_PERID(29))>; 1229 dma-names = "tx", "rx"; 1230 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1231 clock-names = "usart"; 1232 status = "disabled"; 1233 }; 1234 1235 pinctrl: pinctrl@fffff400 { 1236 #address-cells = <1>; 1237 #size-cells = <1>; 1238 compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 1239 ranges = <0xfffff400 0xfffff400 0x800>; 1240 1241 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ 1242 atmel,mux-mask = < 1243 /* A B C */ 1244 0xffffffff 0xffe03fff 0xef00019d /* pioA */ 1245 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ 1246 0xffffffff 0xffffffff 0xf83fffff /* pioC */ 1247 0x003fffff 0x003f8000 0x00000000 /* pioD */ 1248 >; 1249 1250 pioA: gpio@fffff400 { 1251 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1252 reg = <0xfffff400 0x200>; 1253 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1254 #gpio-cells = <2>; 1255 gpio-controller; 1256 interrupt-controller; 1257 #interrupt-cells = <2>; 1258 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1259 }; 1260 1261 pioB: gpio@fffff600 { 1262 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1263 reg = <0xfffff600 0x200>; 1264 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1265 #gpio-cells = <2>; 1266 gpio-controller; 1267 #gpio-lines = <26>; 1268 interrupt-controller; 1269 #interrupt-cells = <2>; 1270 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1271 }; 1272 1273 pioC: gpio@fffff800 { 1274 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1275 reg = <0xfffff800 0x200>; 1276 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1277 #gpio-cells = <2>; 1278 gpio-controller; 1279 interrupt-controller; 1280 #interrupt-cells = <2>; 1281 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1282 }; 1283 1284 pioD: gpio@fffffa00 { 1285 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1286 reg = <0xfffffa00 0x200>; 1287 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1288 #gpio-cells = <2>; 1289 gpio-controller; 1290 #gpio-lines = <22>; 1291 interrupt-controller; 1292 #interrupt-cells = <2>; 1293 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1294 }; 1295 }; 1296 1297 pmc: clock-controller@fffffc00 { 1298 compatible = "microchip,sam9x60-pmc", "syscon"; 1299 reg = <0xfffffc00 0x200>; 1300 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1301 #clock-cells = <2>; 1302 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1303 clock-names = "td_slck", "md_slck", "main_xtal"; 1304 }; 1305 1306 reset_controller: reset-controller@fffffe00 { 1307 compatible = "microchip,sam9x60-rstc"; 1308 reg = <0xfffffe00 0x10>; 1309 clocks = <&clk32k 0>; 1310 }; 1311 1312 shutdown_controller: poweroff@fffffe10 { 1313 compatible = "microchip,sam9x60-shdwc"; 1314 reg = <0xfffffe10 0x10>; 1315 clocks = <&clk32k 0>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 atmel,wakeup-rtc-timer; 1319 atmel,wakeup-rtt-timer; 1320 status = "disabled"; 1321 }; 1322 1323 rtt: rtc@fffffe20 { 1324 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 1325 reg = <0xfffffe20 0x20>; 1326 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1327 clocks = <&clk32k 1>; 1328 }; 1329 1330 pit: timer@fffffe40 { 1331 compatible = "atmel,at91sam9260-pit"; 1332 reg = <0xfffffe40 0x10>; 1333 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1334 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 1335 }; 1336 1337 clk32k: clock-controller@fffffe50 { 1338 compatible = "microchip,sam9x60-sckc"; 1339 reg = <0xfffffe50 0x4>; 1340 clocks = <&slow_xtal>; 1341 #clock-cells = <1>; 1342 }; 1343 1344 gpbr: syscon@fffffe60 { 1345 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1346 reg = <0xfffffe60 0x10>; 1347 }; 1348 1349 rtc: rtc@fffffea8 { 1350 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; 1351 reg = <0xfffffea8 0x100>; 1352 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1353 clocks = <&clk32k 1>; 1354 }; 1355 1356 watchdog: watchdog@ffffff80 { 1357 compatible = "microchip,sam9x60-wdt"; 1358 reg = <0xffffff80 0x24>; 1359 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1360 clocks = <&clk32k 0>; 1361 status = "disabled"; 1362 }; 1363 }; 1364 }; 1365}; 1366