1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Marvell Technology Group Ltd. 4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 5 */ 6 7#include <dt-bindings/clock/marvell,pxa910.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 aliases { 14 serial0 = &uart1; 15 serial1 = &uart2; 16 serial2 = &uart3; 17 i2c0 = &twsi1; 18 i2c1 = &twsi2; 19 }; 20 21 soc { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 compatible = "simple-bus"; 25 interrupt-parent = <&intc>; 26 ranges; 27 28 L2: l2-cache { 29 compatible = "marvell,tauros2-cache"; 30 marvell,tauros2-cache-features = <0x3>; 31 }; 32 33 axi@d4200000 { /* AXI */ 34 compatible = "mrvl,axi-bus", "simple-bus"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 reg = <0xd4200000 0x00200000>; 38 ranges; 39 40 intc: interrupt-controller@d4282000 { 41 compatible = "mrvl,mmp-intc"; 42 interrupt-controller; 43 #interrupt-cells = <1>; 44 reg = <0xd4282000 0x1000>; 45 mrvl,intc-nr-irqs = <64>; 46 }; 47 48 }; 49 50 apb@d4000000 { /* APB */ 51 compatible = "mrvl,apb-bus", "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 reg = <0xd4000000 0x00200000>; 55 ranges; 56 57 timer0: timer@d4014000 { 58 compatible = "mrvl,mmp-timer"; 59 reg = <0xd4014000 0x100>; 60 interrupts = <13>; 61 }; 62 63 timer1: timer@d4016000 { 64 compatible = "mrvl,mmp-timer"; 65 reg = <0xd4016000 0x100>; 66 interrupts = <29>; 67 status = "disabled"; 68 }; 69 70 uart1: serial@d4017000 { 71 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 72 reg = <0xd4017000 0x1000>; 73 reg-shift = <2>; 74 interrupts = <27>; 75 clocks = <&soc_clocks PXA910_CLK_UART0>; 76 resets = <&soc_clocks PXA910_CLK_UART0>; 77 status = "disabled"; 78 }; 79 80 uart2: serial@d4018000 { 81 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 82 reg = <0xd4018000 0x1000>; 83 reg-shift = <2>; 84 interrupts = <28>; 85 clocks = <&soc_clocks PXA910_CLK_UART1>; 86 resets = <&soc_clocks PXA910_CLK_UART1>; 87 status = "disabled"; 88 }; 89 90 uart3: serial@d4036000 { 91 compatible = "mrvl,mmp-uart", "intel,xscale-uart"; 92 reg = <0xd4036000 0x1000>; 93 reg-shift = <2>; 94 interrupts = <59>; 95 clocks = <&soc_clocks PXA910_CLK_UART2>; 96 resets = <&soc_clocks PXA910_CLK_UART2>; 97 status = "disabled"; 98 }; 99 100 gpio@d4019000 { 101 compatible = "marvell,mmp-gpio"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 reg = <0xd4019000 0x1000>; 105 gpio-controller; 106 #gpio-cells = <2>; 107 interrupts = <49>; 108 interrupt-names = "gpio_mux"; 109 clocks = <&soc_clocks PXA910_CLK_GPIO>; 110 resets = <&soc_clocks PXA910_CLK_GPIO>; 111 interrupt-controller; 112 #interrupt-cells = <2>; 113 ranges; 114 115 gcb0: gpio@d4019000 { 116 reg = <0xd4019000 0x4>; 117 }; 118 119 gcb1: gpio@d4019004 { 120 reg = <0xd4019004 0x4>; 121 }; 122 123 gcb2: gpio@d4019008 { 124 reg = <0xd4019008 0x4>; 125 }; 126 127 gcb3: gpio@d4019100 { 128 reg = <0xd4019100 0x4>; 129 }; 130 }; 131 132 twsi1: i2c@d4011000 { 133 compatible = "mrvl,mmp-twsi"; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 reg = <0xd4011000 0x1000>; 137 interrupts = <7>; 138 clocks = <&soc_clocks PXA910_CLK_TWSI0>; 139 resets = <&soc_clocks PXA910_CLK_TWSI0>; 140 mrvl,i2c-fast-mode; 141 status = "disabled"; 142 }; 143 144 twsi2: i2c@d4037000 { 145 compatible = "mrvl,mmp-twsi"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 reg = <0xd4037000 0x1000>; 149 interrupts = <54>; 150 clocks = <&soc_clocks PXA910_CLK_TWSI1>; 151 resets = <&soc_clocks PXA910_CLK_TWSI1>; 152 status = "disabled"; 153 }; 154 155 rtc: rtc@d4010000 { 156 compatible = "mrvl,mmp-rtc"; 157 reg = <0xd4010000 0x1000>; 158 interrupts = <5>, <6>; 159 interrupt-names = "rtc 1Hz", "rtc alarm"; 160 clocks = <&soc_clocks PXA910_CLK_RTC>; 161 resets = <&soc_clocks PXA910_CLK_RTC>; 162 status = "disabled"; 163 }; 164 }; 165 166 soc_clocks: clocks { 167 compatible = "marvell,pxa910-clock"; 168 reg = <0xd4050000 0x1000>, 169 <0xd4282800 0x400>, 170 <0xd4015000 0x1000>, 171 <0xd403b000 0x1000>; 172 reg-names = "mpmu", "apmu", "apbc", "apbcp"; 173 #clock-cells = <1>; 174 #reset-cells = <1>; 175 }; 176 }; 177}; 178