1// SPDX-License-Identifier: GPL-2.0 2/* The pxa3xx skeleton simply augments the 2xx version */ 3#include "pxa2xx.dtsi" 4 5#define MFP_PIN_PXA300(gpio) \ 6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ 9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 10 0) 11#define MFP_PIN_PXA300_2(gpio) \ 12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 14 0) 15 16#define MFP_PIN_PXA310(gpio) \ 17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ 20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ 21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 22 (gpio <= 262) ? 0 : \ 23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ 24 0) 25#define MFP_PIN_PXA310_2(gpio) \ 26 ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 27 (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 28 (gpio <= 10) ? (0x52c + 4 * gpio) : \ 29 0) 30 31#define MFP_PIN_PXA320(gpio) \ 32 ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ 33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ 34 (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ 35 (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ 36 (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ 37 (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ 38 (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ 39 (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ 40 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 41 0) 42#define MFP_PIN_PXA320_2(gpio) \ 43 ((gpio <= 3) ? (0x674 + 4 * gpio) : \ 44 (gpio <= 5) ? (0x284 + 4 * gpio) : \ 45 0) 46 47/* 48 * MFP Alternate functions for pins having a gpio. 49 * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > 50 */ 51#define MFP_AF0 (0 << 0) 52#define MFP_AF1 (1 << 0) 53#define MFP_AF2 (2 << 0) 54#define MFP_AF3 (3 << 0) 55#define MFP_AF4 (4 << 0) 56#define MFP_AF5 (5 << 0) 57#define MFP_AF6 (6 << 0) 58 59/* 60 * MFP drive strength functions for pins. 61 * Example of use: pinctrl-single,drive-strength = MFP_DS03X; 62 */ 63#define MFP_DSMSK (0x7 << 10) 64#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > 65#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > 66#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > 67#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > 68#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > 69#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > 70#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > 71#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > 72 73/* 74 * MFP bias pull mode for pins. 75 * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP; 76 */ 77#define MPF_PULL_MSK (0x7 << 13) 78#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK > 79#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK > 80 81/* 82 * MFP low power mode for pins. 83 * Example of use: 84 * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); 85 * 86 * Table that determines the low power modes outputs, with actual settings 87 * used in parentheses for don't-care values. Except for the float output, 88 * the configured driven and pulled levels match, so if there is a need for 89 * non-LPM pulled output, the same configuration could probably be used. 90 * 91 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel 92 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) 93 * 94 * Input 0 X(0) X(0) X(0) 0 95 * Drive 0 0 0 0 X(1) 0 96 * Drive 1 0 1 X(1) 0 0 97 * Pull hi (1) 1 X(1) 1 0 0 98 * Pull lo (0) 1 X(0) 0 1 0 99 * Z (float) 1 X(0) 0 0 0 100 */ 101#define MFP_LPM(x) < (x) MFP_LPM_MSK > 102 103#define MFP_LPM_MSK 0xe1f0 104#define MFP_LPM_INPUT 0x0000 105#define MFP_LPM_DRIVE_LOW 0x2000 106#define MFP_LPM_DRIVE_HIGH 0x4100 107#define MFP_LPM_PULL_LOW 0x2080 108#define MFP_LPM_PULL_HIGH 0x4180 109#define MFP_LPM_FLOAT 0x0080 110 111#define MFP_LPM_EDGE_NONE 0x0000 112#define MFP_LPM_EDGE_RISE 0x0010 113#define MFP_LPM_EDGE_FALL 0x0020 114#define MFP_LPM_EDGE_BOTH 0x0030 115 116/ { 117 model = "Marvell PXA3xx familiy SoC"; 118 compatible = "marvell,pxa3xx"; 119 120 pxabus { 121 pdma: dma-controller@40000000 { 122 compatible = "marvell,pdma-1.0"; 123 reg = <0x40000000 0x10000>; 124 interrupts = <25>; 125 #dma-cells = <2>; 126 /* For backwards compatibility: */ 127 #dma-channels = <32>; 128 dma-channels = <32>; 129 #dma-requests = <100>; 130 dma-requests = <100>; 131 status = "okay"; 132 }; 133 134 pwri2c: i2c@40f500c0 { 135 compatible = "mrvl,pwri2c"; 136 reg = <0x40f500c0 0x30>; 137 interrupts = <6>; 138 clocks = <&clks CLK_PWRI2C>; 139 #address-cells = <0x1>; 140 #size-cells = <0>; 141 status = "disabled"; 142 }; 143 144 nand_controller: nand-controller@43100000 { 145 compatible = "marvell,pxa3xx-nand-controller"; 146 reg = <0x43100000 90>; 147 interrupts = <45>; 148 clocks = <&clks CLK_NAND>; 149 clock-names = "core"; 150 dmas = <&pdma 97 3>; 151 dma-names = "data"; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 status = "disabled"; 155 }; 156 157 pxairq: interrupt-controller@40d00000 { 158 marvell,intc-priority; 159 marvell,intc-nr-irqs = <56>; 160 }; 161 162 pinctrl: pinctrl@40e10000 { 163 compatible = "pinconf-single"; 164 reg = <0x40e10000 0xffff>; 165 #pinctrl-cells = <1>; 166 pinctrl-single,register-width = <32>; 167 pinctrl-single,function-mask = <0x7>; 168 }; 169 170 gpio: gpio@40e00000 { 171 compatible = "intel,pxa3xx-gpio"; 172 reg = <0x40e00000 0x10000>; 173 clocks = <&clks CLK_GPIO>; 174 gpio-ranges = <&pinctrl 0 0 128>; 175 interrupt-names = "gpio0", "gpio1", "gpio_mux"; 176 interrupts = <8>, <9>, <10>; 177 gpio-controller; 178 #gpio-cells = <0x2>; 179 interrupt-controller; 180 #interrupt-cells = <0x2>; 181 }; 182 183 mmc0: mmc@41100000 { 184 compatible = "marvell,pxa-mmc"; 185 reg = <0x41100000 0x1000>; 186 interrupts = <23>; 187 clocks = <&clks CLK_MMC1>; 188 dmas = <&pdma 21 3 189 &pdma 22 3>; 190 dma-names = "rx", "tx"; 191 status = "disabled"; 192 }; 193 194 mmc1: mmc@42000000 { 195 compatible = "marvell,pxa-mmc"; 196 reg = <0x42000000 0x1000>; 197 interrupts = <41>; 198 clocks = <&clks CLK_MMC2>; 199 dmas = <&pdma 93 3 200 &pdma 94 3>; 201 dma-names = "rx", "tx"; 202 status = "disabled"; 203 }; 204 205 mmc2: mmc@42500000 { 206 compatible = "marvell,pxa-mmc"; 207 reg = <0x42500000 0x1000>; 208 interrupts = <55>; 209 clocks = <&clks CLK_MMC3>; 210 dmas = <&pdma 46 3 211 &pdma 47 3>; 212 dma-names = "rx", "tx"; 213 status = "disabled"; 214 }; 215 216 usb0: usb@4c000000 { 217 compatible = "marvell,pxa-ohci"; 218 reg = <0x4c000000 0x10000>; 219 interrupts = <3>; 220 clocks = <&clks CLK_USBH>; 221 status = "disabled"; 222 }; 223 224 pwm0: pwm@40b00000 { 225 compatible = "marvell,pxa270-pwm"; 226 reg = <0x40b00000 0x10>; 227 #pwm-cells = <1>; 228 clocks = <&clks CLK_PWM0>; 229 status = "disabled"; 230 }; 231 232 pwm1: pwm@40b00010 { 233 compatible = "marvell,pxa270-pwm"; 234 reg = <0x40b00010 0x10>; 235 #pwm-cells = <1>; 236 clocks = <&clks CLK_PWM1>; 237 status = "disabled"; 238 }; 239 240 pwm2: pwm@40c00000 { 241 compatible = "marvell,pxa270-pwm"; 242 reg = <0x40c00000 0x10>; 243 #pwm-cells = <1>; 244 clocks = <&clks CLK_PWM0>; 245 status = "disabled"; 246 }; 247 248 pwm3: pwm@40c00010 { 249 compatible = "marvell,pxa270-pwm"; 250 reg = <0x40c00010 0x10>; 251 #pwm-cells = <1>; 252 clocks = <&clks CLK_PWM1>; 253 status = "disabled"; 254 }; 255 256 ssp1: ssp@41000000 { 257 compatible = "mrvl,pxa3xx-ssp"; 258 reg = <0x41000000 0x40>; 259 interrupts = <24>; 260 clocks = <&clks CLK_SSP1>; 261 status = "disabled"; 262 }; 263 264 ssp2: ssp@41700000 { 265 compatible = "mrvl,pxa3xx-ssp"; 266 reg = <0x41700000 0x40>; 267 interrupts = <16>; 268 clocks = <&clks CLK_SSP2>; 269 status = "disabled"; 270 }; 271 272 ssp3: ssp@41900000 { 273 compatible = "mrvl,pxa3xx-ssp"; 274 reg = <0x41900000 0x40>; 275 interrupts = <0>; 276 clocks = <&clks CLK_SSP3>; 277 status = "disabled"; 278 }; 279 280 ssp4: ssp@41a00000 { 281 compatible = "mrvl,pxa3xx-ssp"; 282 reg = <0x41a00000 0x40>; 283 interrupts = <13>; 284 clocks = <&clks CLK_SSP4>; 285 status = "disabled"; 286 }; 287 288 timer@40a00000 { 289 compatible = "marvell,pxa-timer"; 290 reg = <0x40a00000 0x20>; 291 interrupts = <26>; 292 clocks = <&clks CLK_OSTIMER>; 293 status = "okay"; 294 }; 295 296 gcu: display-controller@54000000 { 297 compatible = "marvell,pxa300-gcu"; 298 reg = <0x54000000 0x1000>; 299 interrupts = <39>; 300 clocks = <&clks CLK_PXA300_GCU>; 301 status = "disabled"; 302 }; 303 }; 304 305 clocks { 306 /* 307 * The muxing of external clocks/internal dividers for osc* clock 308 * sources has been hidden under the carpet by now. 309 */ 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 clks: clocks { 315 compatible = "marvell,pxa300-clocks"; 316 #clock-cells = <1>; 317 status = "okay"; 318 }; 319 }; 320}; 321