1// SPDX-License-Identifier: GPL-2.0 2/* The pxa3xx skeleton simply augments the 2xx version */ 3#include "pxa2xx.dtsi" 4#include "dt-bindings/clock/pxa-clock.h" 5 6/ { 7 model = "Marvell PXA27x familiy SoC"; 8 compatible = "marvell,pxa27x"; 9 10 pxabus { 11 pdma: dma-controller@40000000 { 12 compatible = "marvell,pdma-1.0"; 13 reg = <0x40000000 0x10000>; 14 interrupts = <25>; 15 #dma-cells = <2>; 16 /* For backwards compatibility: */ 17 #dma-channels = <32>; 18 dma-channels = <32>; 19 #dma-requests = <75>; 20 dma-requests = <75>; 21 status = "okay"; 22 }; 23 24 pxairq: interrupt-controller@40d00000 { 25 marvell,intc-priority; 26 marvell,intc-nr-irqs = <34>; 27 }; 28 29 pinctrl: pinctrl@40e00000 { 30 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 31 0x40f00020 0x10>; 32 compatible = "marvell,pxa27x-pinctrl"; 33 }; 34 35 gpio: gpio@40e00000 { 36 compatible = "intel,pxa27x-gpio"; 37 gpio-ranges = <&pinctrl 0 0 128>; 38 clocks = <&clks CLK_NONE>; 39 }; 40 41 usb0: usb@4c000000 { 42 compatible = "marvell,pxa-ohci"; 43 reg = <0x4c000000 0x10000>; 44 interrupts = <3>; 45 clocks = <&clks CLK_USBHOST>; 46 status = "disabled"; 47 }; 48 49 pwm0: pwm@40b00000 { 50 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 51 reg = <0x40b00000 0x10>; 52 #pwm-cells = <1>; 53 clocks = <&clks CLK_PWM0>; 54 }; 55 56 pwm1: pwm@40b00010 { 57 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 58 reg = <0x40b00010 0x10>; 59 #pwm-cells = <1>; 60 clocks = <&clks CLK_PWM1>; 61 }; 62 63 pwm2: pwm@40c00000 { 64 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 65 reg = <0x40c00000 0x10>; 66 #pwm-cells = <1>; 67 clocks = <&clks CLK_PWM0>; 68 }; 69 70 pwm3: pwm@40c00010 { 71 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 72 reg = <0x40c00010 0x10>; 73 #pwm-cells = <1>; 74 clocks = <&clks CLK_PWM1>; 75 }; 76 77 pwri2c: i2c@40f00180 { 78 compatible = "mrvl,pxa-i2c"; 79 reg = <0x40f00180 0x24>; 80 interrupts = <6>; 81 clocks = <&clks CLK_PWRI2C>; 82 #address-cells = <0x1>; 83 #size-cells = <0>; 84 status = "disabled"; 85 }; 86 87 pxa27x_udc: udc@40600000 { 88 compatible = "marvell,pxa270-udc"; 89 reg = <0x40600000 0x10000>; 90 interrupts = <11>; 91 clocks = <&clks CLK_USB>; 92 status = "disabled"; 93 }; 94 95 keypad: keypad@41500000 { 96 compatible = "marvell,pxa27x-keypad"; 97 reg = <0x41500000 0x4c>; 98 interrupts = <4>; 99 clocks = <&clks CLK_KEYPAD>; 100 status = "disabled"; 101 }; 102 103 pxa_camera: imaging@50000000 { 104 compatible = "marvell,pxa270-qci"; 105 reg = <0x50000000 0x1000>; 106 interrupts = <33>; 107 dmas = <&pdma 68 0 /* Y channel */ 108 &pdma 69 0 /* U channel */ 109 &pdma 70 0>; /* V channel */ 110 dma-names = "CI_Y", "CI_U", "CI_V"; 111 112 clocks = <&clks CLK_CAMERA>; 113 clock-names = "ciclk"; 114 clock-frequency = <5000000>; 115 clock-output-names = "qci_mclk"; 116 117 status = "disabled"; 118 }; 119 120 rtc@40900000 { 121 clocks = <&clks CLK_OSC32k768>; 122 }; 123 }; 124 125 clocks { 126 /* 127 * The muxing of external clocks/internal dividers for osc* clock 128 * sources has been hidden under the carpet by now. 129 */ 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges; 133 134 clks: pxa2xx_clks@41300004 { 135 compatible = "marvell,pxa270-clocks"; 136 #clock-cells = <1>; 137 status = "okay"; 138 }; 139 }; 140 141 timer@40a00000 { 142 compatible = "marvell,pxa-timer"; 143 reg = <0x40a00000 0x20>; 144 interrupts = <26>; 145 clocks = <&clks CLK_OSTIMER>; 146 status = "okay"; 147 }; 148 149 pxa270_opp_table: opp_table0 { 150 compatible = "operating-points-v2"; 151 152 opp-104000000 { 153 opp-hz = /bits/ 64 <104000000>; 154 opp-microvolt = <900000 900000 1705000>; 155 clock-latency-ns = <20>; 156 }; 157 opp-156000000 { 158 opp-hz = /bits/ 64 <156000000>; 159 opp-microvolt = <1000000 1000000 1705000>; 160 clock-latency-ns = <20>; 161 }; 162 opp-208000000 { 163 opp-hz = /bits/ 64 <208000000>; 164 opp-microvolt = <1180000 1180000 1705000>; 165 clock-latency-ns = <20>; 166 }; 167 opp-312000000 { 168 opp-hz = /bits/ 64 <312000000>; 169 opp-microvolt = <1250000 1250000 1705000>; 170 clock-latency-ns = <20>; 171 }; 172 opp-416000000 { 173 opp-hz = /bits/ 64 <416000000>; 174 opp-microvolt = <1350000 1350000 1705000>; 175 clock-latency-ns = <20>; 176 }; 177 opp-520000000 { 178 opp-hz = /bits/ 64 <520000000>; 179 opp-microvolt = <1450000 1450000 1705000>; 180 clock-latency-ns = <20>; 181 }; 182 opp-624000000 { 183 opp-hz = /bits/ 64 <624000000>; 184 opp-microvolt = <1550000 1550000 1705000>; 185 clock-latency-ns = <20>; 186 }; 187 }; 188}; 189