1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (c) 2013-2014 Linaro Ltd. 4*724ba675SRob Herring * Copyright (c) 2013-2014 HiSilicon Limited. 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring#include "hisi-x5hd2.dtsi" 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Hisilicon HIX5HD2 Development Board"; 12*724ba675SRob Herring compatible = "hisilicon,hix5hd2"; 13*724ba675SRob Herring 14*724ba675SRob Herring chosen { 15*724ba675SRob Herring stdout-path = "serial0:115200n8"; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring cpus { 19*724ba675SRob Herring #address-cells = <1>; 20*724ba675SRob Herring #size-cells = <0>; 21*724ba675SRob Herring enable-method = "hisilicon,hix5hd2-smp"; 22*724ba675SRob Herring 23*724ba675SRob Herring cpu@0 { 24*724ba675SRob Herring compatible = "arm,cortex-a9"; 25*724ba675SRob Herring device_type = "cpu"; 26*724ba675SRob Herring reg = <0>; 27*724ba675SRob Herring next-level-cache = <&l2>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring 30*724ba675SRob Herring cpu@1 { 31*724ba675SRob Herring compatible = "arm,cortex-a9"; 32*724ba675SRob Herring device_type = "cpu"; 33*724ba675SRob Herring reg = <1>; 34*724ba675SRob Herring next-level-cache = <&l2>; 35*724ba675SRob Herring }; 36*724ba675SRob Herring }; 37*724ba675SRob Herring 38*724ba675SRob Herring memory@0 { 39*724ba675SRob Herring device_type = "memory"; 40*724ba675SRob Herring reg = <0x00000000 0x80000000>; 41*724ba675SRob Herring }; 42*724ba675SRob Herring}; 43*724ba675SRob Herring 44*724ba675SRob Herring&timer0 { 45*724ba675SRob Herring status = "okay"; 46*724ba675SRob Herring}; 47*724ba675SRob Herring 48*724ba675SRob Herring&uart0 { 49*724ba675SRob Herring status = "okay"; 50*724ba675SRob Herring}; 51*724ba675SRob Herring 52*724ba675SRob Herring&gmac0 { 53*724ba675SRob Herring #address-cells = <1>; 54*724ba675SRob Herring #size-cells = <0>; 55*724ba675SRob Herring phy-handle = <&phy2>; 56*724ba675SRob Herring phy-mode = "mii"; 57*724ba675SRob Herring /* Placeholder, overwritten by bootloader */ 58*724ba675SRob Herring mac-address = [00 00 00 00 00 00]; 59*724ba675SRob Herring status = "okay"; 60*724ba675SRob Herring 61*724ba675SRob Herring phy2: ethernet-phy@2 { 62*724ba675SRob Herring reg = <2>; 63*724ba675SRob Herring }; 64*724ba675SRob Herring}; 65*724ba675SRob Herring 66*724ba675SRob Herring&gmac1 { 67*724ba675SRob Herring #address-cells = <1>; 68*724ba675SRob Herring #size-cells = <0>; 69*724ba675SRob Herring phy-handle = <&phy1>; 70*724ba675SRob Herring phy-mode = "rgmii"; 71*724ba675SRob Herring /* Placeholder, overwritten by bootloader */ 72*724ba675SRob Herring mac-address = [00 00 00 00 00 00]; 73*724ba675SRob Herring status = "okay"; 74*724ba675SRob Herring 75*724ba675SRob Herring phy1: ethernet-phy@1 { 76*724ba675SRob Herring reg = <1>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring}; 79*724ba675SRob Herring 80*724ba675SRob Herring&ahci { 81*724ba675SRob Herring phys = <&sata_phy>; 82*724ba675SRob Herring phy-names = "sata-phy"; 83*724ba675SRob Herring}; 84