1/*
2 *  BSD LICENSE
3 *
4 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
5 *
6 *  Redistribution and use in source and binary forms, with or without
7 *  modification, are permitted provided that the following conditions
8 *  are met:
9 *
10 *    * Redistributions of source code must retain the above copyright
11 *      notice, this list of conditions and the following disclaimer.
12 *    * Redistributions in binary form must reproduce the above copyright
13 *      notice, this list of conditions and the following disclaimer in
14 *      the documentation and/or other materials provided with the
15 *      distribution.
16 *    * Neither the name of Broadcom Corporation nor the names of its
17 *      contributors may be used to endorse or promote products derived
18 *      from this software without specific prior written permission.
19 *
20 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34#include <dt-bindings/interrupt-controller/irq.h>
35#include <dt-bindings/clock/bcm-nsp.h>
36
37/ {
38	#address-cells = <1>;
39	#size-cells = <1>;
40	compatible = "brcm,nsp";
41	model = "Broadcom Northstar Plus SoC";
42	interrupt-parent = <&gic>;
43
44	aliases {
45		serial0 = &uart0;
46		serial1 = &uart1;
47		ethernet0 = &amac0;
48		ethernet1 = &amac1;
49		ethernet2 = &amac2;
50	};
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cpu0: cpu@0 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a9";
59			next-level-cache = <&L2>;
60			reg = <0x0>;
61		};
62
63		cpu1: cpu@1 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a9";
66			next-level-cache = <&L2>;
67			enable-method = "brcm,bcm-nsp-smp";
68			secondary-boot-reg = <0xffff0fec>;
69			reg = <0x1>;
70		};
71	};
72
73	pmu {
74		compatible = "arm,cortex-a9-pmu";
75		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
76			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
77		interrupt-affinity = <&cpu0>, <&cpu1>;
78	};
79
80	mpcore-bus@19000000 {
81		compatible = "simple-bus";
82		ranges = <0x00000000 0x19000000 0x00023000>;
83		#address-cells = <1>;
84		#size-cells = <1>;
85
86		a9pll: arm_clk@0 {
87			#clock-cells = <0>;
88			compatible = "brcm,nsp-armpll";
89			clocks = <&osc>;
90			reg = <0x00000 0x1000>;
91		};
92
93		timer@20200 {
94			compatible = "arm,cortex-a9-global-timer";
95			reg = <0x20200 0x100>;
96			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
97			clocks = <&periph_clk>;
98		};
99
100		twd-timer@20600 {
101			compatible = "arm,cortex-a9-twd-timer";
102			reg = <0x20600 0x20>;
103			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
104						  IRQ_TYPE_EDGE_RISING)>;
105			clocks = <&periph_clk>;
106		};
107
108		twd-watchdog@20620 {
109			compatible = "arm,cortex-a9-twd-wdt";
110			reg = <0x20620 0x20>;
111			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
112						  IRQ_TYPE_LEVEL_HIGH)>;
113			clocks = <&periph_clk>;
114		};
115
116		gic: interrupt-controller@21000 {
117			compatible = "arm,cortex-a9-gic";
118			#interrupt-cells = <3>;
119			#address-cells = <0>;
120			interrupt-controller;
121			reg = <0x21000 0x1000>,
122			      <0x20100 0x100>;
123		};
124
125		L2: cache-controller@22000 {
126			compatible = "arm,pl310-cache";
127			reg = <0x22000 0x1000>;
128			cache-unified;
129			cache-level = <2>;
130		};
131	};
132
133	clocks {
134		#address-cells = <1>;
135		#size-cells = <1>;
136		ranges;
137
138		osc: oscillator {
139			#clock-cells = <0>;
140			compatible = "fixed-clock";
141			clock-frequency = <25000000>;
142		};
143
144		iprocmed: iprocmed {
145			#clock-cells = <0>;
146			compatible = "fixed-factor-clock";
147			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
148			clock-div = <2>;
149			clock-mult = <1>;
150		};
151
152		iprocslow: iprocslow {
153			#clock-cells = <0>;
154			compatible = "fixed-factor-clock";
155			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
156			clock-div = <4>;
157			clock-mult = <1>;
158		};
159
160		periph_clk: periph_clk {
161			#clock-cells = <0>;
162			compatible = "fixed-factor-clock";
163			clocks = <&a9pll>;
164			clock-div = <2>;
165			clock-mult = <1>;
166		};
167	};
168
169	axi: axi@18000000 {
170		compatible = "simple-bus";
171		ranges = <0x00000000 0x18000000 0x0011c40c>;
172		#address-cells = <1>;
173		#size-cells = <1>;
174
175		gpioa: gpio@20 {
176			compatible = "brcm,nsp-gpio-a";
177			reg = <0x0020 0x70>,
178			      <0x3f1c4 0x1c>;
179			#gpio-cells = <2>;
180			gpio-controller;
181			ngpios = <32>;
182			interrupt-controller;
183			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
184			gpio-ranges = <&pinctrl 0 0 32>;
185		};
186
187		uart0: serial@300 {
188			compatible = "ns16550a";
189			reg = <0x0300 0x100>;
190			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&osc>;
192			status = "disabled";
193		};
194
195		uart1: serial@400 {
196			compatible = "ns16550a";
197			reg = <0x0400 0x100>;
198			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
199			clocks = <&osc>;
200			status = "disabled";
201		};
202
203		dma: dma@20000 {
204			compatible = "arm,pl330", "arm,primecell";
205			reg = <0x20000 0x1000>;
206			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
207				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
208				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
209				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
210				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
211				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
212				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
214				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
215			clocks = <&iprocslow>;
216			clock-names = "apb_pclk";
217			#dma-cells = <1>;
218			dma-coherent;
219			status = "disabled";
220		};
221
222		sdio: mmc@21000 {
223			compatible = "brcm,sdhci-iproc-cygnus";
224			reg = <0x21000 0x100>;
225			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
226			sdhci,auto-cmd12;
227			clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
228			dma-coherent;
229			status = "disabled";
230		};
231
232		amac0: ethernet@22000 {
233			compatible = "brcm,nsp-amac";
234			reg = <0x022000 0x1000>,
235			      <0x110000 0x1000>;
236			reg-names = "amac_base", "idm_base";
237			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
238			dma-coherent;
239			status = "disabled";
240		};
241
242		amac1: ethernet@23000 {
243			compatible = "brcm,nsp-amac";
244			reg = <0x023000 0x1000>,
245			      <0x111000 0x1000>;
246			reg-names = "amac_base", "idm_base";
247			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
248			dma-coherent;
249			status = "disabled";
250		};
251
252		amac2: ethernet@24000 {
253			compatible = "brcm,nsp-amac";
254			reg = <0x024000 0x1000>,
255			      <0x112000 0x1000>;
256			reg-names = "amac_base", "idm_base";
257			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
258			dma-coherent;
259			status = "disabled";
260		};
261
262		mailbox: mailbox@25c00 {
263			compatible = "brcm,iproc-fa2-mbox";
264			reg = <0x25c00 0x400>;
265			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
266			#mbox-cells = <1>;
267			brcm,rx-status-len = <32>;
268			brcm,use-bcm-hdr;
269			dma-coherent;
270		};
271
272		nand_controller: nand-controller@26000 {
273			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
274			reg = <0x026000 0x600>,
275			      <0x11b408 0x600>,
276			      <0x026f00 0x20>;
277			reg-names = "nand", "iproc-idm", "iproc-ext";
278			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
279
280			#address-cells = <1>;
281			#size-cells = <0>;
282
283			brcm,nand-has-wp;
284		};
285
286		qspi: spi@27200 {
287			compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
288			reg = <0x027200 0x184>,
289			      <0x027000 0x124>,
290			      <0x11c408 0x004>,
291			      <0x0273a0 0x01c>;
292			reg-names = "mspi", "bspi", "intr_regs",
293				    "intr_status_reg";
294			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
296				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
297				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
298				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
299				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
300				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
301			interrupt-names = "spi_lr_fullness_reached",
302					  "spi_lr_session_aborted",
303					  "spi_lr_impatient",
304					  "spi_lr_session_done",
305					  "spi_lr_overhead",
306					  "mspi_done",
307					  "mspi_halted";
308			clocks = <&iprocmed>;
309			clock-names = "iprocmed";
310			num-cs = <2>;
311			#address-cells = <1>;
312			#size-cells = <0>;
313			status = "disabled";
314		};
315
316		xhci: usb@29000 {
317			compatible = "generic-xhci";
318			reg = <0x29000 0x1000>;
319			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
320			phys = <&usb3_phy>;
321			phy-names = "usb3-phy";
322			dma-coherent;
323			status = "disabled";
324		};
325
326		ehci0: usb@2a000 {
327			compatible = "generic-ehci";
328			reg = <0x2a000 0x100>;
329			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
330			dma-coherent;
331			status = "disabled";
332		};
333
334		ohci0: usb@2b000 {
335			compatible = "generic-ohci";
336			reg = <0x2b000 0x100>;
337			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
338			dma-coherent;
339			status = "disabled";
340		};
341
342		crypto@2f000 {
343			compatible = "brcm,spum-nsp-crypto";
344			reg = <0x2f000 0x900>;
345			mboxes = <&mailbox 0>;
346		};
347
348		gpiob: gpio@30000 {
349			compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
350			reg = <0x30000 0x50>;
351			#gpio-cells = <2>;
352			gpio-controller;
353			ngpios = <4>;
354			interrupt-controller;
355			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
356		};
357
358		pwm: pwm@31000 {
359			compatible = "brcm,iproc-pwm";
360			reg = <0x31000 0x28>;
361			clocks = <&osc>;
362			#pwm-cells = <3>;
363			status = "disabled";
364		};
365
366		mdio: mdio@32000 {
367			compatible = "brcm,iproc-mdio";
368			reg = <0x32000 0x8>;
369			#size-cells = <0>;
370			#address-cells = <1>;
371		};
372
373		mdio-mux@32000 {
374			compatible = "mdio-mux-mmioreg", "mdio-mux";
375			reg = <0x32000 0x4>;
376			mux-mask = <0x200>;
377			#address-cells = <1>;
378			#size-cells = <0>;
379			mdio-parent-bus = <&mdio>;
380
381			mdio_int: mdio@0 {
382				reg = <0x0>;
383				#address-cells = <1>;
384				#size-cells = <0>;
385
386				usb3_phy: usb3-phy@10 {
387					compatible = "brcm,ns-bx-usb3-phy";
388					reg = <0x10>;
389					usb3-dmp-syscon = <&usb3_dmp>;
390					#phy-cells = <0>;
391					status = "disabled";
392				};
393			};
394
395			mdio_ext: mdio@200 {
396				reg = <0x200>;
397				#address-cells = <1>;
398				#size-cells = <0>;
399			};
400		};
401
402		rng: rng@33000 {
403			compatible = "brcm,bcm-nsp-rng";
404			reg = <0x33000 0x14>;
405		};
406
407		ccbtimer0: timer@34000 {
408			compatible = "arm,sp804", "arm,primecell";
409			reg = <0x34000 0x1000>;
410			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
411				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
412			clocks = <&iprocslow>;
413			clock-names = "apb_pclk";
414		};
415
416		ccbtimer1: timer@35000 {
417			compatible = "arm,sp804", "arm,primecell";
418			reg = <0x35000 0x1000>;
419			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
420				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
421			clocks = <&iprocslow>;
422			clock-names = "apb_pclk";
423		};
424
425		srab: ethernet-switch@36000 {
426			compatible = "brcm,nsp-srab";
427			reg = <0x36000 0x1000>,
428			      <0x3f308 0x8>,
429			      <0x3f410 0xc>;
430			reg-names = "srab", "mux_config", "sgmii_config";
431			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
432				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
433				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
434				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
435				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
436				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
437				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
438				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
439				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
440				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
441				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
442				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
443				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
444			interrupt-names = "link_state_p0",
445					  "link_state_p1",
446					  "link_state_p2",
447					  "link_state_p3",
448					  "link_state_p4",
449					  "link_state_p5",
450					  "link_state_p7",
451					  "link_state_p8",
452					  "phy",
453					  "ts",
454					  "imp_sleep_timer_p5",
455					  "imp_sleep_timer_p7",
456					  "imp_sleep_timer_p8";
457			status = "disabled";
458
459			/* ports are defined in board DTS */
460			ports {
461				#address-cells = <1>;
462				#size-cells = <0>;
463			};
464		};
465
466		i2c0: i2c@38000 {
467			compatible = "brcm,iproc-i2c";
468			reg = <0x38000 0x50>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
472			clock-frequency = <100000>;
473			dma-coherent;
474			status = "disabled";
475		};
476
477		watchdog@39000 {
478			compatible = "arm,sp805", "arm,primecell";
479			reg = <0x39000 0x1000>;
480			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
481			clocks = <&iprocslow>, <&iprocslow>;
482			clock-names = "wdog_clk", "apb_pclk";
483		};
484
485		lcpll0: lcpll0@3f100 {
486			#clock-cells = <1>;
487			compatible = "brcm,nsp-lcpll0";
488			reg = <0x3f100 0x14>;
489			clocks = <&osc>;
490			clock-output-names = "lcpll0", "pcie_phy", "sdio",
491					     "ddr_phy";
492		};
493
494		genpll: genpll@3f140 {
495			#clock-cells = <1>;
496			compatible = "brcm,nsp-genpll";
497			reg = <0x3f140 0x24>;
498			clocks = <&osc>;
499			clock-output-names = "genpll", "phy", "ethernetclk",
500					     "usbclk", "iprocfast", "sata1",
501					     "sata2";
502		};
503
504		pinctrl: pinctrl@3f1c0 {
505			compatible = "brcm,nsp-pinmux";
506			reg = <0x3f1c0 0x04>,
507			      <0x30028 0x04>,
508			      <0x3f408 0x04>;
509		};
510
511		thermal: thermal@3f2c0 {
512			compatible = "brcm,ns-thermal";
513			reg = <0x3f2c0 0x10>;
514			#thermal-sensor-cells = <0>;
515		};
516
517		sata_phy: sata_phy@40100 {
518			compatible = "brcm,iproc-nsp-sata-phy";
519			reg = <0x40100 0x340>;
520			reg-names = "phy";
521			#address-cells = <1>;
522			#size-cells = <0>;
523
524			sata_phy0: sata-phy@0 {
525				reg = <0>;
526				#phy-cells = <0>;
527				status = "disabled";
528			};
529
530			sata_phy1: sata-phy@1 {
531				reg = <1>;
532				#phy-cells = <0>;
533				status = "disabled";
534			};
535		};
536
537		sata: sata@41000 {
538			compatible = "brcm,bcm-nsp-ahci";
539			reg-names = "ahci", "top-ctrl";
540			reg = <0x41000 0x1000>, <0x40020 0x1c>;
541			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
542			#address-cells = <1>;
543			#size-cells = <0>;
544			dma-coherent;
545			status = "disabled";
546
547			sata0: sata-port@0 {
548				reg = <0>;
549				phys = <&sata_phy0>;
550				phy-names = "sata-phy";
551			};
552
553			sata1: sata-port@1 {
554				reg = <1>;
555				phys = <&sata_phy1>;
556				phy-names = "sata-phy";
557			};
558		};
559
560		usb3_dmp: syscon@104000 {
561			reg = <0x104000 0x1000>;
562		};
563	};
564
565	pcie0: pcie@18012000 {
566		compatible = "brcm,iproc-pcie";
567		reg = <0x18012000 0x1000>;
568
569		#interrupt-cells = <1>;
570		interrupt-map-mask = <0 0 0 0>;
571		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
572
573		linux,pci-domain = <0>;
574
575		bus-range = <0x00 0xff>;
576
577		#address-cells = <3>;
578		#size-cells = <2>;
579		device_type = "pci";
580
581		/* Note: The HW does not support I/O resources.  So,
582		 * only the memory resource range is being specified.
583		 */
584		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
585
586		dma-coherent;
587		status = "disabled";
588
589		msi-parent = <&msi0>;
590		msi0: msi {
591			compatible = "brcm,iproc-msi";
592			msi-controller;
593			interrupt-parent = <&gic>;
594			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
595				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
596				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
597				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
598			brcm,pcie-msi-inten;
599		};
600	};
601
602	pcie1: pcie@18013000 {
603		compatible = "brcm,iproc-pcie";
604		reg = <0x18013000 0x1000>;
605
606		#interrupt-cells = <1>;
607		interrupt-map-mask = <0 0 0 0>;
608		interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
609
610		linux,pci-domain = <1>;
611
612		bus-range = <0x00 0xff>;
613
614		#address-cells = <3>;
615		#size-cells = <2>;
616		device_type = "pci";
617
618		/* Note: The HW does not support I/O resources.  So,
619		 * only the memory resource range is being specified.
620		 */
621		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
622
623		dma-coherent;
624		status = "disabled";
625
626		msi-parent = <&msi1>;
627		msi1: msi {
628			compatible = "brcm,iproc-msi";
629			msi-controller;
630			interrupt-parent = <&gic>;
631			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
632				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
633				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
634				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
635			brcm,pcie-msi-inten;
636		};
637	};
638
639	pcie2: pcie@18014000 {
640		compatible = "brcm,iproc-pcie";
641		reg = <0x18014000 0x1000>;
642
643		#interrupt-cells = <1>;
644		interrupt-map-mask = <0 0 0 0>;
645		interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
646
647		linux,pci-domain = <2>;
648
649		bus-range = <0x00 0xff>;
650
651		#address-cells = <3>;
652		#size-cells = <2>;
653		device_type = "pci";
654
655		/* Note: The HW does not support I/O resources.  So,
656		 * only the memory resource range is being specified.
657		 */
658		ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
659
660		dma-coherent;
661		status = "disabled";
662
663		msi-parent = <&msi2>;
664		msi2: msi {
665			compatible = "brcm,iproc-msi";
666			msi-controller;
667			interrupt-parent = <&gic>;
668			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
669				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
670				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
671				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
672			brcm,pcie-msi-inten;
673		};
674	};
675
676	thermal-zones {
677		cpu-thermal {
678			polling-delay-passive = <0>;
679			polling-delay = <1000>;
680			coefficients = <(-556) 418000>;
681			thermal-sensors = <&thermal>;
682
683			trips {
684				cpu-crit {
685					temperature     = <125000>;
686					hysteresis      = <0>;
687					type            = "critical";
688				};
689			};
690
691			cooling-maps {
692			};
693		};
694	};
695};
696