1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
4
5/ {
6	model = "Aspeed BMC";
7	compatible = "aspeed,ast2500";
8	#address-cells = <1>;
9	#size-cells = <1>;
10	interrupt-parent = <&vic>;
11
12	aliases {
13		i2c0 = &i2c0;
14		i2c1 = &i2c1;
15		i2c2 = &i2c2;
16		i2c3 = &i2c3;
17		i2c4 = &i2c4;
18		i2c5 = &i2c5;
19		i2c6 = &i2c6;
20		i2c7 = &i2c7;
21		i2c8 = &i2c8;
22		i2c9 = &i2c9;
23		i2c10 = &i2c10;
24		i2c11 = &i2c11;
25		i2c12 = &i2c12;
26		i2c13 = &i2c13;
27		serial0 = &uart1;
28		serial1 = &uart2;
29		serial2 = &uart3;
30		serial3 = &uart4;
31		serial4 = &uart5;
32		serial5 = &vuart;
33	};
34
35	cpus {
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		cpu@0 {
40			compatible = "arm,arm1176jzf-s";
41			device_type = "cpu";
42			reg = <0>;
43		};
44	};
45
46	memory@80000000 {
47		device_type = "memory";
48		reg = <0x80000000 0>;
49	};
50
51	ahb {
52		compatible = "simple-bus";
53		#address-cells = <1>;
54		#size-cells = <1>;
55		ranges;
56
57		fmc: spi@1e620000 {
58			reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
59			#address-cells = <1>;
60			#size-cells = <0>;
61			compatible = "aspeed,ast2500-fmc";
62			clocks = <&syscon ASPEED_CLK_AHB>;
63			status = "disabled";
64			interrupts = <19>;
65			flash@0 {
66				reg = < 0 >;
67				compatible = "jedec,spi-nor";
68				spi-max-frequency = <50000000>;
69				spi-rx-bus-width = <2>;
70				status = "disabled";
71			};
72			flash@1 {
73				reg = < 1 >;
74				compatible = "jedec,spi-nor";
75				spi-max-frequency = <50000000>;
76				spi-rx-bus-width = <2>;
77				status = "disabled";
78			};
79			flash@2 {
80				reg = < 2 >;
81				compatible = "jedec,spi-nor";
82				spi-max-frequency = <50000000>;
83				spi-rx-bus-width = <2>;
84				status = "disabled";
85			};
86		};
87
88		spi1: spi@1e630000 {
89			reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
90			#address-cells = <1>;
91			#size-cells = <0>;
92			compatible = "aspeed,ast2500-spi";
93			clocks = <&syscon ASPEED_CLK_AHB>;
94			status = "disabled";
95			flash@0 {
96				reg = < 0 >;
97				compatible = "jedec,spi-nor";
98				spi-max-frequency = <50000000>;
99				spi-rx-bus-width = <2>;
100				status = "disabled";
101			};
102			flash@1 {
103				reg = < 1 >;
104				compatible = "jedec,spi-nor";
105				spi-max-frequency = <50000000>;
106				spi-rx-bus-width = <2>;
107				status = "disabled";
108			};
109		};
110
111		spi2: spi@1e631000 {
112			reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
113			#address-cells = <1>;
114			#size-cells = <0>;
115			compatible = "aspeed,ast2500-spi";
116			clocks = <&syscon ASPEED_CLK_AHB>;
117			status = "disabled";
118			flash@0 {
119				reg = < 0 >;
120				compatible = "jedec,spi-nor";
121				spi-max-frequency = <50000000>;
122				spi-rx-bus-width = <2>;
123				status = "disabled";
124			};
125			flash@1 {
126				reg = < 1 >;
127				compatible = "jedec,spi-nor";
128				spi-max-frequency = <50000000>;
129				spi-rx-bus-width = <2>;
130				status = "disabled";
131			};
132		};
133
134		vic: interrupt-controller@1e6c0080 {
135			compatible = "aspeed,ast2400-vic";
136			interrupt-controller;
137			#interrupt-cells = <1>;
138			valid-sources = <0xfefff7ff 0x0807ffff>;
139			reg = <0x1e6c0080 0x80>;
140		};
141
142		cvic: copro-interrupt-controller@1e6c2000 {
143			compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
144			valid-sources = <0xffffffff>;
145			copro-sw-interrupts = <1>;
146			reg = <0x1e6c2000 0x80>;
147		};
148
149		mac0: ethernet@1e660000 {
150			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
151			reg = <0x1e660000 0x180>;
152			interrupts = <2>;
153			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
154			status = "disabled";
155		};
156
157		mac1: ethernet@1e680000 {
158			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
159			reg = <0x1e680000 0x180>;
160			interrupts = <3>;
161			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
162			status = "disabled";
163		};
164
165		ehci0: usb@1e6a1000 {
166			compatible = "aspeed,ast2500-ehci", "generic-ehci";
167			reg = <0x1e6a1000 0x100>;
168			interrupts = <5>;
169			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
170			pinctrl-names = "default";
171			pinctrl-0 = <&pinctrl_usb2ah_default>;
172			status = "disabled";
173		};
174
175		ehci1: usb@1e6a3000 {
176			compatible = "aspeed,ast2500-ehci", "generic-ehci";
177			reg = <0x1e6a3000 0x100>;
178			interrupts = <13>;
179			clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
180			pinctrl-names = "default";
181			pinctrl-0 = <&pinctrl_usb2bh_default>;
182			status = "disabled";
183		};
184
185		uhci: usb@1e6b0000 {
186			compatible = "aspeed,ast2500-uhci", "generic-uhci";
187			reg = <0x1e6b0000 0x100>;
188			interrupts = <14>;
189			#ports = <2>;
190			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
191			status = "disabled";
192			/*
193			 * No default pinmux, it will follow EHCI, use an explicit pinmux
194			 * override if you don't enable EHCI
195			 */
196		};
197
198		vhub: usb-vhub@1e6a0000 {
199			compatible = "aspeed,ast2500-usb-vhub";
200			reg = <0x1e6a0000 0x300>;
201			interrupts = <5>;
202			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
203			aspeed,vhub-downstream-ports = <5>;
204			aspeed,vhub-generic-endpoints = <15>;
205			pinctrl-names = "default";
206			pinctrl-0 = <&pinctrl_usb2ad_default>;
207			status = "disabled";
208		};
209
210		apb {
211			compatible = "simple-bus";
212			#address-cells = <1>;
213			#size-cells = <1>;
214			ranges;
215
216			edac: memory-controller@1e6e0000 {
217				compatible = "aspeed,ast2500-sdram-edac";
218				reg = <0x1e6e0000 0x174>;
219				interrupts = <0>;
220				status = "disabled";
221			};
222
223			syscon: syscon@1e6e2000 {
224				compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
225				reg = <0x1e6e2000 0x1a8>;
226				#address-cells = <1>;
227				#size-cells = <1>;
228				ranges = <0 0x1e6e2000 0x1000>;
229				#clock-cells = <1>;
230				#reset-cells = <1>;
231
232				scu_ic: interrupt-controller@18 {
233					#interrupt-cells = <1>;
234					compatible = "aspeed,ast2500-scu-ic";
235					reg = <0x18 0x4>;
236					interrupts = <21>;
237					interrupt-controller;
238				};
239
240				p2a: p2a-control@2c {
241					compatible = "aspeed,ast2500-p2a-ctrl";
242					reg = <0x2c 0x4>;
243					status = "disabled";
244				};
245
246				silicon-id@7c {
247					compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
248					reg = <0x7c 0x4 0x150 0x8>;
249				};
250
251				pinctrl: pinctrl@80 {
252					compatible = "aspeed,ast2500-pinctrl";
253					reg = <0x80 0x18>, <0xa0 0x10>;
254					aspeed,external-nodes = <&gfx>, <&lhc>;
255				};
256			};
257
258			rng: hwrng@1e6e2078 {
259				compatible = "timeriomem_rng";
260				reg = <0x1e6e2078 0x4>;
261				period = <1>;
262				quality = <100>;
263			};
264
265			hace: crypto@1e6e3000 {
266				compatible = "aspeed,ast2500-hace";
267				reg = <0x1e6e3000 0x100>;
268				interrupts = <4>;
269				clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
270				resets = <&syscon ASPEED_RESET_HACE>;
271			};
272
273			gfx: display@1e6e6000 {
274				compatible = "aspeed,ast2500-gfx", "syscon";
275				reg = <0x1e6e6000 0x1000>;
276				reg-io-width = <4>;
277				clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
278				resets = <&syscon ASPEED_RESET_CRT1>;
279				syscon = <&syscon>;
280				status = "disabled";
281				interrupts = <0x19>;
282			};
283
284			xdma: xdma@1e6e7000 {
285				compatible = "aspeed,ast2500-xdma";
286				reg = <0x1e6e7000 0x100>;
287				clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
288				resets = <&syscon ASPEED_RESET_XDMA>;
289				interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
290				aspeed,pcie-device = "bmc";
291				aspeed,scu = <&syscon>;
292				status = "disabled";
293			};
294
295			adc: adc@1e6e9000 {
296				compatible = "aspeed,ast2500-adc";
297				reg = <0x1e6e9000 0xb0>;
298				clocks = <&syscon ASPEED_CLK_APB>;
299				resets = <&syscon ASPEED_RESET_ADC>;
300				#io-channel-cells = <1>;
301				status = "disabled";
302			};
303
304			video: video@1e700000 {
305				compatible = "aspeed,ast2500-video-engine";
306				reg = <0x1e700000 0x1000>;
307				clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
308					 <&syscon ASPEED_CLK_GATE_ECLK>;
309				clock-names = "vclk", "eclk";
310				interrupts = <7>;
311				status = "disabled";
312			};
313
314			sram: sram@1e720000 {
315				compatible = "mmio-sram";
316				reg = <0x1e720000 0x9000>;	// 36K
317			};
318
319			sdmmc: sd-controller@1e740000 {
320				compatible = "aspeed,ast2500-sd-controller";
321				reg = <0x1e740000 0x100>;
322				#address-cells = <1>;
323				#size-cells = <1>;
324				ranges = <0 0x1e740000 0x10000>;
325				clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
326				status = "disabled";
327
328				sdhci0: sdhci@100 {
329					compatible = "aspeed,ast2500-sdhci";
330					reg = <0x100 0x100>;
331					interrupts = <26>;
332					sdhci,auto-cmd12;
333					clocks = <&syscon ASPEED_CLK_SDIO>;
334					status = "disabled";
335				};
336
337				sdhci1: sdhci@200 {
338					compatible = "aspeed,ast2500-sdhci";
339					reg = <0x200 0x100>;
340					interrupts = <26>;
341					sdhci,auto-cmd12;
342					clocks = <&syscon ASPEED_CLK_SDIO>;
343					status = "disabled";
344				};
345			};
346
347			gpio: gpio@1e780000 {
348				#gpio-cells = <2>;
349				gpio-controller;
350				compatible = "aspeed,ast2500-gpio";
351				reg = <0x1e780000 0x200>;
352				interrupts = <20>;
353				gpio-ranges = <&pinctrl 0 0 232>;
354				clocks = <&syscon ASPEED_CLK_APB>;
355				interrupt-controller;
356				#interrupt-cells = <2>;
357			};
358
359			sgpio: sgpio@1e780200 {
360				#gpio-cells = <2>;
361				compatible = "aspeed,ast2500-sgpio";
362				gpio-controller;
363				interrupts = <40>;
364				reg = <0x1e780200 0x0100>;
365				clocks = <&syscon ASPEED_CLK_APB>;
366				#interrupt-cells = <2>;
367				interrupt-controller;
368				bus-frequency = <12000000>;
369				pinctrl-names = "default";
370				pinctrl-0 = <&pinctrl_sgpm_default>;
371				status = "disabled";
372			};
373
374			rtc: rtc@1e781000 {
375				compatible = "aspeed,ast2500-rtc";
376				reg = <0x1e781000 0x18>;
377				status = "disabled";
378			};
379
380			timer: timer@1e782000 {
381				/* This timer is a Faraday FTTMR010 derivative */
382				compatible = "aspeed,ast2400-timer";
383				reg = <0x1e782000 0x90>;
384				interrupts = <16 17 18 35 36 37 38 39>;
385				clocks = <&syscon ASPEED_CLK_APB>;
386				clock-names = "PCLK";
387			};
388
389			uart1: serial@1e783000 {
390				compatible = "ns16550a";
391				reg = <0x1e783000 0x20>;
392				reg-shift = <2>;
393				interrupts = <9>;
394				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
395				resets = <&lpc_reset 4>;
396				no-loopback-test;
397				status = "disabled";
398			};
399
400			uart5: serial@1e784000 {
401				compatible = "ns16550a";
402				reg = <0x1e784000 0x20>;
403				reg-shift = <2>;
404				interrupts = <10>;
405				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
406				no-loopback-test;
407				status = "disabled";
408			};
409
410			wdt1: watchdog@1e785000 {
411				compatible = "aspeed,ast2500-wdt";
412				reg = <0x1e785000 0x20>;
413				clocks = <&syscon ASPEED_CLK_APB>;
414			};
415
416			wdt2: watchdog@1e785020 {
417				compatible = "aspeed,ast2500-wdt";
418				reg = <0x1e785020 0x20>;
419				clocks = <&syscon ASPEED_CLK_APB>;
420			};
421
422			wdt3: watchdog@1e785040 {
423				compatible = "aspeed,ast2500-wdt";
424				reg = <0x1e785040 0x20>;
425				clocks = <&syscon ASPEED_CLK_APB>;
426				status = "disabled";
427			};
428
429			pwm_tacho: pwm-tacho-controller@1e786000 {
430				compatible = "aspeed,ast2500-pwm-tacho";
431				#address-cells = <1>;
432				#size-cells = <0>;
433				reg = <0x1e786000 0x1000>;
434				clocks = <&syscon ASPEED_CLK_24M>;
435				resets = <&syscon ASPEED_RESET_PWM>;
436				status = "disabled";
437			};
438
439			vuart: serial@1e787000 {
440				compatible = "aspeed,ast2500-vuart";
441				reg = <0x1e787000 0x40>;
442				reg-shift = <2>;
443				interrupts = <8>;
444				clocks = <&syscon ASPEED_CLK_APB>;
445				no-loopback-test;
446				status = "disabled";
447			};
448
449			lpc: lpc@1e789000 {
450				compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
451				reg = <0x1e789000 0x1000>;
452				reg-io-width = <4>;
453
454				#address-cells = <1>;
455				#size-cells = <1>;
456				ranges = <0x0 0x1e789000 0x1000>;
457
458				kcs1: kcs@24 {
459					compatible = "aspeed,ast2500-kcs-bmc-v2";
460					reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
461					interrupts = <8>;
462					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
463					status = "disabled";
464				};
465
466				kcs2: kcs@28 {
467					compatible = "aspeed,ast2500-kcs-bmc-v2";
468					reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
469					interrupts = <8>;
470					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
471					status = "disabled";
472				};
473
474				kcs3: kcs@2c {
475					compatible = "aspeed,ast2500-kcs-bmc-v2";
476					reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
477					interrupts = <8>;
478					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
479					status = "disabled";
480				};
481
482				kcs4: kcs@114 {
483					compatible = "aspeed,ast2500-kcs-bmc-v2";
484					reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
485					interrupts = <8>;
486					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
487					status = "disabled";
488				};
489
490				lpc_ctrl: lpc-ctrl@80 {
491					compatible = "aspeed,ast2500-lpc-ctrl";
492					reg = <0x80 0x10>;
493					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
494					status = "disabled";
495				};
496
497				lpc_snoop: lpc-snoop@90 {
498					compatible = "aspeed,ast2500-lpc-snoop";
499					reg = <0x90 0x8>;
500					interrupts = <8>;
501					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
502					status = "disabled";
503				};
504
505				lpc_reset: reset-controller@98 {
506					compatible = "aspeed,ast2500-lpc-reset";
507					reg = <0x98 0x4>;
508					#reset-cells = <1>;
509				};
510
511				uart_routing: uart-routing@9c {
512					compatible = "aspeed,ast2500-uart-routing";
513					reg = <0x9c 0x4>;
514					status = "disabled";
515				};
516
517				lhc: lhc@a0 {
518					compatible = "aspeed,ast2500-lhc";
519					reg = <0xa0 0x24 0xc8 0x8>;
520				};
521
522
523				ibt: ibt@140 {
524					compatible = "aspeed,ast2500-ibt-bmc";
525					reg = <0x140 0x18>;
526					interrupts = <8>;
527					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
528					status = "disabled";
529				};
530			};
531
532			peci0: peci-controller@1e78b000 {
533				compatible = "aspeed,ast2500-peci";
534				reg = <0x1e78b000 0x60>;
535				interrupts = <15>;
536				clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
537				resets = <&syscon ASPEED_RESET_PECI>;
538				cmd-timeout-ms = <1000>;
539				clock-frequency = <1000000>;
540				status = "disabled";
541			};
542
543			uart2: serial@1e78d000 {
544				compatible = "ns16550a";
545				reg = <0x1e78d000 0x20>;
546				reg-shift = <2>;
547				interrupts = <32>;
548				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
549				resets = <&lpc_reset 5>;
550				no-loopback-test;
551				status = "disabled";
552			};
553
554			uart3: serial@1e78e000 {
555				compatible = "ns16550a";
556				reg = <0x1e78e000 0x20>;
557				reg-shift = <2>;
558				interrupts = <33>;
559				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
560				resets = <&lpc_reset 6>;
561				no-loopback-test;
562				status = "disabled";
563			};
564
565			uart4: serial@1e78f000 {
566				compatible = "ns16550a";
567				reg = <0x1e78f000 0x20>;
568				reg-shift = <2>;
569				interrupts = <34>;
570				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
571				resets = <&lpc_reset 7>;
572				no-loopback-test;
573				status = "disabled";
574			};
575
576			i2c: bus@1e78a000 {
577				compatible = "simple-bus";
578				#address-cells = <1>;
579				#size-cells = <1>;
580				ranges = <0 0x1e78a000 0x1000>;
581			};
582		};
583	};
584};
585
586&i2c {
587	i2c_ic: interrupt-controller@0 {
588		#interrupt-cells = <1>;
589		compatible = "aspeed,ast2500-i2c-ic";
590		reg = <0x0 0x40>;
591		interrupts = <12>;
592		interrupt-controller;
593	};
594
595	i2c0: i2c-bus@40 {
596		#address-cells = <1>;
597		#size-cells = <0>;
598
599		reg = <0x40 0x40>;
600		compatible = "aspeed,ast2500-i2c-bus";
601		clocks = <&syscon ASPEED_CLK_APB>;
602		resets = <&syscon ASPEED_RESET_I2C>;
603		bus-frequency = <100000>;
604		interrupts = <0>;
605		interrupt-parent = <&i2c_ic>;
606		status = "disabled";
607		/* Does not need pinctrl properties */
608	};
609
610	i2c1: i2c-bus@80 {
611		#address-cells = <1>;
612		#size-cells = <0>;
613
614		reg = <0x80 0x40>;
615		compatible = "aspeed,ast2500-i2c-bus";
616		clocks = <&syscon ASPEED_CLK_APB>;
617		resets = <&syscon ASPEED_RESET_I2C>;
618		bus-frequency = <100000>;
619		interrupts = <1>;
620		interrupt-parent = <&i2c_ic>;
621		status = "disabled";
622		/* Does not need pinctrl properties */
623	};
624
625	i2c2: i2c-bus@c0 {
626		#address-cells = <1>;
627		#size-cells = <0>;
628
629		reg = <0xc0 0x40>;
630		compatible = "aspeed,ast2500-i2c-bus";
631		clocks = <&syscon ASPEED_CLK_APB>;
632		resets = <&syscon ASPEED_RESET_I2C>;
633		bus-frequency = <100000>;
634		interrupts = <2>;
635		interrupt-parent = <&i2c_ic>;
636		pinctrl-names = "default";
637		pinctrl-0 = <&pinctrl_i2c3_default>;
638		status = "disabled";
639	};
640
641	i2c3: i2c-bus@100 {
642		#address-cells = <1>;
643		#size-cells = <0>;
644
645		reg = <0x100 0x40>;
646		compatible = "aspeed,ast2500-i2c-bus";
647		clocks = <&syscon ASPEED_CLK_APB>;
648		resets = <&syscon ASPEED_RESET_I2C>;
649		bus-frequency = <100000>;
650		interrupts = <3>;
651		interrupt-parent = <&i2c_ic>;
652		pinctrl-names = "default";
653		pinctrl-0 = <&pinctrl_i2c4_default>;
654		status = "disabled";
655	};
656
657	i2c4: i2c-bus@140 {
658		#address-cells = <1>;
659		#size-cells = <0>;
660
661		reg = <0x140 0x40>;
662		compatible = "aspeed,ast2500-i2c-bus";
663		clocks = <&syscon ASPEED_CLK_APB>;
664		resets = <&syscon ASPEED_RESET_I2C>;
665		bus-frequency = <100000>;
666		interrupts = <4>;
667		interrupt-parent = <&i2c_ic>;
668		pinctrl-names = "default";
669		pinctrl-0 = <&pinctrl_i2c5_default>;
670		status = "disabled";
671	};
672
673	i2c5: i2c-bus@180 {
674		#address-cells = <1>;
675		#size-cells = <0>;
676
677		reg = <0x180 0x40>;
678		compatible = "aspeed,ast2500-i2c-bus";
679		clocks = <&syscon ASPEED_CLK_APB>;
680		resets = <&syscon ASPEED_RESET_I2C>;
681		bus-frequency = <100000>;
682		interrupts = <5>;
683		interrupt-parent = <&i2c_ic>;
684		pinctrl-names = "default";
685		pinctrl-0 = <&pinctrl_i2c6_default>;
686		status = "disabled";
687	};
688
689	i2c6: i2c-bus@1c0 {
690		#address-cells = <1>;
691		#size-cells = <0>;
692
693		reg = <0x1c0 0x40>;
694		compatible = "aspeed,ast2500-i2c-bus";
695		clocks = <&syscon ASPEED_CLK_APB>;
696		resets = <&syscon ASPEED_RESET_I2C>;
697		bus-frequency = <100000>;
698		interrupts = <6>;
699		interrupt-parent = <&i2c_ic>;
700		pinctrl-names = "default";
701		pinctrl-0 = <&pinctrl_i2c7_default>;
702		status = "disabled";
703	};
704
705	i2c7: i2c-bus@300 {
706		#address-cells = <1>;
707		#size-cells = <0>;
708
709		reg = <0x300 0x40>;
710		compatible = "aspeed,ast2500-i2c-bus";
711		clocks = <&syscon ASPEED_CLK_APB>;
712		resets = <&syscon ASPEED_RESET_I2C>;
713		bus-frequency = <100000>;
714		interrupts = <7>;
715		interrupt-parent = <&i2c_ic>;
716		pinctrl-names = "default";
717		pinctrl-0 = <&pinctrl_i2c8_default>;
718		status = "disabled";
719	};
720
721	i2c8: i2c-bus@340 {
722		#address-cells = <1>;
723		#size-cells = <0>;
724
725		reg = <0x340 0x40>;
726		compatible = "aspeed,ast2500-i2c-bus";
727		clocks = <&syscon ASPEED_CLK_APB>;
728		resets = <&syscon ASPEED_RESET_I2C>;
729		bus-frequency = <100000>;
730		interrupts = <8>;
731		interrupt-parent = <&i2c_ic>;
732		pinctrl-names = "default";
733		pinctrl-0 = <&pinctrl_i2c9_default>;
734		status = "disabled";
735	};
736
737	i2c9: i2c-bus@380 {
738		#address-cells = <1>;
739		#size-cells = <0>;
740
741		reg = <0x380 0x40>;
742		compatible = "aspeed,ast2500-i2c-bus";
743		clocks = <&syscon ASPEED_CLK_APB>;
744		resets = <&syscon ASPEED_RESET_I2C>;
745		bus-frequency = <100000>;
746		interrupts = <9>;
747		interrupt-parent = <&i2c_ic>;
748		pinctrl-names = "default";
749		pinctrl-0 = <&pinctrl_i2c10_default>;
750		status = "disabled";
751	};
752
753	i2c10: i2c-bus@3c0 {
754		#address-cells = <1>;
755		#size-cells = <0>;
756
757		reg = <0x3c0 0x40>;
758		compatible = "aspeed,ast2500-i2c-bus";
759		clocks = <&syscon ASPEED_CLK_APB>;
760		resets = <&syscon ASPEED_RESET_I2C>;
761		bus-frequency = <100000>;
762		interrupts = <10>;
763		interrupt-parent = <&i2c_ic>;
764		pinctrl-names = "default";
765		pinctrl-0 = <&pinctrl_i2c11_default>;
766		status = "disabled";
767	};
768
769	i2c11: i2c-bus@400 {
770		#address-cells = <1>;
771		#size-cells = <0>;
772
773		reg = <0x400 0x40>;
774		compatible = "aspeed,ast2500-i2c-bus";
775		clocks = <&syscon ASPEED_CLK_APB>;
776		resets = <&syscon ASPEED_RESET_I2C>;
777		bus-frequency = <100000>;
778		interrupts = <11>;
779		interrupt-parent = <&i2c_ic>;
780		pinctrl-names = "default";
781		pinctrl-0 = <&pinctrl_i2c12_default>;
782		status = "disabled";
783	};
784
785	i2c12: i2c-bus@440 {
786		#address-cells = <1>;
787		#size-cells = <0>;
788
789		reg = <0x440 0x40>;
790		compatible = "aspeed,ast2500-i2c-bus";
791		clocks = <&syscon ASPEED_CLK_APB>;
792		resets = <&syscon ASPEED_RESET_I2C>;
793		bus-frequency = <100000>;
794		interrupts = <12>;
795		interrupt-parent = <&i2c_ic>;
796		pinctrl-names = "default";
797		pinctrl-0 = <&pinctrl_i2c13_default>;
798		status = "disabled";
799	};
800
801	i2c13: i2c-bus@480 {
802		#address-cells = <1>;
803		#size-cells = <0>;
804
805		reg = <0x480 0x40>;
806		compatible = "aspeed,ast2500-i2c-bus";
807		clocks = <&syscon ASPEED_CLK_APB>;
808		resets = <&syscon ASPEED_RESET_I2C>;
809		bus-frequency = <100000>;
810		interrupts = <13>;
811		interrupt-parent = <&i2c_ic>;
812		pinctrl-names = "default";
813		pinctrl-0 = <&pinctrl_i2c14_default>;
814		status = "disabled";
815	};
816};
817
818&pinctrl {
819	pinctrl_acpi_default: acpi_default {
820		function = "ACPI";
821		groups = "ACPI";
822	};
823
824	pinctrl_adc0_default: adc0_default {
825		function = "ADC0";
826		groups = "ADC0";
827	};
828
829	pinctrl_adc1_default: adc1_default {
830		function = "ADC1";
831		groups = "ADC1";
832	};
833
834	pinctrl_adc10_default: adc10_default {
835		function = "ADC10";
836		groups = "ADC10";
837	};
838
839	pinctrl_adc11_default: adc11_default {
840		function = "ADC11";
841		groups = "ADC11";
842	};
843
844	pinctrl_adc12_default: adc12_default {
845		function = "ADC12";
846		groups = "ADC12";
847	};
848
849	pinctrl_adc13_default: adc13_default {
850		function = "ADC13";
851		groups = "ADC13";
852	};
853
854	pinctrl_adc14_default: adc14_default {
855		function = "ADC14";
856		groups = "ADC14";
857	};
858
859	pinctrl_adc15_default: adc15_default {
860		function = "ADC15";
861		groups = "ADC15";
862	};
863
864	pinctrl_adc2_default: adc2_default {
865		function = "ADC2";
866		groups = "ADC2";
867	};
868
869	pinctrl_adc3_default: adc3_default {
870		function = "ADC3";
871		groups = "ADC3";
872	};
873
874	pinctrl_adc4_default: adc4_default {
875		function = "ADC4";
876		groups = "ADC4";
877	};
878
879	pinctrl_adc5_default: adc5_default {
880		function = "ADC5";
881		groups = "ADC5";
882	};
883
884	pinctrl_adc6_default: adc6_default {
885		function = "ADC6";
886		groups = "ADC6";
887	};
888
889	pinctrl_adc7_default: adc7_default {
890		function = "ADC7";
891		groups = "ADC7";
892	};
893
894	pinctrl_adc8_default: adc8_default {
895		function = "ADC8";
896		groups = "ADC8";
897	};
898
899	pinctrl_adc9_default: adc9_default {
900		function = "ADC9";
901		groups = "ADC9";
902	};
903
904	pinctrl_bmcint_default: bmcint_default {
905		function = "BMCINT";
906		groups = "BMCINT";
907	};
908
909	pinctrl_ddcclk_default: ddcclk_default {
910		function = "DDCCLK";
911		groups = "DDCCLK";
912	};
913
914	pinctrl_ddcdat_default: ddcdat_default {
915		function = "DDCDAT";
916		groups = "DDCDAT";
917	};
918
919	pinctrl_espi_default: espi_default {
920		function = "ESPI";
921		groups = "ESPI";
922	};
923
924	pinctrl_fwspics1_default: fwspics1_default {
925		function = "FWSPICS1";
926		groups = "FWSPICS1";
927	};
928
929	pinctrl_fwspics2_default: fwspics2_default {
930		function = "FWSPICS2";
931		groups = "FWSPICS2";
932	};
933
934	pinctrl_gpid0_default: gpid0_default {
935		function = "GPID0";
936		groups = "GPID0";
937	};
938
939	pinctrl_gpid2_default: gpid2_default {
940		function = "GPID2";
941		groups = "GPID2";
942	};
943
944	pinctrl_gpid4_default: gpid4_default {
945		function = "GPID4";
946		groups = "GPID4";
947	};
948
949	pinctrl_gpid6_default: gpid6_default {
950		function = "GPID6";
951		groups = "GPID6";
952	};
953
954	pinctrl_gpie0_default: gpie0_default {
955		function = "GPIE0";
956		groups = "GPIE0";
957	};
958
959	pinctrl_gpie2_default: gpie2_default {
960		function = "GPIE2";
961		groups = "GPIE2";
962	};
963
964	pinctrl_gpie4_default: gpie4_default {
965		function = "GPIE4";
966		groups = "GPIE4";
967	};
968
969	pinctrl_gpie6_default: gpie6_default {
970		function = "GPIE6";
971		groups = "GPIE6";
972	};
973
974	pinctrl_i2c10_default: i2c10_default {
975		function = "I2C10";
976		groups = "I2C10";
977	};
978
979	pinctrl_i2c11_default: i2c11_default {
980		function = "I2C11";
981		groups = "I2C11";
982	};
983
984	pinctrl_i2c12_default: i2c12_default {
985		function = "I2C12";
986		groups = "I2C12";
987	};
988
989	pinctrl_i2c13_default: i2c13_default {
990		function = "I2C13";
991		groups = "I2C13";
992	};
993
994	pinctrl_i2c14_default: i2c14_default {
995		function = "I2C14";
996		groups = "I2C14";
997	};
998
999	pinctrl_i2c3_default: i2c3_default {
1000		function = "I2C3";
1001		groups = "I2C3";
1002	};
1003
1004	pinctrl_i2c4_default: i2c4_default {
1005		function = "I2C4";
1006		groups = "I2C4";
1007	};
1008
1009	pinctrl_i2c5_default: i2c5_default {
1010		function = "I2C5";
1011		groups = "I2C5";
1012	};
1013
1014	pinctrl_i2c6_default: i2c6_default {
1015		function = "I2C6";
1016		groups = "I2C6";
1017	};
1018
1019	pinctrl_i2c7_default: i2c7_default {
1020		function = "I2C7";
1021		groups = "I2C7";
1022	};
1023
1024	pinctrl_i2c8_default: i2c8_default {
1025		function = "I2C8";
1026		groups = "I2C8";
1027	};
1028
1029	pinctrl_i2c9_default: i2c9_default {
1030		function = "I2C9";
1031		groups = "I2C9";
1032	};
1033
1034	pinctrl_lad0_default: lad0_default {
1035		function = "LAD0";
1036		groups = "LAD0";
1037	};
1038
1039	pinctrl_lad1_default: lad1_default {
1040		function = "LAD1";
1041		groups = "LAD1";
1042	};
1043
1044	pinctrl_lad2_default: lad2_default {
1045		function = "LAD2";
1046		groups = "LAD2";
1047	};
1048
1049	pinctrl_lad3_default: lad3_default {
1050		function = "LAD3";
1051		groups = "LAD3";
1052	};
1053
1054	pinctrl_lclk_default: lclk_default {
1055		function = "LCLK";
1056		groups = "LCLK";
1057	};
1058
1059	pinctrl_lframe_default: lframe_default {
1060		function = "LFRAME";
1061		groups = "LFRAME";
1062	};
1063
1064	pinctrl_lpchc_default: lpchc_default {
1065		function = "LPCHC";
1066		groups = "LPCHC";
1067	};
1068
1069	pinctrl_lpcpd_default: lpcpd_default {
1070		function = "LPCPD";
1071		groups = "LPCPD";
1072	};
1073
1074	pinctrl_lpcplus_default: lpcplus_default {
1075		function = "LPCPLUS";
1076		groups = "LPCPLUS";
1077	};
1078
1079	pinctrl_lpcpme_default: lpcpme_default {
1080		function = "LPCPME";
1081		groups = "LPCPME";
1082	};
1083
1084	pinctrl_lpcrst_default: lpcrst_default {
1085		function = "LPCRST";
1086		groups = "LPCRST";
1087	};
1088
1089	pinctrl_lpcsmi_default: lpcsmi_default {
1090		function = "LPCSMI";
1091		groups = "LPCSMI";
1092	};
1093
1094	pinctrl_lsirq_default: lsirq_default {
1095		function = "LSIRQ";
1096		groups = "LSIRQ";
1097	};
1098
1099	pinctrl_mac1link_default: mac1link_default {
1100		function = "MAC1LINK";
1101		groups = "MAC1LINK";
1102	};
1103
1104	pinctrl_mac2link_default: mac2link_default {
1105		function = "MAC2LINK";
1106		groups = "MAC2LINK";
1107	};
1108
1109	pinctrl_mdio1_default: mdio1_default {
1110		function = "MDIO1";
1111		groups = "MDIO1";
1112	};
1113
1114	pinctrl_mdio2_default: mdio2_default {
1115		function = "MDIO2";
1116		groups = "MDIO2";
1117	};
1118
1119	pinctrl_ncts1_default: ncts1_default {
1120		function = "NCTS1";
1121		groups = "NCTS1";
1122	};
1123
1124	pinctrl_ncts2_default: ncts2_default {
1125		function = "NCTS2";
1126		groups = "NCTS2";
1127	};
1128
1129	pinctrl_ncts3_default: ncts3_default {
1130		function = "NCTS3";
1131		groups = "NCTS3";
1132	};
1133
1134	pinctrl_ncts4_default: ncts4_default {
1135		function = "NCTS4";
1136		groups = "NCTS4";
1137	};
1138
1139	pinctrl_ndcd1_default: ndcd1_default {
1140		function = "NDCD1";
1141		groups = "NDCD1";
1142	};
1143
1144	pinctrl_ndcd2_default: ndcd2_default {
1145		function = "NDCD2";
1146		groups = "NDCD2";
1147	};
1148
1149	pinctrl_ndcd3_default: ndcd3_default {
1150		function = "NDCD3";
1151		groups = "NDCD3";
1152	};
1153
1154	pinctrl_ndcd4_default: ndcd4_default {
1155		function = "NDCD4";
1156		groups = "NDCD4";
1157	};
1158
1159	pinctrl_ndsr1_default: ndsr1_default {
1160		function = "NDSR1";
1161		groups = "NDSR1";
1162	};
1163
1164	pinctrl_ndsr2_default: ndsr2_default {
1165		function = "NDSR2";
1166		groups = "NDSR2";
1167	};
1168
1169	pinctrl_ndsr3_default: ndsr3_default {
1170		function = "NDSR3";
1171		groups = "NDSR3";
1172	};
1173
1174	pinctrl_ndsr4_default: ndsr4_default {
1175		function = "NDSR4";
1176		groups = "NDSR4";
1177	};
1178
1179	pinctrl_ndtr1_default: ndtr1_default {
1180		function = "NDTR1";
1181		groups = "NDTR1";
1182	};
1183
1184	pinctrl_ndtr2_default: ndtr2_default {
1185		function = "NDTR2";
1186		groups = "NDTR2";
1187	};
1188
1189	pinctrl_ndtr3_default: ndtr3_default {
1190		function = "NDTR3";
1191		groups = "NDTR3";
1192	};
1193
1194	pinctrl_ndtr4_default: ndtr4_default {
1195		function = "NDTR4";
1196		groups = "NDTR4";
1197	};
1198
1199	pinctrl_nri1_default: nri1_default {
1200		function = "NRI1";
1201		groups = "NRI1";
1202	};
1203
1204	pinctrl_nri2_default: nri2_default {
1205		function = "NRI2";
1206		groups = "NRI2";
1207	};
1208
1209	pinctrl_nri3_default: nri3_default {
1210		function = "NRI3";
1211		groups = "NRI3";
1212	};
1213
1214	pinctrl_nri4_default: nri4_default {
1215		function = "NRI4";
1216		groups = "NRI4";
1217	};
1218
1219	pinctrl_nrts1_default: nrts1_default {
1220		function = "NRTS1";
1221		groups = "NRTS1";
1222	};
1223
1224	pinctrl_nrts2_default: nrts2_default {
1225		function = "NRTS2";
1226		groups = "NRTS2";
1227	};
1228
1229	pinctrl_nrts3_default: nrts3_default {
1230		function = "NRTS3";
1231		groups = "NRTS3";
1232	};
1233
1234	pinctrl_nrts4_default: nrts4_default {
1235		function = "NRTS4";
1236		groups = "NRTS4";
1237	};
1238
1239	pinctrl_oscclk_default: oscclk_default {
1240		function = "OSCCLK";
1241		groups = "OSCCLK";
1242	};
1243
1244	pinctrl_pewake_default: pewake_default {
1245		function = "PEWAKE";
1246		groups = "PEWAKE";
1247	};
1248
1249	pinctrl_pnor_default: pnor_default {
1250		function = "PNOR";
1251		groups = "PNOR";
1252	};
1253
1254	pinctrl_pwm0_default: pwm0_default {
1255		function = "PWM0";
1256		groups = "PWM0";
1257	};
1258
1259	pinctrl_pwm1_default: pwm1_default {
1260		function = "PWM1";
1261		groups = "PWM1";
1262	};
1263
1264	pinctrl_pwm2_default: pwm2_default {
1265		function = "PWM2";
1266		groups = "PWM2";
1267	};
1268
1269	pinctrl_pwm3_default: pwm3_default {
1270		function = "PWM3";
1271		groups = "PWM3";
1272	};
1273
1274	pinctrl_pwm4_default: pwm4_default {
1275		function = "PWM4";
1276		groups = "PWM4";
1277	};
1278
1279	pinctrl_pwm5_default: pwm5_default {
1280		function = "PWM5";
1281		groups = "PWM5";
1282	};
1283
1284	pinctrl_pwm6_default: pwm6_default {
1285		function = "PWM6";
1286		groups = "PWM6";
1287	};
1288
1289	pinctrl_pwm7_default: pwm7_default {
1290		function = "PWM7";
1291		groups = "PWM7";
1292	};
1293
1294	pinctrl_rgmii1_default: rgmii1_default {
1295		function = "RGMII1";
1296		groups = "RGMII1";
1297	};
1298
1299	pinctrl_rgmii2_default: rgmii2_default {
1300		function = "RGMII2";
1301		groups = "RGMII2";
1302	};
1303
1304	pinctrl_rmii1_default: rmii1_default {
1305		function = "RMII1";
1306		groups = "RMII1";
1307	};
1308
1309	pinctrl_rmii2_default: rmii2_default {
1310		function = "RMII2";
1311		groups = "RMII2";
1312	};
1313
1314	pinctrl_rxd1_default: rxd1_default {
1315		function = "RXD1";
1316		groups = "RXD1";
1317	};
1318
1319	pinctrl_rxd2_default: rxd2_default {
1320		function = "RXD2";
1321		groups = "RXD2";
1322	};
1323
1324	pinctrl_rxd3_default: rxd3_default {
1325		function = "RXD3";
1326		groups = "RXD3";
1327	};
1328
1329	pinctrl_rxd4_default: rxd4_default {
1330		function = "RXD4";
1331		groups = "RXD4";
1332	};
1333
1334	pinctrl_salt1_default: salt1_default {
1335		function = "SALT1";
1336		groups = "SALT1";
1337	};
1338
1339	pinctrl_salt10_default: salt10_default {
1340		function = "SALT10";
1341		groups = "SALT10";
1342	};
1343
1344	pinctrl_salt11_default: salt11_default {
1345		function = "SALT11";
1346		groups = "SALT11";
1347	};
1348
1349	pinctrl_salt12_default: salt12_default {
1350		function = "SALT12";
1351		groups = "SALT12";
1352	};
1353
1354	pinctrl_salt13_default: salt13_default {
1355		function = "SALT13";
1356		groups = "SALT13";
1357	};
1358
1359	pinctrl_salt14_default: salt14_default {
1360		function = "SALT14";
1361		groups = "SALT14";
1362	};
1363
1364	pinctrl_salt2_default: salt2_default {
1365		function = "SALT2";
1366		groups = "SALT2";
1367	};
1368
1369	pinctrl_salt3_default: salt3_default {
1370		function = "SALT3";
1371		groups = "SALT3";
1372	};
1373
1374	pinctrl_salt4_default: salt4_default {
1375		function = "SALT4";
1376		groups = "SALT4";
1377	};
1378
1379	pinctrl_salt5_default: salt5_default {
1380		function = "SALT5";
1381		groups = "SALT5";
1382	};
1383
1384	pinctrl_salt6_default: salt6_default {
1385		function = "SALT6";
1386		groups = "SALT6";
1387	};
1388
1389	pinctrl_salt7_default: salt7_default {
1390		function = "SALT7";
1391		groups = "SALT7";
1392	};
1393
1394	pinctrl_salt8_default: salt8_default {
1395		function = "SALT8";
1396		groups = "SALT8";
1397	};
1398
1399	pinctrl_salt9_default: salt9_default {
1400		function = "SALT9";
1401		groups = "SALT9";
1402	};
1403
1404	pinctrl_scl1_default: scl1_default {
1405		function = "SCL1";
1406		groups = "SCL1";
1407	};
1408
1409	pinctrl_scl2_default: scl2_default {
1410		function = "SCL2";
1411		groups = "SCL2";
1412	};
1413
1414	pinctrl_sd1_default: sd1_default {
1415		function = "SD1";
1416		groups = "SD1";
1417	};
1418
1419	pinctrl_sd2_default: sd2_default {
1420		function = "SD2";
1421		groups = "SD2";
1422	};
1423
1424	pinctrl_sda1_default: sda1_default {
1425		function = "SDA1";
1426		groups = "SDA1";
1427	};
1428
1429	pinctrl_sda2_default: sda2_default {
1430		function = "SDA2";
1431		groups = "SDA2";
1432	};
1433
1434	pinctrl_sgpm_default: sgpm_default {
1435		function = "SGPM";
1436		groups = "SGPM";
1437	};
1438
1439	pinctrl_sgps1_default: sgps1_default {
1440		function = "SGPS1";
1441		groups = "SGPS1";
1442	};
1443
1444	pinctrl_sgps2_default: sgps2_default {
1445		function = "SGPS2";
1446		groups = "SGPS2";
1447	};
1448
1449	pinctrl_sioonctrl_default: sioonctrl_default {
1450		function = "SIOONCTRL";
1451		groups = "SIOONCTRL";
1452	};
1453
1454	pinctrl_siopbi_default: siopbi_default {
1455		function = "SIOPBI";
1456		groups = "SIOPBI";
1457	};
1458
1459	pinctrl_siopbo_default: siopbo_default {
1460		function = "SIOPBO";
1461		groups = "SIOPBO";
1462	};
1463
1464	pinctrl_siopwreq_default: siopwreq_default {
1465		function = "SIOPWREQ";
1466		groups = "SIOPWREQ";
1467	};
1468
1469	pinctrl_siopwrgd_default: siopwrgd_default {
1470		function = "SIOPWRGD";
1471		groups = "SIOPWRGD";
1472	};
1473
1474	pinctrl_sios3_default: sios3_default {
1475		function = "SIOS3";
1476		groups = "SIOS3";
1477	};
1478
1479	pinctrl_sios5_default: sios5_default {
1480		function = "SIOS5";
1481		groups = "SIOS5";
1482	};
1483
1484	pinctrl_siosci_default: siosci_default {
1485		function = "SIOSCI";
1486		groups = "SIOSCI";
1487	};
1488
1489	pinctrl_spi1_default: spi1_default {
1490		function = "SPI1";
1491		groups = "SPI1";
1492	};
1493
1494	pinctrl_spi1cs1_default: spi1cs1_default {
1495		function = "SPI1CS1";
1496		groups = "SPI1CS1";
1497	};
1498
1499	pinctrl_spi1debug_default: spi1debug_default {
1500		function = "SPI1DEBUG";
1501		groups = "SPI1DEBUG";
1502	};
1503
1504	pinctrl_spi1passthru_default: spi1passthru_default {
1505		function = "SPI1PASSTHRU";
1506		groups = "SPI1PASSTHRU";
1507	};
1508
1509	pinctrl_spi2ck_default: spi2ck_default {
1510		function = "SPI2CK";
1511		groups = "SPI2CK";
1512	};
1513
1514	pinctrl_spi2cs0_default: spi2cs0_default {
1515		function = "SPI2CS0";
1516		groups = "SPI2CS0";
1517	};
1518
1519	pinctrl_spi2cs1_default: spi2cs1_default {
1520		function = "SPI2CS1";
1521		groups = "SPI2CS1";
1522	};
1523
1524	pinctrl_spi2miso_default: spi2miso_default {
1525		function = "SPI2MISO";
1526		groups = "SPI2MISO";
1527	};
1528
1529	pinctrl_spi2mosi_default: spi2mosi_default {
1530		function = "SPI2MOSI";
1531		groups = "SPI2MOSI";
1532	};
1533
1534	pinctrl_timer3_default: timer3_default {
1535		function = "TIMER3";
1536		groups = "TIMER3";
1537	};
1538
1539	pinctrl_timer4_default: timer4_default {
1540		function = "TIMER4";
1541		groups = "TIMER4";
1542	};
1543
1544	pinctrl_timer5_default: timer5_default {
1545		function = "TIMER5";
1546		groups = "TIMER5";
1547	};
1548
1549	pinctrl_timer6_default: timer6_default {
1550		function = "TIMER6";
1551		groups = "TIMER6";
1552	};
1553
1554	pinctrl_timer7_default: timer7_default {
1555		function = "TIMER7";
1556		groups = "TIMER7";
1557	};
1558
1559	pinctrl_timer8_default: timer8_default {
1560		function = "TIMER8";
1561		groups = "TIMER8";
1562	};
1563
1564	pinctrl_txd1_default: txd1_default {
1565		function = "TXD1";
1566		groups = "TXD1";
1567	};
1568
1569	pinctrl_txd2_default: txd2_default {
1570		function = "TXD2";
1571		groups = "TXD2";
1572	};
1573
1574	pinctrl_txd3_default: txd3_default {
1575		function = "TXD3";
1576		groups = "TXD3";
1577	};
1578
1579	pinctrl_txd4_default: txd4_default {
1580		function = "TXD4";
1581		groups = "TXD4";
1582	};
1583
1584	pinctrl_uart6_default: uart6_default {
1585		function = "UART6";
1586		groups = "UART6";
1587	};
1588
1589	pinctrl_usbcki_default: usbcki_default {
1590		function = "USBCKI";
1591		groups = "USBCKI";
1592	};
1593
1594	pinctrl_usb2ah_default: usb2ah_default {
1595		function = "USB2AH";
1596		groups = "USB2AH";
1597	};
1598
1599	pinctrl_usb2ad_default: usb2ad_default {
1600		function = "USB2AD";
1601		groups = "USB2AD";
1602	};
1603
1604	pinctrl_usb11bhid_default: usb11bhid_default {
1605		function = "USB11BHID";
1606		groups = "USB11BHID";
1607	};
1608
1609	pinctrl_usb2bh_default: usb2bh_default {
1610		function = "USB2BH";
1611		groups = "USB2BH";
1612	};
1613
1614	pinctrl_vgabiosrom_default: vgabiosrom_default {
1615		function = "VGABIOSROM";
1616		groups = "VGABIOSROM";
1617	};
1618
1619	pinctrl_vgahs_default: vgahs_default {
1620		function = "VGAHS";
1621		groups = "VGAHS";
1622	};
1623
1624	pinctrl_vgavs_default: vgavs_default {
1625		function = "VGAVS";
1626		groups = "VGAVS";
1627	};
1628
1629	pinctrl_vpi24_default: vpi24_default {
1630		function = "VPI24";
1631		groups = "VPI24";
1632	};
1633
1634	pinctrl_vpo_default: vpo_default {
1635		function = "VPO";
1636		groups = "VPO";
1637	};
1638
1639	pinctrl_wdtrst1_default: wdtrst1_default {
1640		function = "WDTRST1";
1641		groups = "WDTRST1";
1642	};
1643
1644	pinctrl_wdtrst2_default: wdtrst2_default {
1645		function = "WDTRST2";
1646		groups = "WDTRST2";
1647	};
1648};
1649