1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2400";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm926ej-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@40000000 {
46		device_type = "memory";
47		reg = <0x40000000 0>;
48	};
49
50	ahb {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges;
55
56		fmc: spi@1e620000 {
57			reg = <0x1e620000 0x94>, <0x20000000 0x10000000>;
58			#address-cells = <1>;
59			#size-cells = <0>;
60			compatible = "aspeed,ast2400-fmc";
61			clocks = <&syscon ASPEED_CLK_AHB>;
62			status = "disabled";
63			interrupts = <19>;
64			flash@0 {
65				reg = < 0 >;
66				compatible = "jedec,spi-nor";
67				spi-rx-bus-width = <2>;
68				spi-max-frequency = <50000000>;
69				status = "disabled";
70			};
71			flash@1 {
72				reg = < 1 >;
73				compatible = "jedec,spi-nor";
74				spi-rx-bus-width = <2>;
75				spi-max-frequency = <50000000>;
76				status = "disabled";
77			};
78			flash@2 {
79				reg = < 2 >;
80				compatible = "jedec,spi-nor";
81				spi-rx-bus-width = <2>;
82				spi-max-frequency = <50000000>;
83				status = "disabled";
84			};
85			flash@3 {
86				reg = < 3 >;
87				compatible = "jedec,spi-nor";
88				spi-rx-bus-width = <2>;
89				spi-max-frequency = <50000000>;
90				status = "disabled";
91			};
92			flash@4 {
93				reg = < 4 >;
94				compatible = "jedec,spi-nor";
95				spi-rx-bus-width = <2>;
96				spi-max-frequency = <50000000>;
97				status = "disabled";
98			};
99		};
100
101		spi: spi@1e630000 {
102			reg = <0x1e630000 0x18>, <0x30000000 0x10000000>;
103			#address-cells = <1>;
104			#size-cells = <0>;
105			compatible = "aspeed,ast2400-spi";
106			clocks = <&syscon ASPEED_CLK_AHB>;
107			status = "disabled";
108			flash@0 {
109				reg = < 0 >;
110				compatible = "jedec,spi-nor";
111				spi-max-frequency = <50000000>;
112				spi-rx-bus-width = <2>;
113				status = "disabled";
114			};
115		};
116
117		vic: interrupt-controller@1e6c0080 {
118			compatible = "aspeed,ast2400-vic";
119			interrupt-controller;
120			#interrupt-cells = <1>;
121			valid-sources = <0xffffffff 0x0007ffff>;
122			reg = <0x1e6c0080 0x80>;
123		};
124
125		cvic: copro-interrupt-controller@1e6c2000 {
126			compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
127			valid-sources = <0x7fffffff>;
128			reg = <0x1e6c2000 0x80>;
129		};
130
131		mac0: ethernet@1e660000 {
132			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
133			reg = <0x1e660000 0x180>;
134			interrupts = <2>;
135			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
136			status = "disabled";
137		};
138
139		mac1: ethernet@1e680000 {
140			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
141			reg = <0x1e680000 0x180>;
142			interrupts = <3>;
143			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
144			status = "disabled";
145		};
146
147		ehci0: usb@1e6a1000 {
148			compatible = "aspeed,ast2400-ehci", "generic-ehci";
149			reg = <0x1e6a1000 0x100>;
150			interrupts = <5>;
151			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
152			pinctrl-names = "default";
153			pinctrl-0 = <&pinctrl_usb2h_default>;
154			status = "disabled";
155		};
156
157		uhci: usb@1e6b0000 {
158			compatible = "aspeed,ast2400-uhci", "generic-uhci";
159			reg = <0x1e6b0000 0x100>;
160			interrupts = <14>;
161			#ports = <3>;
162			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
163			status = "disabled";
164			/*
165			 * No default pinmux, it will follow EHCI, use an explicit pinmux
166			 * override if you don't enable EHCI
167			 */
168		};
169
170		vhub: usb-vhub@1e6a0000 {
171			compatible = "aspeed,ast2400-usb-vhub";
172			reg = <0x1e6a0000 0x300>;
173			interrupts = <5>;
174			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
175			aspeed,vhub-downstream-ports = <5>;
176			aspeed,vhub-generic-endpoints = <15>;
177			pinctrl-names = "default";
178			pinctrl-0 = <&pinctrl_usb2d_default>;
179			status = "disabled";
180		};
181
182		apb {
183			compatible = "simple-bus";
184			#address-cells = <1>;
185			#size-cells = <1>;
186			ranges;
187
188			syscon: syscon@1e6e2000 {
189				compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
190				reg = <0x1e6e2000 0x1a8>;
191				#address-cells = <1>;
192				#size-cells = <1>;
193				ranges = <0 0x1e6e2000 0x1000>;
194				#clock-cells = <1>;
195				#reset-cells = <1>;
196
197				p2a: p2a-control@2c {
198					reg = <0x2c 0x4>;
199					compatible = "aspeed,ast2400-p2a-ctrl";
200					status = "disabled";
201				};
202
203				silicon-id@7c {
204					compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
205					reg = <0x7c 0x4>;
206				};
207
208				pinctrl: pinctrl@80 {
209					reg = <0x80 0x18>, <0xa0 0x10>;
210					compatible = "aspeed,ast2400-pinctrl";
211				};
212			};
213
214			rng: hwrng@1e6e2078 {
215				compatible = "timeriomem_rng";
216				reg = <0x1e6e2078 0x4>;
217				period = <1>;
218				quality = <100>;
219			};
220
221			adc: adc@1e6e9000 {
222				compatible = "aspeed,ast2400-adc";
223				reg = <0x1e6e9000 0xb0>;
224				clocks = <&syscon ASPEED_CLK_APB>;
225				resets = <&syscon ASPEED_RESET_ADC>;
226				#io-channel-cells = <1>;
227				status = "disabled";
228			};
229
230			sram: sram@1e720000 {
231				compatible = "mmio-sram";
232				reg = <0x1e720000 0x8000>;	// 32K
233			};
234
235			video: video@1e700000 {
236				compatible = "aspeed,ast2400-video-engine";
237				reg = <0x1e700000 0x1000>;
238				clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
239					 <&syscon ASPEED_CLK_GATE_ECLK>;
240				clock-names = "vclk", "eclk";
241				interrupts = <7>;
242				status = "disabled";
243			};
244
245			sdmmc: sd-controller@1e740000 {
246				compatible = "aspeed,ast2400-sd-controller";
247				reg = <0x1e740000 0x100>;
248				#address-cells = <1>;
249				#size-cells = <1>;
250				ranges = <0 0x1e740000 0x10000>;
251				clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
252				status = "disabled";
253
254				sdhci0: sdhci@100 {
255					compatible = "aspeed,ast2400-sdhci";
256					reg = <0x100 0x100>;
257					interrupts = <26>;
258					sdhci,auto-cmd12;
259					clocks = <&syscon ASPEED_CLK_SDIO>;
260					status = "disabled";
261				};
262
263				sdhci1: sdhci@200 {
264					compatible = "aspeed,ast2400-sdhci";
265					reg = <0x200 0x100>;
266					interrupts = <26>;
267					sdhci,auto-cmd12;
268					clocks = <&syscon ASPEED_CLK_SDIO>;
269					status = "disabled";
270				};
271			};
272
273			gpio: gpio@1e780000 {
274				#gpio-cells = <2>;
275				gpio-controller;
276				compatible = "aspeed,ast2400-gpio";
277				reg = <0x1e780000 0x1000>;
278				interrupts = <20>;
279				gpio-ranges = <&pinctrl 0 0 220>;
280				clocks = <&syscon ASPEED_CLK_APB>;
281				interrupt-controller;
282				#interrupt-cells = <2>;
283			};
284
285			timer: timer@1e782000 {
286				/* This timer is a Faraday FTTMR010 derivative */
287				compatible = "aspeed,ast2400-timer";
288				reg = <0x1e782000 0x90>;
289				interrupts = <16 17 18 35 36 37 38 39>;
290				clocks = <&syscon ASPEED_CLK_APB>;
291				clock-names = "PCLK";
292			};
293
294			rtc: rtc@1e781000 {
295				compatible = "aspeed,ast2400-rtc";
296				reg = <0x1e781000 0x18>;
297				status = "disabled";
298			};
299
300			uart1: serial@1e783000 {
301				compatible = "ns16550a";
302				reg = <0x1e783000 0x20>;
303				reg-shift = <2>;
304				interrupts = <9>;
305				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
306				resets = <&lpc_reset 4>;
307				no-loopback-test;
308				status = "disabled";
309			};
310
311			uart5: serial@1e784000 {
312				compatible = "ns16550a";
313				reg = <0x1e784000 0x20>;
314				reg-shift = <2>;
315				interrupts = <10>;
316				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
317				no-loopback-test;
318				status = "disabled";
319			};
320
321			wdt1: watchdog@1e785000 {
322				compatible = "aspeed,ast2400-wdt";
323				reg = <0x1e785000 0x1c>;
324				clocks = <&syscon ASPEED_CLK_APB>;
325			};
326
327			wdt2: watchdog@1e785020 {
328				compatible = "aspeed,ast2400-wdt";
329				reg = <0x1e785020 0x1c>;
330				clocks = <&syscon ASPEED_CLK_APB>;
331			};
332
333			pwm_tacho: pwm-tacho-controller@1e786000 {
334				compatible = "aspeed,ast2400-pwm-tacho";
335				#address-cells = <1>;
336				#size-cells = <0>;
337				reg = <0x1e786000 0x1000>;
338				clocks = <&syscon ASPEED_CLK_24M>;
339				resets = <&syscon ASPEED_RESET_PWM>;
340				status = "disabled";
341			};
342
343			vuart: serial@1e787000 {
344				compatible = "aspeed,ast2400-vuart";
345				reg = <0x1e787000 0x40>;
346				reg-shift = <2>;
347				interrupts = <8>;
348				clocks = <&syscon ASPEED_CLK_APB>;
349				no-loopback-test;
350				status = "disabled";
351			};
352
353			lpc: lpc@1e789000 {
354				compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
355				reg = <0x1e789000 0x1000>;
356				reg-io-width = <4>;
357
358				#address-cells = <1>;
359				#size-cells = <1>;
360				ranges = <0x0 0x1e789000 0x1000>;
361
362				lpc_ctrl: lpc-ctrl@80 {
363					compatible = "aspeed,ast2400-lpc-ctrl";
364					reg = <0x80 0x10>;
365					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
366					status = "disabled";
367				};
368
369				lpc_snoop: lpc-snoop@90 {
370					compatible = "aspeed,ast2400-lpc-snoop";
371					reg = <0x90 0x8>;
372					interrupts = <8>;
373					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
374					status = "disabled";
375				};
376
377				lhc: lhc@a0 {
378					compatible = "aspeed,ast2400-lhc";
379					reg = <0xa0 0x24 0xc8 0x8>;
380				};
381
382				lpc_reset: reset-controller@98 {
383					compatible = "aspeed,ast2400-lpc-reset";
384					reg = <0x98 0x4>;
385					#reset-cells = <1>;
386				};
387
388				ibt: ibt@140 {
389					compatible = "aspeed,ast2400-ibt-bmc";
390					reg = <0x140 0x18>;
391					interrupts = <8>;
392					clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
393					status = "disabled";
394				};
395
396				uart_routing: uart-routing@9c {
397					compatible = "aspeed,ast2400-uart-routing";
398					reg = <0x9c 0x4>;
399					status = "disabled";
400				};
401			};
402
403			peci0: peci-controller@1e78b000 {
404				compatible = "aspeed,ast2400-peci";
405				reg = <0x1e78b000 0x60>;
406				interrupts = <15>;
407				clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
408				resets = <&syscon ASPEED_RESET_PECI>;
409				cmd-timeout-ms = <1000>;
410				clock-frequency = <1000000>;
411				status = "disabled";
412			};
413
414			uart2: serial@1e78d000 {
415				compatible = "ns16550a";
416				reg = <0x1e78d000 0x20>;
417				reg-shift = <2>;
418				interrupts = <32>;
419				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
420				resets = <&lpc_reset 5>;
421				no-loopback-test;
422				status = "disabled";
423			};
424
425			uart3: serial@1e78e000 {
426				compatible = "ns16550a";
427				reg = <0x1e78e000 0x20>;
428				reg-shift = <2>;
429				interrupts = <33>;
430				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
431				resets = <&lpc_reset 6>;
432				no-loopback-test;
433				status = "disabled";
434			};
435
436			uart4: serial@1e78f000 {
437				compatible = "ns16550a";
438				reg = <0x1e78f000 0x20>;
439				reg-shift = <2>;
440				interrupts = <34>;
441				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
442				resets = <&lpc_reset 7>;
443				no-loopback-test;
444				status = "disabled";
445			};
446
447			i2c: bus@1e78a000 {
448				compatible = "simple-bus";
449				#address-cells = <1>;
450				#size-cells = <1>;
451				ranges = <0 0x1e78a000 0x1000>;
452			};
453		};
454	};
455};
456
457&i2c {
458	i2c_ic: interrupt-controller@0 {
459		#interrupt-cells = <1>;
460		compatible = "aspeed,ast2400-i2c-ic";
461		reg = <0x0 0x40>;
462		interrupts = <12>;
463		interrupt-controller;
464	};
465
466	i2c0: i2c-bus@40 {
467		#address-cells = <1>;
468		#size-cells = <0>;
469
470		reg = <0x40 0x40>;
471		compatible = "aspeed,ast2400-i2c-bus";
472		clocks = <&syscon ASPEED_CLK_APB>;
473		resets = <&syscon ASPEED_RESET_I2C>;
474		bus-frequency = <100000>;
475		interrupts = <0>;
476		interrupt-parent = <&i2c_ic>;
477		status = "disabled";
478		/* Does not need pinctrl properties */
479	};
480
481	i2c1: i2c-bus@80 {
482		#address-cells = <1>;
483		#size-cells = <0>;
484
485		reg = <0x80 0x40>;
486		compatible = "aspeed,ast2400-i2c-bus";
487		clocks = <&syscon ASPEED_CLK_APB>;
488		resets = <&syscon ASPEED_RESET_I2C>;
489		bus-frequency = <100000>;
490		interrupts = <1>;
491		interrupt-parent = <&i2c_ic>;
492		status = "disabled";
493		/* Does not need pinctrl properties */
494	};
495
496	i2c2: i2c-bus@c0 {
497		#address-cells = <1>;
498		#size-cells = <0>;
499
500		reg = <0xc0 0x40>;
501		compatible = "aspeed,ast2400-i2c-bus";
502		clocks = <&syscon ASPEED_CLK_APB>;
503		resets = <&syscon ASPEED_RESET_I2C>;
504		bus-frequency = <100000>;
505		interrupts = <2>;
506		interrupt-parent = <&i2c_ic>;
507		pinctrl-names = "default";
508		pinctrl-0 = <&pinctrl_i2c3_default>;
509		status = "disabled";
510	};
511
512	i2c3: i2c-bus@100 {
513		#address-cells = <1>;
514		#size-cells = <0>;
515
516		reg = <0x100 0x40>;
517		compatible = "aspeed,ast2400-i2c-bus";
518		clocks = <&syscon ASPEED_CLK_APB>;
519		resets = <&syscon ASPEED_RESET_I2C>;
520		bus-frequency = <100000>;
521		interrupts = <3>;
522		interrupt-parent = <&i2c_ic>;
523		pinctrl-names = "default";
524		pinctrl-0 = <&pinctrl_i2c4_default>;
525		status = "disabled";
526	};
527
528	i2c4: i2c-bus@140 {
529		#address-cells = <1>;
530		#size-cells = <0>;
531
532		reg = <0x140 0x40>;
533		compatible = "aspeed,ast2400-i2c-bus";
534		clocks = <&syscon ASPEED_CLK_APB>;
535		resets = <&syscon ASPEED_RESET_I2C>;
536		bus-frequency = <100000>;
537		interrupts = <4>;
538		interrupt-parent = <&i2c_ic>;
539		pinctrl-names = "default";
540		pinctrl-0 = <&pinctrl_i2c5_default>;
541		status = "disabled";
542	};
543
544	i2c5: i2c-bus@180 {
545		#address-cells = <1>;
546		#size-cells = <0>;
547
548		reg = <0x180 0x40>;
549		compatible = "aspeed,ast2400-i2c-bus";
550		clocks = <&syscon ASPEED_CLK_APB>;
551		resets = <&syscon ASPEED_RESET_I2C>;
552		bus-frequency = <100000>;
553		interrupts = <5>;
554		interrupt-parent = <&i2c_ic>;
555		pinctrl-names = "default";
556		pinctrl-0 = <&pinctrl_i2c6_default>;
557		status = "disabled";
558	};
559
560	i2c6: i2c-bus@1c0 {
561		#address-cells = <1>;
562		#size-cells = <0>;
563
564		reg = <0x1c0 0x40>;
565		compatible = "aspeed,ast2400-i2c-bus";
566		clocks = <&syscon ASPEED_CLK_APB>;
567		resets = <&syscon ASPEED_RESET_I2C>;
568		bus-frequency = <100000>;
569		interrupts = <6>;
570		interrupt-parent = <&i2c_ic>;
571		pinctrl-names = "default";
572		pinctrl-0 = <&pinctrl_i2c7_default>;
573		status = "disabled";
574	};
575
576	i2c7: i2c-bus@300 {
577		#address-cells = <1>;
578		#size-cells = <0>;
579
580		reg = <0x300 0x40>;
581		compatible = "aspeed,ast2400-i2c-bus";
582		clocks = <&syscon ASPEED_CLK_APB>;
583		resets = <&syscon ASPEED_RESET_I2C>;
584		bus-frequency = <100000>;
585		interrupts = <7>;
586		interrupt-parent = <&i2c_ic>;
587		pinctrl-names = "default";
588		pinctrl-0 = <&pinctrl_i2c8_default>;
589		status = "disabled";
590	};
591
592	i2c8: i2c-bus@340 {
593		#address-cells = <1>;
594		#size-cells = <0>;
595
596		reg = <0x340 0x40>;
597		compatible = "aspeed,ast2400-i2c-bus";
598		clocks = <&syscon ASPEED_CLK_APB>;
599		resets = <&syscon ASPEED_RESET_I2C>;
600		bus-frequency = <100000>;
601		interrupts = <8>;
602		interrupt-parent = <&i2c_ic>;
603		pinctrl-names = "default";
604		pinctrl-0 = <&pinctrl_i2c9_default>;
605		status = "disabled";
606	};
607
608	i2c9: i2c-bus@380 {
609		#address-cells = <1>;
610		#size-cells = <0>;
611
612		reg = <0x380 0x40>;
613		compatible = "aspeed,ast2400-i2c-bus";
614		clocks = <&syscon ASPEED_CLK_APB>;
615		resets = <&syscon ASPEED_RESET_I2C>;
616		bus-frequency = <100000>;
617		interrupts = <9>;
618		interrupt-parent = <&i2c_ic>;
619		pinctrl-names = "default";
620		pinctrl-0 = <&pinctrl_i2c10_default>;
621		status = "disabled";
622	};
623
624	i2c10: i2c-bus@3c0 {
625		#address-cells = <1>;
626		#size-cells = <0>;
627
628		reg = <0x3c0 0x40>;
629		compatible = "aspeed,ast2400-i2c-bus";
630		clocks = <&syscon ASPEED_CLK_APB>;
631		resets = <&syscon ASPEED_RESET_I2C>;
632		bus-frequency = <100000>;
633		interrupts = <10>;
634		interrupt-parent = <&i2c_ic>;
635		pinctrl-names = "default";
636		pinctrl-0 = <&pinctrl_i2c11_default>;
637		status = "disabled";
638	};
639
640	i2c11: i2c-bus@400 {
641		#address-cells = <1>;
642		#size-cells = <0>;
643
644		reg = <0x400 0x40>;
645		compatible = "aspeed,ast2400-i2c-bus";
646		clocks = <&syscon ASPEED_CLK_APB>;
647		resets = <&syscon ASPEED_RESET_I2C>;
648		bus-frequency = <100000>;
649		interrupts = <11>;
650		interrupt-parent = <&i2c_ic>;
651		pinctrl-names = "default";
652		pinctrl-0 = <&pinctrl_i2c12_default>;
653		status = "disabled";
654	};
655
656	i2c12: i2c-bus@440 {
657		#address-cells = <1>;
658		#size-cells = <0>;
659
660		reg = <0x440 0x40>;
661		compatible = "aspeed,ast2400-i2c-bus";
662		clocks = <&syscon ASPEED_CLK_APB>;
663		resets = <&syscon ASPEED_RESET_I2C>;
664		bus-frequency = <100000>;
665		interrupts = <12>;
666		interrupt-parent = <&i2c_ic>;
667		pinctrl-names = "default";
668		pinctrl-0 = <&pinctrl_i2c13_default>;
669		status = "disabled";
670	};
671
672	i2c13: i2c-bus@480 {
673		#address-cells = <1>;
674		#size-cells = <0>;
675
676		reg = <0x480 0x40>;
677		compatible = "aspeed,ast2400-i2c-bus";
678		clocks = <&syscon ASPEED_CLK_APB>;
679		resets = <&syscon ASPEED_RESET_I2C>;
680		bus-frequency = <100000>;
681		interrupts = <13>;
682		interrupt-parent = <&i2c_ic>;
683		pinctrl-names = "default";
684		pinctrl-0 = <&pinctrl_i2c14_default>;
685		status = "disabled";
686	};
687};
688
689&pinctrl {
690	pinctrl_acpi_default: acpi_default {
691		function = "ACPI";
692		groups = "ACPI";
693	};
694
695	pinctrl_adc0_default: adc0_default {
696		function = "ADC0";
697		groups = "ADC0";
698	};
699
700	pinctrl_adc1_default: adc1_default {
701		function = "ADC1";
702		groups = "ADC1";
703	};
704
705	pinctrl_adc10_default: adc10_default {
706		function = "ADC10";
707		groups = "ADC10";
708	};
709
710	pinctrl_adc11_default: adc11_default {
711		function = "ADC11";
712		groups = "ADC11";
713	};
714
715	pinctrl_adc12_default: adc12_default {
716		function = "ADC12";
717		groups = "ADC12";
718	};
719
720	pinctrl_adc13_default: adc13_default {
721		function = "ADC13";
722		groups = "ADC13";
723	};
724
725	pinctrl_adc14_default: adc14_default {
726		function = "ADC14";
727		groups = "ADC14";
728	};
729
730	pinctrl_adc15_default: adc15_default {
731		function = "ADC15";
732		groups = "ADC15";
733	};
734
735	pinctrl_adc2_default: adc2_default {
736		function = "ADC2";
737		groups = "ADC2";
738	};
739
740	pinctrl_adc3_default: adc3_default {
741		function = "ADC3";
742		groups = "ADC3";
743	};
744
745	pinctrl_adc4_default: adc4_default {
746		function = "ADC4";
747		groups = "ADC4";
748	};
749
750	pinctrl_adc5_default: adc5_default {
751		function = "ADC5";
752		groups = "ADC5";
753	};
754
755	pinctrl_adc6_default: adc6_default {
756		function = "ADC6";
757		groups = "ADC6";
758	};
759
760	pinctrl_adc7_default: adc7_default {
761		function = "ADC7";
762		groups = "ADC7";
763	};
764
765	pinctrl_adc8_default: adc8_default {
766		function = "ADC8";
767		groups = "ADC8";
768	};
769
770	pinctrl_adc9_default: adc9_default {
771		function = "ADC9";
772		groups = "ADC9";
773	};
774
775	pinctrl_bmcint_default: bmcint_default {
776		function = "BMCINT";
777		groups = "BMCINT";
778	};
779
780	pinctrl_ddcclk_default: ddcclk_default {
781		function = "DDCCLK";
782		groups = "DDCCLK";
783	};
784
785	pinctrl_ddcdat_default: ddcdat_default {
786		function = "DDCDAT";
787		groups = "DDCDAT";
788	};
789
790	pinctrl_extrst_default: extrst_default {
791		function = "EXTRST";
792		groups = "EXTRST";
793	};
794
795	pinctrl_flack_default: flack_default {
796		function = "FLACK";
797		groups = "FLACK";
798	};
799
800	pinctrl_flbusy_default: flbusy_default {
801		function = "FLBUSY";
802		groups = "FLBUSY";
803	};
804
805	pinctrl_flwp_default: flwp_default {
806		function = "FLWP";
807		groups = "FLWP";
808	};
809
810	pinctrl_gpid_default: gpid_default {
811		function = "GPID";
812		groups = "GPID";
813	};
814
815	pinctrl_gpid0_default: gpid0_default {
816		function = "GPID0";
817		groups = "GPID0";
818	};
819
820	pinctrl_gpid2_default: gpid2_default {
821		function = "GPID2";
822		groups = "GPID2";
823	};
824
825	pinctrl_gpid4_default: gpid4_default {
826		function = "GPID4";
827		groups = "GPID4";
828	};
829
830	pinctrl_gpid6_default: gpid6_default {
831		function = "GPID6";
832		groups = "GPID6";
833	};
834
835	pinctrl_gpie0_default: gpie0_default {
836		function = "GPIE0";
837		groups = "GPIE0";
838	};
839
840	pinctrl_gpie2_default: gpie2_default {
841		function = "GPIE2";
842		groups = "GPIE2";
843	};
844
845	pinctrl_gpie4_default: gpie4_default {
846		function = "GPIE4";
847		groups = "GPIE4";
848	};
849
850	pinctrl_gpie6_default: gpie6_default {
851		function = "GPIE6";
852		groups = "GPIE6";
853	};
854
855	pinctrl_i2c10_default: i2c10_default {
856		function = "I2C10";
857		groups = "I2C10";
858	};
859
860	pinctrl_i2c11_default: i2c11_default {
861		function = "I2C11";
862		groups = "I2C11";
863	};
864
865	pinctrl_i2c12_default: i2c12_default {
866		function = "I2C12";
867		groups = "I2C12";
868	};
869
870	pinctrl_i2c13_default: i2c13_default {
871		function = "I2C13";
872		groups = "I2C13";
873	};
874
875	pinctrl_i2c14_default: i2c14_default {
876		function = "I2C14";
877		groups = "I2C14";
878	};
879
880	pinctrl_i2c3_default: i2c3_default {
881		function = "I2C3";
882		groups = "I2C3";
883	};
884
885	pinctrl_i2c4_default: i2c4_default {
886		function = "I2C4";
887		groups = "I2C4";
888	};
889
890	pinctrl_i2c5_default: i2c5_default {
891		function = "I2C5";
892		groups = "I2C5";
893	};
894
895	pinctrl_i2c6_default: i2c6_default {
896		function = "I2C6";
897		groups = "I2C6";
898	};
899
900	pinctrl_i2c7_default: i2c7_default {
901		function = "I2C7";
902		groups = "I2C7";
903	};
904
905	pinctrl_i2c8_default: i2c8_default {
906		function = "I2C8";
907		groups = "I2C8";
908	};
909
910	pinctrl_i2c9_default: i2c9_default {
911		function = "I2C9";
912		groups = "I2C9";
913	};
914
915	pinctrl_lpcpd_default: lpcpd_default {
916		function = "LPCPD";
917		groups = "LPCPD";
918	};
919
920	pinctrl_lpcpme_default: lpcpme_default {
921		function = "LPCPME";
922		groups = "LPCPME";
923	};
924
925	pinctrl_lpcrst_default: lpcrst_default {
926		function = "LPCRST";
927		groups = "LPCRST";
928	};
929
930	pinctrl_lpcsmi_default: lpcsmi_default {
931		function = "LPCSMI";
932		groups = "LPCSMI";
933	};
934
935	pinctrl_mac1link_default: mac1link_default {
936		function = "MAC1LINK";
937		groups = "MAC1LINK";
938	};
939
940	pinctrl_mac2link_default: mac2link_default {
941		function = "MAC2LINK";
942		groups = "MAC2LINK";
943	};
944
945	pinctrl_mdio1_default: mdio1_default {
946		function = "MDIO1";
947		groups = "MDIO1";
948	};
949
950	pinctrl_mdio2_default: mdio2_default {
951		function = "MDIO2";
952		groups = "MDIO2";
953	};
954
955	pinctrl_ncts1_default: ncts1_default {
956		function = "NCTS1";
957		groups = "NCTS1";
958	};
959
960	pinctrl_ncts2_default: ncts2_default {
961		function = "NCTS2";
962		groups = "NCTS2";
963	};
964
965	pinctrl_ncts3_default: ncts3_default {
966		function = "NCTS3";
967		groups = "NCTS3";
968	};
969
970	pinctrl_ncts4_default: ncts4_default {
971		function = "NCTS4";
972		groups = "NCTS4";
973	};
974
975	pinctrl_ndcd1_default: ndcd1_default {
976		function = "NDCD1";
977		groups = "NDCD1";
978	};
979
980	pinctrl_ndcd2_default: ndcd2_default {
981		function = "NDCD2";
982		groups = "NDCD2";
983	};
984
985	pinctrl_ndcd3_default: ndcd3_default {
986		function = "NDCD3";
987		groups = "NDCD3";
988	};
989
990	pinctrl_ndcd4_default: ndcd4_default {
991		function = "NDCD4";
992		groups = "NDCD4";
993	};
994
995	pinctrl_ndsr1_default: ndsr1_default {
996		function = "NDSR1";
997		groups = "NDSR1";
998	};
999
1000	pinctrl_ndsr2_default: ndsr2_default {
1001		function = "NDSR2";
1002		groups = "NDSR2";
1003	};
1004
1005	pinctrl_ndsr3_default: ndsr3_default {
1006		function = "NDSR3";
1007		groups = "NDSR3";
1008	};
1009
1010	pinctrl_ndsr4_default: ndsr4_default {
1011		function = "NDSR4";
1012		groups = "NDSR4";
1013	};
1014
1015	pinctrl_ndtr1_default: ndtr1_default {
1016		function = "NDTR1";
1017		groups = "NDTR1";
1018	};
1019
1020	pinctrl_ndtr2_default: ndtr2_default {
1021		function = "NDTR2";
1022		groups = "NDTR2";
1023	};
1024
1025	pinctrl_ndtr3_default: ndtr3_default {
1026		function = "NDTR3";
1027		groups = "NDTR3";
1028	};
1029
1030	pinctrl_ndtr4_default: ndtr4_default {
1031		function = "NDTR4";
1032		groups = "NDTR4";
1033	};
1034
1035	pinctrl_ndts4_default: ndts4_default {
1036		function = "NDTS4";
1037		groups = "NDTS4";
1038	};
1039
1040	pinctrl_nri1_default: nri1_default {
1041		function = "NRI1";
1042		groups = "NRI1";
1043	};
1044
1045	pinctrl_nri2_default: nri2_default {
1046		function = "NRI2";
1047		groups = "NRI2";
1048	};
1049
1050	pinctrl_nri3_default: nri3_default {
1051		function = "NRI3";
1052		groups = "NRI3";
1053	};
1054
1055	pinctrl_nri4_default: nri4_default {
1056		function = "NRI4";
1057		groups = "NRI4";
1058	};
1059
1060	pinctrl_nrts1_default: nrts1_default {
1061		function = "NRTS1";
1062		groups = "NRTS1";
1063	};
1064
1065	pinctrl_nrts2_default: nrts2_default {
1066		function = "NRTS2";
1067		groups = "NRTS2";
1068	};
1069
1070	pinctrl_nrts3_default: nrts3_default {
1071		function = "NRTS3";
1072		groups = "NRTS3";
1073	};
1074
1075	pinctrl_oscclk_default: oscclk_default {
1076		function = "OSCCLK";
1077		groups = "OSCCLK";
1078	};
1079
1080	pinctrl_pwm0_default: pwm0_default {
1081		function = "PWM0";
1082		groups = "PWM0";
1083	};
1084
1085	pinctrl_pwm1_default: pwm1_default {
1086		function = "PWM1";
1087		groups = "PWM1";
1088	};
1089
1090	pinctrl_pwm2_default: pwm2_default {
1091		function = "PWM2";
1092		groups = "PWM2";
1093	};
1094
1095	pinctrl_pwm3_default: pwm3_default {
1096		function = "PWM3";
1097		groups = "PWM3";
1098	};
1099
1100	pinctrl_pwm4_default: pwm4_default {
1101		function = "PWM4";
1102		groups = "PWM4";
1103	};
1104
1105	pinctrl_pwm5_default: pwm5_default {
1106		function = "PWM5";
1107		groups = "PWM5";
1108	};
1109
1110	pinctrl_pwm6_default: pwm6_default {
1111		function = "PWM6";
1112		groups = "PWM6";
1113	};
1114
1115	pinctrl_pwm7_default: pwm7_default {
1116		function = "PWM7";
1117		groups = "PWM7";
1118	};
1119
1120	pinctrl_rgmii1_default: rgmii1_default {
1121		function = "RGMII1";
1122		groups = "RGMII1";
1123	};
1124
1125	pinctrl_rgmii2_default: rgmii2_default {
1126		function = "RGMII2";
1127		groups = "RGMII2";
1128	};
1129
1130	pinctrl_rmii1_default: rmii1_default {
1131		function = "RMII1";
1132		groups = "RMII1";
1133	};
1134
1135	pinctrl_rmii2_default: rmii2_default {
1136		function = "RMII2";
1137		groups = "RMII2";
1138	};
1139
1140	pinctrl_rom16_default: rom16_default {
1141		function = "ROM16";
1142		groups = "ROM16";
1143	};
1144
1145	pinctrl_rom8_default: rom8_default {
1146		function = "ROM8";
1147		groups = "ROM8";
1148	};
1149
1150	pinctrl_romcs1_default: romcs1_default {
1151		function = "ROMCS1";
1152		groups = "ROMCS1";
1153	};
1154
1155	pinctrl_romcs2_default: romcs2_default {
1156		function = "ROMCS2";
1157		groups = "ROMCS2";
1158	};
1159
1160	pinctrl_romcs3_default: romcs3_default {
1161		function = "ROMCS3";
1162		groups = "ROMCS3";
1163	};
1164
1165	pinctrl_romcs4_default: romcs4_default {
1166		function = "ROMCS4";
1167		groups = "ROMCS4";
1168	};
1169
1170	pinctrl_rxd1_default: rxd1_default {
1171		function = "RXD1";
1172		groups = "RXD1";
1173	};
1174
1175	pinctrl_rxd2_default: rxd2_default {
1176		function = "RXD2";
1177		groups = "RXD2";
1178	};
1179
1180	pinctrl_rxd3_default: rxd3_default {
1181		function = "RXD3";
1182		groups = "RXD3";
1183	};
1184
1185	pinctrl_rxd4_default: rxd4_default {
1186		function = "RXD4";
1187		groups = "RXD4";
1188	};
1189
1190	pinctrl_salt1_default: salt1_default {
1191		function = "SALT1";
1192		groups = "SALT1";
1193	};
1194
1195	pinctrl_salt2_default: salt2_default {
1196		function = "SALT2";
1197		groups = "SALT2";
1198	};
1199
1200	pinctrl_salt3_default: salt3_default {
1201		function = "SALT3";
1202		groups = "SALT3";
1203	};
1204
1205	pinctrl_salt4_default: salt4_default {
1206		function = "SALT4";
1207		groups = "SALT4";
1208	};
1209
1210	pinctrl_sd1_default: sd1_default {
1211		function = "SD1";
1212		groups = "SD1";
1213	};
1214
1215	pinctrl_sd2_default: sd2_default {
1216		function = "SD2";
1217		groups = "SD2";
1218	};
1219
1220	pinctrl_sgpmck_default: sgpmck_default {
1221		function = "SGPMCK";
1222		groups = "SGPMCK";
1223	};
1224
1225	pinctrl_sgpmi_default: sgpmi_default {
1226		function = "SGPMI";
1227		groups = "SGPMI";
1228	};
1229
1230	pinctrl_sgpmld_default: sgpmld_default {
1231		function = "SGPMLD";
1232		groups = "SGPMLD";
1233	};
1234
1235	pinctrl_sgpmo_default: sgpmo_default {
1236		function = "SGPMO";
1237		groups = "SGPMO";
1238	};
1239
1240	pinctrl_sgpsck_default: sgpsck_default {
1241		function = "SGPSCK";
1242		groups = "SGPSCK";
1243	};
1244
1245	pinctrl_sgpsi0_default: sgpsi0_default {
1246		function = "SGPSI0";
1247		groups = "SGPSI0";
1248	};
1249
1250	pinctrl_sgpsi1_default: sgpsi1_default {
1251		function = "SGPSI1";
1252		groups = "SGPSI1";
1253	};
1254
1255	pinctrl_sgpsld_default: sgpsld_default {
1256		function = "SGPSLD";
1257		groups = "SGPSLD";
1258	};
1259
1260	pinctrl_sioonctrl_default: sioonctrl_default {
1261		function = "SIOONCTRL";
1262		groups = "SIOONCTRL";
1263	};
1264
1265	pinctrl_siopbi_default: siopbi_default {
1266		function = "SIOPBI";
1267		groups = "SIOPBI";
1268	};
1269
1270	pinctrl_siopbo_default: siopbo_default {
1271		function = "SIOPBO";
1272		groups = "SIOPBO";
1273	};
1274
1275	pinctrl_siopwreq_default: siopwreq_default {
1276		function = "SIOPWREQ";
1277		groups = "SIOPWREQ";
1278	};
1279
1280	pinctrl_siopwrgd_default: siopwrgd_default {
1281		function = "SIOPWRGD";
1282		groups = "SIOPWRGD";
1283	};
1284
1285	pinctrl_sios3_default: sios3_default {
1286		function = "SIOS3";
1287		groups = "SIOS3";
1288	};
1289
1290	pinctrl_sios5_default: sios5_default {
1291		function = "SIOS5";
1292		groups = "SIOS5";
1293	};
1294
1295	pinctrl_siosci_default: siosci_default {
1296		function = "SIOSCI";
1297		groups = "SIOSCI";
1298	};
1299
1300	pinctrl_spi1_default: spi1_default {
1301		function = "SPI1";
1302		groups = "SPI1";
1303	};
1304
1305	pinctrl_spi1debug_default: spi1debug_default {
1306		function = "SPI1DEBUG";
1307		groups = "SPI1DEBUG";
1308	};
1309
1310	pinctrl_spi1passthru_default: spi1passthru_default {
1311		function = "SPI1PASSTHRU";
1312		groups = "SPI1PASSTHRU";
1313	};
1314
1315	pinctrl_spics1_default: spics1_default {
1316		function = "SPICS1";
1317		groups = "SPICS1";
1318	};
1319
1320	pinctrl_timer3_default: timer3_default {
1321		function = "TIMER3";
1322		groups = "TIMER3";
1323	};
1324
1325	pinctrl_timer4_default: timer4_default {
1326		function = "TIMER4";
1327		groups = "TIMER4";
1328	};
1329
1330	pinctrl_timer5_default: timer5_default {
1331		function = "TIMER5";
1332		groups = "TIMER5";
1333	};
1334
1335	pinctrl_timer6_default: timer6_default {
1336		function = "TIMER6";
1337		groups = "TIMER6";
1338	};
1339
1340	pinctrl_timer7_default: timer7_default {
1341		function = "TIMER7";
1342		groups = "TIMER7";
1343	};
1344
1345	pinctrl_timer8_default: timer8_default {
1346		function = "TIMER8";
1347		groups = "TIMER8";
1348	};
1349
1350	pinctrl_txd1_default: txd1_default {
1351		function = "TXD1";
1352		groups = "TXD1";
1353	};
1354
1355	pinctrl_txd2_default: txd2_default {
1356		function = "TXD2";
1357		groups = "TXD2";
1358	};
1359
1360	pinctrl_txd3_default: txd3_default {
1361		function = "TXD3";
1362		groups = "TXD3";
1363	};
1364
1365	pinctrl_txd4_default: txd4_default {
1366		function = "TXD4";
1367		groups = "TXD4";
1368	};
1369
1370	pinctrl_uart6_default: uart6_default {
1371		function = "UART6";
1372		groups = "UART6";
1373	};
1374
1375	pinctrl_usbcki_default: usbcki_default {
1376		function = "USBCKI";
1377		groups = "USBCKI";
1378	};
1379
1380	pinctrl_usb2h_default: usb2h_default {
1381		function = "USB2H1";
1382		groups = "USB2H1";
1383	};
1384
1385	pinctrl_usb2d_default: usb2d_default {
1386		function = "USB2D1";
1387		groups = "USB2D1";
1388	};
1389
1390	pinctrl_vgabios_rom_default: vgabios_rom_default {
1391		function = "VGABIOS_ROM";
1392		groups = "VGABIOS_ROM";
1393	};
1394
1395	pinctrl_vgahs_default: vgahs_default {
1396		function = "VGAHS";
1397		groups = "VGAHS";
1398	};
1399
1400	pinctrl_vgavs_default: vgavs_default {
1401		function = "VGAVS";
1402		groups = "VGAVS";
1403	};
1404
1405	pinctrl_vpi18_default: vpi18_default {
1406		function = "VPI18";
1407		groups = "VPI18";
1408	};
1409
1410	pinctrl_vpi24_default: vpi24_default {
1411		function = "VPI24";
1412		groups = "VPI24";
1413	};
1414
1415	pinctrl_vpi30_default: vpi30_default {
1416		function = "VPI30";
1417		groups = "VPI30";
1418	};
1419
1420	pinctrl_vpo12_default: vpo12_default {
1421		function = "VPO12";
1422		groups = "VPO12";
1423	};
1424
1425	pinctrl_vpo24_default: vpo24_default {
1426		function = "VPO24";
1427		groups = "VPO24";
1428	};
1429
1430	pinctrl_wdtrst1_default: wdtrst1_default {
1431		function = "WDTRST1";
1432		groups = "WDTRST1";
1433	};
1434
1435	pinctrl_wdtrst2_default: wdtrst2_default {
1436		function = "WDTRST2";
1437		groups = "WDTRST2";
1438	};
1439};
1440