1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring// Copyright (C) 2021 YADRO 3*724ba675SRob Herring/dts-v1/; 4*724ba675SRob Herring 5*724ba675SRob Herring#include "aspeed-bmc-vegman.dtsi" 6*724ba675SRob Herring 7*724ba675SRob Herring/ { 8*724ba675SRob Herring model = "YADRO VEGMAN N110 BMC"; 9*724ba675SRob Herring compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500"; 10*724ba675SRob Herring}; 11*724ba675SRob Herring 12*724ba675SRob Herring&gpio { 13*724ba675SRob Herring status = "okay"; 14*724ba675SRob Herring gpio-line-names = 15*724ba675SRob Herring /*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","", 16*724ba675SRob Herring /*B0-B7*/ "","","","","","","","", 17*724ba675SRob Herring /*C0-C7*/ "","","","","","","","", 18*724ba675SRob Herring /*D0-D7*/ "","","","","","","","", 19*724ba675SRob Herring /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","", 20*724ba675SRob Herring /*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","", 21*724ba675SRob Herring /*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","", 22*724ba675SRob Herring /*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS", 23*724ba675SRob Herring /*I0-I7*/ "","","","","","","","", 24*724ba675SRob Herring /*J0-J7*/ "","","","","","","","", 25*724ba675SRob Herring /*K0-K7*/ "","","","","","","","", 26*724ba675SRob Herring /*L0-L7*/ "","","","","","","","", 27*724ba675SRob Herring /*M0-M7*/ "","","","","","","","", 28*724ba675SRob Herring /*N0-N7*/ "","","","","","","","", 29*724ba675SRob Herring /*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL", 30*724ba675SRob Herring /*P0-P7*/ "","","","","","","","", 31*724ba675SRob Herring /*Q0-Q7*/ "","","","","","","","", 32*724ba675SRob Herring /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","", 33*724ba675SRob Herring /*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","", 34*724ba675SRob Herring /*T0-T7*/ "","","","","","","","", 35*724ba675SRob Herring /*U0-U7*/ "","","","","","","","", 36*724ba675SRob Herring /*V0-V7*/ "","","","","","","","", 37*724ba675SRob Herring /*W0-W7*/ "","","","","","","","", 38*724ba675SRob Herring /*X0-X7*/ "","","","","","","","", 39*724ba675SRob Herring /*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","", 40*724ba675SRob Herring /*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","", 41*724ba675SRob Herring /*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE", 42*724ba675SRob Herring /*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","", 43*724ba675SRob Herring /*AC0-AC7*/ "","","","","","","",""; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&sgpio { 47*724ba675SRob Herring ngpios = <80>; 48*724ba675SRob Herring bus-frequency = <2000000>; 49*724ba675SRob Herring status = "okay"; 50*724ba675SRob Herring /* SGPIO lines. even: input, odd: output */ 51*724ba675SRob Herring gpio-line-names = 52*724ba675SRob Herring /*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","", 53*724ba675SRob Herring /*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","", 54*724ba675SRob Herring /*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","", 55*724ba675SRob Herring /*D0-D7*/ "","","","","","","","","","","","","","","","", 56*724ba675SRob Herring /*E0-E7*/ "","","","","","","","","","","","","","","","", 57*724ba675SRob Herring /*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","", 58*724ba675SRob Herring /*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","", 59*724ba675SRob Herring /*H0-H7*/ "","","","","","","","","","","","","","","","", 60*724ba675SRob Herring /*I0-I7*/ "","","","","","","","","","","","","","","","", 61*724ba675SRob Herring /*J0-J7*/ "","","","","","","","","","","","","","","",""; 62*724ba675SRob Herring}; 63*724ba675SRob Herring 64*724ba675SRob Herring&i2c11 { 65*724ba675SRob Herring /* SMB_BMC_MGMT_LVC3 */ 66*724ba675SRob Herring gpio@21 { 67*724ba675SRob Herring compatible = "nxp,pcal9535"; 68*724ba675SRob Herring reg = <0x21>; 69*724ba675SRob Herring gpio-controller; 70*724ba675SRob Herring #gpio-cells = <2>; 71*724ba675SRob Herring gpio-line-names = 72*724ba675SRob Herring /*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "", 73*724ba675SRob Herring /*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", ""; 74*724ba675SRob Herring }; 75*724ba675SRob Herring gpio@27 { 76*724ba675SRob Herring compatible = "nxp,pca9698"; 77*724ba675SRob Herring reg = <0x27>; 78*724ba675SRob Herring gpio-controller; 79*724ba675SRob Herring #gpio-cells = <2>; 80*724ba675SRob Herring gpio-line-names = 81*724ba675SRob Herring /*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX", 82*724ba675SRob Herring /*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0", 83*724ba675SRob Herring /*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "", 84*724ba675SRob Herring /*IO3.0-3.7*/ "", "", "", "", "", "", "", "", 85*724ba675SRob Herring /*IO4.0-4.7*/ "", "", "", "", "", "", "", ""; 86*724ba675SRob Herring }; 87*724ba675SRob Herring}; 88*724ba675SRob Herring 89*724ba675SRob Herring&i2c13 { 90*724ba675SRob Herring /* SMB_PCIE2_STBY_LVC3 */ 91*724ba675SRob Herring mux-expa@73 { 92*724ba675SRob Herring compatible = "nxp,pca9545"; 93*724ba675SRob Herring reg = <0x73>; 94*724ba675SRob Herring #address-cells = <1>; 95*724ba675SRob Herring #size-cells = <0>; 96*724ba675SRob Herring i2c-mux-idle-disconnect; 97*724ba675SRob Herring }; 98*724ba675SRob Herring mux-sata@71 { 99*724ba675SRob Herring compatible = "nxp,pca9543"; 100*724ba675SRob Herring reg = <0x71>; 101*724ba675SRob Herring #address-cells = <1>; 102*724ba675SRob Herring #size-cells = <0>; 103*724ba675SRob Herring i2c-mux-idle-disconnect; 104*724ba675SRob Herring }; 105*724ba675SRob Herring}; 106*724ba675SRob Herring 107*724ba675SRob Herring&i2c2 { 108*724ba675SRob Herring /* SMB_PCIE_STBY_LVC3 */ 109*724ba675SRob Herring mux-expb@71 { 110*724ba675SRob Herring compatible = "nxp,pca9545"; 111*724ba675SRob Herring reg = <0x71>; 112*724ba675SRob Herring #address-cells = <1>; 113*724ba675SRob Herring #size-cells = <0>; 114*724ba675SRob Herring i2c-mux-idle-disconnect; 115*724ba675SRob Herring }; 116*724ba675SRob Herring}; 117*724ba675SRob Herring 118*724ba675SRob Herring&pwm_tacho { 119*724ba675SRob Herring status = "okay"; 120*724ba675SRob Herring pinctrl-names = "default"; 121*724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default 122*724ba675SRob Herring &pinctrl_pwm2_default &pinctrl_pwm3_default 123*724ba675SRob Herring &pinctrl_pwm4_default &pinctrl_pwm5_default>; 124*724ba675SRob Herring 125*724ba675SRob Herring fan@0 { 126*724ba675SRob Herring reg = <0x00>; 127*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>; 128*724ba675SRob Herring }; 129*724ba675SRob Herring fan@1 { 130*724ba675SRob Herring reg = <0x01>; 131*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring fan@2 { 134*724ba675SRob Herring reg = <0x02>; 135*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>; 136*724ba675SRob Herring }; 137*724ba675SRob Herring fan@3 { 138*724ba675SRob Herring reg = <0x03>; 139*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>; 140*724ba675SRob Herring }; 141*724ba675SRob Herring fan@4 { 142*724ba675SRob Herring reg = <0x04>; 143*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring fan@5 { 146*724ba675SRob Herring reg = <0x05>; 147*724ba675SRob Herring aspeed,fan-tach-ch = /bits/ 8 <0x05>; 148*724ba675SRob Herring }; 149*724ba675SRob Herring}; 150