1/* 2 * Copyright 2015 Annapurna Labs Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * Alternatively, redistribution and use in source and binary forms, with or 9 * without modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * * Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 20 * This program is distributed in the hope it will be useful, but WITHOUT 21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 23 * more details. 24 * 25 */ 26 27#include <dt-bindings/interrupt-controller/arm-gic.h> 28 29/ { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 /* SOC compatibility */ 33 compatible = "al,alpine"; 34 35 memory { 36 device_type = "memory"; 37 reg = <0 0 0 0>; 38 }; 39 40 /* CPU Configuration */ 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 enable-method = "al,alpine-smp"; 45 46 cpu@0 { 47 compatible = "arm,cortex-a15"; 48 device_type = "cpu"; 49 reg = <0>; 50 clock-frequency = <1700000000>; 51 }; 52 53 cpu@1 { 54 compatible = "arm,cortex-a15"; 55 device_type = "cpu"; 56 reg = <1>; 57 clock-frequency = <1700000000>; 58 }; 59 60 cpu@2 { 61 compatible = "arm,cortex-a15"; 62 device_type = "cpu"; 63 reg = <2>; 64 clock-frequency = <1700000000>; 65 }; 66 67 cpu@3 { 68 compatible = "arm,cortex-a15"; 69 device_type = "cpu"; 70 reg = <3>; 71 clock-frequency = <1700000000>; 72 }; 73 }; 74 75 soc { 76 #address-cells = <2>; 77 #size-cells = <2>; 78 compatible = "simple-bus"; 79 interrupt-parent = <&gic>; 80 ranges; 81 82 arch-timer { 83 compatible = "arm,cortex-a15-timer", 84 "arm,armv7-timer"; 85 interrupts = 86 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 90 clock-frequency = <50000000>; 91 }; 92 93 /* Interrupt Controller */ 94 gic: interrupt-controller@fb001000 { 95 compatible = "arm,cortex-a15-gic"; 96 #interrupt-cells = <3>; 97 #size-cells = <0>; 98 #address-cells = <0>; 99 interrupt-controller; 100 reg = <0x0 0xfb001000 0x0 0x1000>, 101 <0x0 0xfb002000 0x0 0x2000>, 102 <0x0 0xfb004000 0x0 0x2000>, 103 <0x0 0xfb006000 0x0 0x2000>; 104 interrupts = 105 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 106 }; 107 108 /* CPU Resume registers */ 109 cpu-resume@fbff5ec0 { 110 compatible = "al,alpine-cpu-resume"; 111 reg = <0x0 0xfbff5ec0 0x0 0x30>; 112 }; 113 114 /* North Bridge Service Registers */ 115 sysfabric-service@fb070000 { 116 compatible = "al,alpine-sysfabric-service", "syscon"; 117 reg = <0x0 0xfb070000 0x0 0x10000>; 118 }; 119 120 /* Performance Monitor Unit */ 121 pmu { 122 compatible = "arm,cortex-a15-pmu"; 123 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 127 }; 128 129 uart0: serial@fd883000 { 130 compatible = "ns16550a"; 131 reg = <0x0 0xfd883000 0x0 0x1000>; 132 clock-frequency = <375000000>; 133 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 134 reg-shift = <2>; 135 reg-io-width = <4>; 136 }; 137 138 uart1: serial@fd884000 { 139 compatible = "ns16550a"; 140 reg = <0x0 0xfd884000 0x0 0x1000>; 141 clock-frequency = <375000000>; 142 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 143 reg-shift = <2>; 144 reg-io-width = <4>; 145 }; 146 147 /* Internal PCIe Controller */ 148 pcie@fbc00000 { 149 compatible = "pci-host-ecam-generic"; 150 device_type = "pci"; 151 #size-cells = <2>; 152 #address-cells = <3>; 153 #interrupt-cells = <1>; 154 reg = <0x0 0xfbc00000 0x0 0x100000>; 155 interrupt-map-mask = <0xf800 0 0 7>; 156 /* Add legacy interrupts for SATA devices only */ 157 interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, 158 <0x4800 0 0 1 &gic 0 44 4>; 159 160 /* 32 bit non prefetchable memory space */ 161 ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; 162 163 bus-range = <0x00 0x00>; 164 msi-parent = <&msix>; 165 }; 166 167 msix: msix@fbe00000 { 168 compatible = "al,alpine-msix"; 169 reg = <0x0 0xfbe00000 0x0 0x100000>; 170 interrupt-controller; 171 msi-controller; 172 al,msi-base-spi = <96>; 173 al,msi-num-spis = <64>; 174 }; 175 }; 176}; 177