1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/linkage.h> 12 13/* 14 * Debugging stuff 15 * 16 * Note that these macros must not contain any code which is not 17 * 100% relocatable. Any attempt to do so will result in a crash. 18 * Please select one of the following when turning on debugging. 19 */ 20#ifdef DEBUG 21 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm 30#else 31 .macro loadsp, rb 32 .endm 33 .macro writeb, ch, rb 34 mcr p14, 0, \ch, c1, c0, 0 35 .endm 36#endif 37 38#else 39 40#include <asm/arch/debug-macro.S> 41 42 .macro writeb, ch, rb 43 senduart \ch, \rb 44 .endm 45 46#if defined(CONFIG_ARCH_SA1100) 47 .macro loadsp, rb 48 mov \rb, #0x80000000 @ physical base address 49#ifdef CONFIG_DEBUG_LL_SER3 50 add \rb, \rb, #0x00050000 @ Ser3 51#else 52 add \rb, \rb, #0x00010000 @ Ser1 53#endif 54 .endm 55#elif defined(CONFIG_ARCH_S3C2410) 56 .macro loadsp, rb 57 mov \rb, #0x50000000 58 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 59 .endm 60#else 61 .macro loadsp, rb 62 addruart \rb 63 .endm 64#endif 65#endif 66#endif 67 68 .macro kputc,val 69 mov r0, \val 70 bl putc 71 .endm 72 73 .macro kphex,val,len 74 mov r0, \val 75 mov r1, #\len 76 bl phex 77 .endm 78 79 .macro debug_reloc_start 80#ifdef DEBUG 81 kputc #'\n' 82 kphex r6, 8 /* processor id */ 83 kputc #':' 84 kphex r7, 8 /* architecture id */ 85#ifdef CONFIG_CPU_CP15 86 kputc #':' 87 mrc p15, 0, r0, c1, c0 88 kphex r0, 8 /* control reg */ 89#endif 90 kputc #'\n' 91 kphex r5, 8 /* decompressed kernel start */ 92 kputc #'-' 93 kphex r9, 8 /* decompressed kernel end */ 94 kputc #'>' 95 kphex r4, 8 /* kernel execution address */ 96 kputc #'\n' 97#endif 98 .endm 99 100 .macro debug_reloc_end 101#ifdef DEBUG 102 kphex r5, 8 /* end of kernel */ 103 kputc #'\n' 104 mov r0, r4 105 bl memdump /* dump 256 bytes at start of kernel */ 106#endif 107 .endm 108 109 .section ".start", #alloc, #execinstr 110/* 111 * sort out different calling conventions 112 */ 113 .align 114start: 115 .type start,#function 116 .rept 8 117 mov r0, r0 118 .endr 119 120 b 1f 121 .word 0x016f2818 @ Magic numbers to help the loader 122 .word start @ absolute load/run zImage address 123 .word _edata @ zImage end address 1241: mov r7, r1 @ save architecture ID 125 mov r8, r2 @ save atags pointer 126 127#ifndef __ARM_ARCH_2__ 128 /* 129 * Booting from Angel - need to enter SVC mode and disable 130 * FIQs/IRQs (numeric definitions from angel arm.h source). 131 * We only do this if we were in user mode on entry. 132 */ 133 mrs r2, cpsr @ get current mode 134 tst r2, #3 @ not user? 135 bne not_angel 136 mov r0, #0x17 @ angel_SWIreason_EnterSVC 137 swi 0x123456 @ angel_SWI_ARM 138not_angel: 139 mrs r2, cpsr @ turn off interrupts to 140 orr r2, r2, #0xc0 @ prevent angel from running 141 msr cpsr_c, r2 142#else 143 teqp pc, #0x0c000003 @ turn off interrupts 144#endif 145 146 /* 147 * Note that some cache flushing and other stuff may 148 * be needed here - is there an Angel SWI call for this? 149 */ 150 151 /* 152 * some architecture specific code can be inserted 153 * by the linker here, but it should preserve r7, r8, and r9. 154 */ 155 156 .text 157 adr r0, LC0 158 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} 159 subs r0, r0, r1 @ calculate the delta offset 160 161 @ if delta is zero, we are 162 beq not_relocated @ running at the address we 163 @ were linked at. 164 165 /* 166 * We're running at a different address. We need to fix 167 * up various pointers: 168 * r5 - zImage base address 169 * r6 - GOT start 170 * ip - GOT end 171 */ 172 add r5, r5, r0 173 add r6, r6, r0 174 add ip, ip, r0 175 176#ifndef CONFIG_ZBOOT_ROM 177 /* 178 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, 179 * we need to fix up pointers into the BSS region. 180 * r2 - BSS start 181 * r3 - BSS end 182 * sp - stack pointer 183 */ 184 add r2, r2, r0 185 add r3, r3, r0 186 add sp, sp, r0 187 188 /* 189 * Relocate all entries in the GOT table. 190 */ 1911: ldr r1, [r6, #0] @ relocate entries in the GOT 192 add r1, r1, r0 @ table. This fixes up the 193 str r1, [r6], #4 @ C references. 194 cmp r6, ip 195 blo 1b 196#else 197 198 /* 199 * Relocate entries in the GOT table. We only relocate 200 * the entries that are outside the (relocated) BSS region. 201 */ 2021: ldr r1, [r6, #0] @ relocate entries in the GOT 203 cmp r1, r2 @ entry < bss_start || 204 cmphs r3, r1 @ _end < entry 205 addlo r1, r1, r0 @ table. This fixes up the 206 str r1, [r6], #4 @ C references. 207 cmp r6, ip 208 blo 1b 209#endif 210 211not_relocated: mov r0, #0 2121: str r0, [r2], #4 @ clear bss 213 str r0, [r2], #4 214 str r0, [r2], #4 215 str r0, [r2], #4 216 cmp r2, r3 217 blo 1b 218 219 /* 220 * The C runtime environment should now be setup 221 * sufficiently. Turn the cache on, set up some 222 * pointers, and start decompressing. 223 */ 224 bl cache_on 225 226 mov r1, sp @ malloc space above stack 227 add r2, sp, #0x10000 @ 64k max 228 229/* 230 * Check to see if we will overwrite ourselves. 231 * r4 = final kernel address 232 * r5 = start of this image 233 * r2 = end of malloc space (and therefore this image) 234 * We basically want: 235 * r4 >= r2 -> OK 236 * r4 + image length <= r5 -> OK 237 */ 238 cmp r4, r2 239 bhs wont_overwrite 240 sub r3, sp, r5 @ > compressed kernel size 241 add r0, r4, r3, lsl #2 @ allow for 4x expansion 242 cmp r0, r5 243 bls wont_overwrite 244 245 mov r5, r2 @ decompress after malloc space 246 mov r0, r5 247 mov r3, r7 248 bl decompress_kernel 249 250 add r0, r0, #127 + 128 @ alignment + stack 251 bic r0, r0, #127 @ align the kernel length 252/* 253 * r0 = decompressed kernel length 254 * r1-r3 = unused 255 * r4 = kernel execution address 256 * r5 = decompressed kernel start 257 * r6 = processor ID 258 * r7 = architecture ID 259 * r8 = atags pointer 260 * r9-r14 = corrupted 261 */ 262 add r1, r5, r0 @ end of decompressed kernel 263 adr r2, reloc_start 264 ldr r3, LC1 265 add r3, r2, r3 2661: ldmia r2!, {r9 - r14} @ copy relocation code 267 stmia r1!, {r9 - r14} 268 ldmia r2!, {r9 - r14} 269 stmia r1!, {r9 - r14} 270 cmp r2, r3 271 blo 1b 272 add sp, r1, #128 @ relocate the stack 273 274 bl cache_clean_flush 275 add pc, r5, r0 @ call relocation code 276 277/* 278 * We're not in danger of overwriting ourselves. Do this the simple way. 279 * 280 * r4 = kernel execution address 281 * r7 = architecture ID 282 */ 283wont_overwrite: mov r0, r4 284 mov r3, r7 285 bl decompress_kernel 286 b call_kernel 287 288 .type LC0, #object 289LC0: .word LC0 @ r1 290 .word __bss_start @ r2 291 .word _end @ r3 292 .word zreladdr @ r4 293 .word _start @ r5 294 .word _got_start @ r6 295 .word _got_end @ ip 296 .word user_stack+4096 @ sp 297LC1: .word reloc_end - reloc_start 298 .size LC0, . - LC0 299 300#ifdef CONFIG_ARCH_RPC 301 .globl params 302params: ldr r0, =params_phys 303 mov pc, lr 304 .ltorg 305 .align 306#endif 307 308/* 309 * Turn on the cache. We need to setup some page tables so that we 310 * can have both the I and D caches on. 311 * 312 * We place the page tables 16k down from the kernel execution address, 313 * and we hope that nothing else is using it. If we're using it, we 314 * will go pop! 315 * 316 * On entry, 317 * r4 = kernel execution address 318 * r6 = processor ID 319 * r7 = architecture number 320 * r8 = atags pointer 321 * r9 = run-time address of "start" (???) 322 * On exit, 323 * r1, r2, r3, r9, r10, r12 corrupted 324 * This routine must preserve: 325 * r4, r5, r6, r7, r8 326 */ 327 .align 5 328cache_on: mov r3, #8 @ cache_on function 329 b call_cache_fn 330 331/* 332 * Initialize the highest priority protection region, PR7 333 * to cover all 32bit address and cacheable and bufferable. 334 */ 335__armv4_mpu_cache_on: 336 mov r0, #0x3f @ 4G, the whole 337 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 338 mcr p15, 0, r0, c6, c7, 1 339 340 mov r0, #0x80 @ PR7 341 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 342 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 343 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 344 345 mov r0, #0xc000 346 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 347 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 348 349 mov r0, #0 350 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 351 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 352 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 353 mrc p15, 0, r0, c1, c0, 0 @ read control reg 354 @ ...I .... ..D. WC.M 355 orr r0, r0, #0x002d @ .... .... ..1. 11.1 356 orr r0, r0, #0x1000 @ ...1 .... .... .... 357 358 mcr p15, 0, r0, c1, c0, 0 @ write control reg 359 360 mov r0, #0 361 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 362 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 363 mov pc, lr 364 365__armv3_mpu_cache_on: 366 mov r0, #0x3f @ 4G, the whole 367 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 368 369 mov r0, #0x80 @ PR7 370 mcr p15, 0, r0, c2, c0, 0 @ cache on 371 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 372 373 mov r0, #0xc000 374 mcr p15, 0, r0, c5, c0, 0 @ access permission 375 376 mov r0, #0 377 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 378 mrc p15, 0, r0, c1, c0, 0 @ read control reg 379 @ .... .... .... WC.M 380 orr r0, r0, #0x000d @ .... .... .... 11.1 381 mov r0, #0 382 mcr p15, 0, r0, c1, c0, 0 @ write control reg 383 384 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 385 mov pc, lr 386 387__setup_mmu: sub r3, r4, #16384 @ Page directory size 388 bic r3, r3, #0xff @ Align the pointer 389 bic r3, r3, #0x3f00 390/* 391 * Initialise the page tables, turning on the cacheable and bufferable 392 * bits for the RAM area only. 393 */ 394 mov r0, r3 395 mov r9, r0, lsr #18 396 mov r9, r9, lsl #18 @ start of RAM 397 add r10, r9, #0x10000000 @ a reasonable RAM size 398 mov r1, #0x12 399 orr r1, r1, #3 << 10 400 add r2, r3, #16384 4011: cmp r1, r9 @ if virt > start of RAM 402 orrhs r1, r1, #0x0c @ set cacheable, bufferable 403 cmp r1, r10 @ if virt > end of RAM 404 bichs r1, r1, #0x0c @ clear cacheable, bufferable 405 str r1, [r0], #4 @ 1:1 mapping 406 add r1, r1, #1048576 407 teq r0, r2 408 bne 1b 409/* 410 * If ever we are running from Flash, then we surely want the cache 411 * to be enabled also for our execution instance... We map 2MB of it 412 * so there is no map overlap problem for up to 1 MB compressed kernel. 413 * If the execution is in RAM then we would only be duplicating the above. 414 */ 415 mov r1, #0x1e 416 orr r1, r1, #3 << 10 417 mov r2, pc, lsr #20 418 orr r1, r1, r2, lsl #20 419 add r0, r3, r2, lsl #2 420 str r1, [r0], #4 421 add r1, r1, #1048576 422 str r1, [r0] 423 mov pc, lr 424 425__armv4_mmu_cache_on: 426 mov r12, lr 427 bl __setup_mmu 428 mov r0, #0 429 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 430 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 431 mrc p15, 0, r0, c1, c0, 0 @ read control reg 432 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 433 orr r0, r0, #0x0030 434 bl __common_mmu_cache_on 435 mov r0, #0 436 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 437 mov pc, r12 438 439__armv7_mmu_cache_on: 440 mov r12, lr 441 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 442 tst r11, #0xf @ VMSA 443 blne __setup_mmu 444 mov r0, #0 445 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 446 tst r11, #0xf @ VMSA 447 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 448 mrc p15, 0, r0, c1, c0, 0 @ read control reg 449 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 450 orr r0, r0, #0x003c @ write buffer 451 orrne r0, r0, #1 @ MMU enabled 452 movne r1, #-1 453 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 454 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 455 mcr p15, 0, r0, c1, c0, 0 @ load control register 456 mrc p15, 0, r0, c1, c0, 0 @ and read it back 457 mov r0, #0 458 mcr p15, 0, r0, c7, c5, 4 @ ISB 459 mov pc, r12 460 461__arm6_mmu_cache_on: 462 mov r12, lr 463 bl __setup_mmu 464 mov r0, #0 465 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 466 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 467 mov r0, #0x30 468 bl __common_mmu_cache_on 469 mov r0, #0 470 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 471 mov pc, r12 472 473__common_mmu_cache_on: 474#ifndef DEBUG 475 orr r0, r0, #0x000d @ Write buffer, mmu 476#endif 477 mov r1, #-1 478 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 479 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 480 b 1f 481 .align 5 @ cache line aligned 4821: mcr p15, 0, r0, c1, c0, 0 @ load control register 483 mrc p15, 0, r0, c1, c0, 0 @ and read it back to 484 sub pc, lr, r0, lsr #32 @ properly flush pipeline 485 486/* 487 * All code following this line is relocatable. It is relocated by 488 * the above code to the end of the decompressed kernel image and 489 * executed there. During this time, we have no stacks. 490 * 491 * r0 = decompressed kernel length 492 * r1-r3 = unused 493 * r4 = kernel execution address 494 * r5 = decompressed kernel start 495 * r6 = processor ID 496 * r7 = architecture ID 497 * r8 = atags pointer 498 * r9-r14 = corrupted 499 */ 500 .align 5 501reloc_start: add r9, r5, r0 502 sub r9, r9, #128 @ do not copy the stack 503 debug_reloc_start 504 mov r1, r4 5051: 506 .rept 4 507 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel 508 stmia r1!, {r0, r2, r3, r10 - r14} 509 .endr 510 511 cmp r5, r9 512 blo 1b 513 add sp, r1, #128 @ relocate the stack 514 debug_reloc_end 515 516call_kernel: bl cache_clean_flush 517 bl cache_off 518 mov r0, #0 @ must be zero 519 mov r1, r7 @ restore architecture number 520 mov r2, r8 @ restore atags pointer 521 mov pc, r4 @ call kernel 522 523/* 524 * Here follow the relocatable cache support functions for the 525 * various processors. This is a generic hook for locating an 526 * entry and jumping to an instruction at the specified offset 527 * from the start of the block. Please note this is all position 528 * independent code. 529 * 530 * r1 = corrupted 531 * r2 = corrupted 532 * r3 = block offset 533 * r6 = corrupted 534 * r12 = corrupted 535 */ 536 537call_cache_fn: adr r12, proc_types 538#ifdef CONFIG_CPU_CP15 539 mrc p15, 0, r6, c0, c0 @ get processor ID 540#else 541 ldr r6, =CONFIG_PROCESSOR_ID 542#endif 5431: ldr r1, [r12, #0] @ get value 544 ldr r2, [r12, #4] @ get mask 545 eor r1, r1, r6 @ (real ^ match) 546 tst r1, r2 @ & mask 547 addeq pc, r12, r3 @ call cache function 548 add r12, r12, #4*5 549 b 1b 550 551/* 552 * Table for cache operations. This is basically: 553 * - CPU ID match 554 * - CPU ID mask 555 * - 'cache on' method instruction 556 * - 'cache off' method instruction 557 * - 'cache flush' method instruction 558 * 559 * We match an entry using: ((real_id ^ match) & mask) == 0 560 * 561 * Writethrough caches generally only need 'on' and 'off' 562 * methods. Writeback caches _must_ have the flush method 563 * defined. 564 */ 565 .type proc_types,#object 566proc_types: 567 .word 0x41560600 @ ARM6/610 568 .word 0xffffffe0 569 b __arm6_mmu_cache_off @ works, but slow 570 b __arm6_mmu_cache_off 571 mov pc, lr 572@ b __arm6_mmu_cache_on @ untested 573@ b __arm6_mmu_cache_off 574@ b __armv3_mmu_cache_flush 575 576 .word 0x00000000 @ old ARM ID 577 .word 0x0000f000 578 mov pc, lr 579 mov pc, lr 580 mov pc, lr 581 582 .word 0x41007000 @ ARM7/710 583 .word 0xfff8fe00 584 b __arm7_mmu_cache_off 585 b __arm7_mmu_cache_off 586 mov pc, lr 587 588 .word 0x41807200 @ ARM720T (writethrough) 589 .word 0xffffff00 590 b __armv4_mmu_cache_on 591 b __armv4_mmu_cache_off 592 mov pc, lr 593 594 .word 0x41007400 @ ARM74x 595 .word 0xff00ff00 596 b __armv3_mpu_cache_on 597 b __armv3_mpu_cache_off 598 b __armv3_mpu_cache_flush 599 600 .word 0x41009400 @ ARM94x 601 .word 0xff00ff00 602 b __armv4_mpu_cache_on 603 b __armv4_mpu_cache_off 604 b __armv4_mpu_cache_flush 605 606 .word 0x00007000 @ ARM7 IDs 607 .word 0x0000f000 608 mov pc, lr 609 mov pc, lr 610 mov pc, lr 611 612 @ Everything from here on will be the new ID system. 613 614 .word 0x4401a100 @ sa110 / sa1100 615 .word 0xffffffe0 616 b __armv4_mmu_cache_on 617 b __armv4_mmu_cache_off 618 b __armv4_mmu_cache_flush 619 620 .word 0x6901b110 @ sa1110 621 .word 0xfffffff0 622 b __armv4_mmu_cache_on 623 b __armv4_mmu_cache_off 624 b __armv4_mmu_cache_flush 625 626 .word 0x56055310 @ Feroceon 627 .word 0xfffffff0 628 b __armv4_mmu_cache_on 629 b __armv4_mmu_cache_off 630 b __armv5tej_mmu_cache_flush 631 632 @ These match on the architecture ID 633 634 .word 0x00020000 @ ARMv4T 635 .word 0x000f0000 636 b __armv4_mmu_cache_on 637 b __armv4_mmu_cache_off 638 b __armv4_mmu_cache_flush 639 640 .word 0x00050000 @ ARMv5TE 641 .word 0x000f0000 642 b __armv4_mmu_cache_on 643 b __armv4_mmu_cache_off 644 b __armv4_mmu_cache_flush 645 646 .word 0x00060000 @ ARMv5TEJ 647 .word 0x000f0000 648 b __armv4_mmu_cache_on 649 b __armv4_mmu_cache_off 650 b __armv5tej_mmu_cache_flush 651 652 .word 0x0007b000 @ ARMv6 653 .word 0x000ff000 654 b __armv4_mmu_cache_on 655 b __armv4_mmu_cache_off 656 b __armv6_mmu_cache_flush 657 658 .word 0x000f0000 @ new CPU Id 659 .word 0x000f0000 660 b __armv7_mmu_cache_on 661 b __armv7_mmu_cache_off 662 b __armv7_mmu_cache_flush 663 664 .word 0 @ unrecognised type 665 .word 0 666 mov pc, lr 667 mov pc, lr 668 mov pc, lr 669 670 .size proc_types, . - proc_types 671 672/* 673 * Turn off the Cache and MMU. ARMv3 does not support 674 * reading the control register, but ARMv4 does. 675 * 676 * On entry, r6 = processor ID 677 * On exit, r0, r1, r2, r3, r12 corrupted 678 * This routine must preserve: r4, r6, r7 679 */ 680 .align 5 681cache_off: mov r3, #12 @ cache_off function 682 b call_cache_fn 683 684__armv4_mpu_cache_off: 685 mrc p15, 0, r0, c1, c0 686 bic r0, r0, #0x000d 687 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 688 mov r0, #0 689 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 690 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 691 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 692 mov pc, lr 693 694__armv3_mpu_cache_off: 695 mrc p15, 0, r0, c1, c0 696 bic r0, r0, #0x000d 697 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 698 mov r0, #0 699 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 700 mov pc, lr 701 702__armv4_mmu_cache_off: 703 mrc p15, 0, r0, c1, c0 704 bic r0, r0, #0x000d 705 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 706 mov r0, #0 707 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 708 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 709 mov pc, lr 710 711__armv7_mmu_cache_off: 712 mrc p15, 0, r0, c1, c0 713 bic r0, r0, #0x000d 714 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 715 mov r12, lr 716 bl __armv7_mmu_cache_flush 717 mov r0, #0 718 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 719 mov pc, r12 720 721__arm6_mmu_cache_off: 722 mov r0, #0x00000030 @ ARM6 control reg. 723 b __armv3_mmu_cache_off 724 725__arm7_mmu_cache_off: 726 mov r0, #0x00000070 @ ARM7 control reg. 727 b __armv3_mmu_cache_off 728 729__armv3_mmu_cache_off: 730 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 731 mov r0, #0 732 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 733 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 734 mov pc, lr 735 736/* 737 * Clean and flush the cache to maintain consistency. 738 * 739 * On entry, 740 * r6 = processor ID 741 * On exit, 742 * r1, r2, r3, r11, r12 corrupted 743 * This routine must preserve: 744 * r0, r4, r5, r6, r7 745 */ 746 .align 5 747cache_clean_flush: 748 mov r3, #16 749 b call_cache_fn 750 751__armv4_mpu_cache_flush: 752 mov r2, #1 753 mov r3, #0 754 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 755 mov r1, #7 << 5 @ 8 segments 7561: orr r3, r1, #63 << 26 @ 64 entries 7572: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 758 subs r3, r3, #1 << 26 759 bcs 2b @ entries 63 to 0 760 subs r1, r1, #1 << 5 761 bcs 1b @ segments 7 to 0 762 763 teq r2, #0 764 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 765 mcr p15, 0, ip, c7, c10, 4 @ drain WB 766 mov pc, lr 767 768 769__armv6_mmu_cache_flush: 770 mov r1, #0 771 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 772 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 773 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 774 mcr p15, 0, r1, c7, c10, 4 @ drain WB 775 mov pc, lr 776 777__armv7_mmu_cache_flush: 778 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 779 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 780 beq hierarchical 781 mov r10, #0 782 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 783 b iflush 784hierarchical: 785 stmfd sp!, {r0-r5, r7, r9-r11} 786 mrc p15, 1, r0, c0, c0, 1 @ read clidr 787 ands r3, r0, #0x7000000 @ extract loc from clidr 788 mov r3, r3, lsr #23 @ left align loc bit field 789 beq finished @ if loc is 0, then no need to clean 790 mov r10, #0 @ start clean at cache level 0 791loop1: 792 add r2, r10, r10, lsr #1 @ work out 3x current cache level 793 mov r1, r0, lsr r2 @ extract cache type bits from clidr 794 and r1, r1, #7 @ mask of the bits for current cache only 795 cmp r1, #2 @ see what cache we have at this level 796 blt skip @ skip if no cache, or just i-cache 797 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 798 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 799 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 800 and r2, r1, #7 @ extract the length of the cache lines 801 add r2, r2, #4 @ add 4 (line length offset) 802 ldr r4, =0x3ff 803 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 804 .word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment 805 ldr r7, =0x7fff 806 ands r7, r7, r1, lsr #13 @ extract max number of the index size 807loop2: 808 mov r9, r4 @ create working copy of max way size 809loop3: 810 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 811 orr r11, r11, r7, lsl r2 @ factor index number into r11 812 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 813 subs r9, r9, #1 @ decrement the way 814 bge loop3 815 subs r7, r7, #1 @ decrement the index 816 bge loop2 817skip: 818 add r10, r10, #2 @ increment cache number 819 cmp r3, r10 820 bgt loop1 821finished: 822 mov r10, #0 @ swith back to cache level 0 823 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 824 ldmfd sp!, {r0-r5, r7, r9-r11} 825iflush: 826 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 827 mcr p15, 0, r10, c7, c10, 4 @ drain WB 828 mov pc, lr 829 830__armv5tej_mmu_cache_flush: 8311: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 832 bne 1b 833 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 834 mcr p15, 0, r0, c7, c10, 4 @ drain WB 835 mov pc, lr 836 837__armv4_mmu_cache_flush: 838 mov r2, #64*1024 @ default: 32K dcache size (*2) 839 mov r11, #32 @ default: 32 byte line size 840 mrc p15, 0, r3, c0, c0, 1 @ read cache type 841 teq r3, r6 @ cache ID register present? 842 beq no_cache_id 843 mov r1, r3, lsr #18 844 and r1, r1, #7 845 mov r2, #1024 846 mov r2, r2, lsl r1 @ base dcache size *2 847 tst r3, #1 << 14 @ test M bit 848 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 849 mov r3, r3, lsr #12 850 and r3, r3, #3 851 mov r11, #8 852 mov r11, r11, lsl r3 @ cache line size in bytes 853no_cache_id: 854 bic r1, pc, #63 @ align to longest cache line 855 add r2, r1, r2 8561: ldr r3, [r1], r11 @ s/w flush D cache 857 teq r1, r2 858 bne 1b 859 860 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 861 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 862 mcr p15, 0, r1, c7, c10, 4 @ drain WB 863 mov pc, lr 864 865__armv3_mmu_cache_flush: 866__armv3_mpu_cache_flush: 867 mov r1, #0 868 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 869 mov pc, lr 870 871/* 872 * Various debugging routines for printing hex characters and 873 * memory, which again must be relocatable. 874 */ 875#ifdef DEBUG 876 .type phexbuf,#object 877phexbuf: .space 12 878 .size phexbuf, . - phexbuf 879 880phex: adr r3, phexbuf 881 mov r2, #0 882 strb r2, [r3, r1] 8831: subs r1, r1, #1 884 movmi r0, r3 885 bmi puts 886 and r2, r0, #15 887 mov r0, r0, lsr #4 888 cmp r2, #10 889 addge r2, r2, #7 890 add r2, r2, #'0' 891 strb r2, [r3, r1] 892 b 1b 893 894puts: loadsp r3 8951: ldrb r2, [r0], #1 896 teq r2, #0 897 moveq pc, lr 8982: writeb r2, r3 899 mov r1, #0x00020000 9003: subs r1, r1, #1 901 bne 3b 902 teq r2, #'\n' 903 moveq r2, #'\r' 904 beq 2b 905 teq r0, #0 906 bne 1b 907 mov pc, lr 908putc: 909 mov r2, r0 910 mov r0, #0 911 loadsp r3 912 b 2b 913 914memdump: mov r12, r0 915 mov r10, lr 916 mov r11, #0 9172: mov r0, r11, lsl #2 918 add r0, r0, r12 919 mov r1, #8 920 bl phex 921 mov r0, #':' 922 bl putc 9231: mov r0, #' ' 924 bl putc 925 ldr r0, [r12, r11, lsl #2] 926 mov r1, #8 927 bl phex 928 and r0, r11, #7 929 teq r0, #3 930 moveq r0, #' ' 931 bleq putc 932 and r0, r11, #7 933 add r11, r11, #1 934 teq r0, #7 935 bne 1b 936 mov r0, #'\n' 937 bl putc 938 cmp r11, #64 939 blt 2b 940 mov pc, r10 941#endif 942 943 .ltorg 944reloc_end: 945 946 .align 947 .section ".stack", "w" 948user_stack: .space 4096 949