1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AXS101/AXS103 Software Development Platform 4 * 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 6 */ 7 8 #include <linux/of_fdt.h> 9 #include <linux/of_platform.h> 10 #include <linux/libfdt.h> 11 12 #include <asm/asm-offsets.h> 13 #include <asm/io.h> 14 #include <asm/mach_desc.h> 15 #include <soc/arc/mcip.h> 16 17 #define AXS_MB_CGU 0xE0010000 18 #define AXS_MB_CREG 0xE0011000 19 20 #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214) 21 #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220) 22 #define CREG_MB_VER (AXS_MB_CREG + 0x230) 23 #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234) 24 25 #define AXC001_CREG 0xF0001000 26 #define AXC001_GPIO_INTC 0xF0003000 27 28 static void __init axs10x_enable_gpio_intc_wire(void) 29 { 30 /* 31 * Peripherals on CPU Card and Mother Board are wired to cpu intc via 32 * intermediate DW APB GPIO blocks (mainly for debouncing) 33 * 34 * --------------------- 35 * | snps,arc700-intc | 36 * --------------------- 37 * | #7 | #15 38 * ------------------- ------------------- 39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | 40 * ------------------- ------------------- 41 * | #12 | 42 * | [ Debug UART on cpu card ] 43 * | 44 * ------------------------ 45 * | snps,dw-apb-intc (MB)| 46 * ------------------------ 47 * | | | | 48 * [eth] [uart] [... other perip on Main Board] 49 * 50 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well 51 * with stacked INTCs. In particular problem happens if its master INTC 52 * not yet instantiated. See discussion here - 53 * https://lore.kernel.org/lkml/54F6FE2C.7020309@synopsys.com 54 * 55 * So setup the first gpio block as a passive pass thru and hide it from 56 * DT hardware topology - connect MB intc directly to cpu intc 57 * The GPIO "wire" needs to be init nevertheless (here) 58 * 59 * One side adv is that peripheral interrupt handling avoids one nested 60 * intc ISR hop 61 */ 62 #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) 63 #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) 64 #define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38) 65 #define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c) 66 #define MB_TO_GPIO_IRQ 12 67 68 iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK); 69 iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL); 70 iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY); 71 iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); 72 } 73 74 static void __init axs10x_print_board_ver(unsigned int creg, const char *str) 75 { 76 union ver { 77 struct { 78 #ifdef CONFIG_CPU_BIG_ENDIAN 79 unsigned int pad:11, y:12, m:4, d:5; 80 #else 81 unsigned int d:5, m:4, y:12, pad:11; 82 #endif 83 }; 84 unsigned int val; 85 } board; 86 87 board.val = ioread32((void __iomem *)creg); 88 pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m, 89 board.y); 90 } 91 92 static void __init axs10x_early_init(void) 93 { 94 int mb_rev; 95 char mb[32]; 96 97 /* Determine motherboard version */ 98 if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28)) 99 mb_rev = 3; /* HT-3 (rev3.0) */ 100 else 101 mb_rev = 2; /* HT-2 (rev2.0) */ 102 103 axs10x_enable_gpio_intc_wire(); 104 105 scnprintf(mb, 32, "MainBoard v%d", mb_rev); 106 axs10x_print_board_ver(CREG_MB_VER, mb); 107 } 108 109 #ifdef CONFIG_AXS101 110 111 #define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) 112 #define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) 113 #define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) 114 #define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) 115 116 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) 117 #define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) 118 119 /* 120 * Set up System Memory Map for ARC cpu / peripherals controllers 121 * 122 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each 123 * of which maps to a corresponding 256MB aperture in Target slave memory map. 124 * 125 * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0 126 * (0x0000_0000) of DDR Port 0 (slave #1) 127 * 128 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel: 129 * which has master/slaves on both ends. 130 * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14 131 * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to 132 * MB AXI Tunnel Master, which also has a mem map setup 133 * 134 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup 135 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master 136 */ 137 struct aperture { 138 unsigned int slave_sel:4, slave_off:4, pad:24; 139 }; 140 141 /* CPU Card target slaves */ 142 #define AXC001_SLV_NONE 0 143 #define AXC001_SLV_DDR_PORT0 1 144 #define AXC001_SLV_SRAM 2 145 #define AXC001_SLV_AXI_TUNNEL 3 146 #define AXC001_SLV_AXI2APB 6 147 #define AXC001_SLV_DDR_PORT1 7 148 149 /* MB AXI Target slaves */ 150 #define AXS_MB_SLV_NONE 0 151 #define AXS_MB_SLV_AXI_TUNNEL_CPU 1 152 #define AXS_MB_SLV_AXI_TUNNEL_HAPS 2 153 #define AXS_MB_SLV_SRAM 3 154 #define AXS_MB_SLV_CONTROL 4 155 156 /* MB AXI masters */ 157 #define AXS_MB_MST_TUNNEL_CPU 0 158 #define AXS_MB_MST_USB_OHCI 10 159 160 /* 161 * memmap for ARC core on CPU Card 162 */ 163 static const struct aperture axc001_memmap[16] = { 164 {AXC001_SLV_AXI_TUNNEL, 0x0}, 165 {AXC001_SLV_AXI_TUNNEL, 0x1}, 166 {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */ 167 {AXC001_SLV_NONE, 0x0}, 168 {AXC001_SLV_NONE, 0x0}, 169 {AXC001_SLV_NONE, 0x0}, 170 {AXC001_SLV_NONE, 0x0}, 171 {AXC001_SLV_NONE, 0x0}, 172 {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */ 173 {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */ 174 {AXC001_SLV_DDR_PORT0, 0x2}, 175 {AXC001_SLV_DDR_PORT0, 0x3}, 176 {AXC001_SLV_NONE, 0x0}, 177 {AXC001_SLV_AXI_TUNNEL, 0xD}, 178 {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */ 179 {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */ 180 }; 181 182 /* 183 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers) 184 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR 185 */ 186 static const struct aperture axc001_axi_tunnel_memmap[16] = { 187 {AXC001_SLV_AXI_TUNNEL, 0x0}, 188 {AXC001_SLV_AXI_TUNNEL, 0x1}, 189 {AXC001_SLV_SRAM, 0x0}, 190 {AXC001_SLV_NONE, 0x0}, 191 {AXC001_SLV_NONE, 0x0}, 192 {AXC001_SLV_NONE, 0x0}, 193 {AXC001_SLV_NONE, 0x0}, 194 {AXC001_SLV_NONE, 0x0}, 195 {AXC001_SLV_DDR_PORT1, 0x0}, 196 {AXC001_SLV_DDR_PORT1, 0x1}, 197 {AXC001_SLV_DDR_PORT1, 0x2}, 198 {AXC001_SLV_DDR_PORT1, 0x3}, 199 {AXC001_SLV_NONE, 0x0}, 200 {AXC001_SLV_AXI_TUNNEL, 0xD}, 201 {AXC001_SLV_AXI_TUNNEL, 0xE}, 202 {AXC001_SLV_AXI2APB, 0x0}, 203 }; 204 205 /* 206 * memmap for MB AXI Masters 207 * Same mem map for all perip controllers as well as MB AXI Tunnel Master 208 */ 209 static const struct aperture axs_mb_memmap[16] = { 210 {AXS_MB_SLV_SRAM, 0x0}, 211 {AXS_MB_SLV_SRAM, 0x0}, 212 {AXS_MB_SLV_NONE, 0x0}, 213 {AXS_MB_SLV_NONE, 0x0}, 214 {AXS_MB_SLV_NONE, 0x0}, 215 {AXS_MB_SLV_NONE, 0x0}, 216 {AXS_MB_SLV_NONE, 0x0}, 217 {AXS_MB_SLV_NONE, 0x0}, 218 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */ 219 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */ 220 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA}, 221 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB}, 222 {AXS_MB_SLV_NONE, 0x0}, 223 {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD}, 224 {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */ 225 {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF}, 226 }; 227 228 static noinline void __init 229 axs101_set_memmap(void __iomem *base, const struct aperture map[16]) 230 { 231 unsigned int slave_select, slave_offset; 232 int i; 233 234 slave_select = slave_offset = 0; 235 for (i = 0; i < 8; i++) { 236 slave_select |= map[i].slave_sel << (i << 2); 237 slave_offset |= map[i].slave_off << (i << 2); 238 } 239 240 iowrite32(slave_select, base + 0x0); /* SLV0 */ 241 iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ 242 243 slave_select = slave_offset = 0; 244 for (i = 0; i < 8; i++) { 245 slave_select |= map[i+8].slave_sel << (i << 2); 246 slave_offset |= map[i+8].slave_off << (i << 2); 247 } 248 249 iowrite32(slave_select, base + 0x4); /* SLV1 */ 250 iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ 251 } 252 253 static void __init axs101_early_init(void) 254 { 255 int i; 256 257 /* ARC 770D memory view */ 258 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap); 259 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD); 260 261 /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ 262 axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN, 263 axc001_axi_tunnel_memmap); 264 iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD); 265 266 /* MB peripherals memory map */ 267 for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++) 268 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4), 269 axs_mb_memmap); 270 271 iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */ 272 273 /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */ 274 iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); 275 276 /* Set up the MB interrupt system: mux interrupts to GPIO7) */ 277 iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); 278 279 /* reset ethernet and ULPI interfaces */ 280 iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET); 281 282 /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */ 283 iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX); 284 285 axs10x_early_init(); 286 } 287 288 #endif /* CONFIG_AXS101 */ 289 290 #ifdef CONFIG_AXS103 291 292 #define AXC003_CREG 0xF0001000 293 #define AXC003_MST_AXI_TUNNEL 0 294 #define AXC003_MST_HS38 1 295 296 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440) 297 #define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480) 298 #define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494) 299 300 301 static void __init axs103_early_init(void) 302 { 303 #ifdef CONFIG_ARC_MCIP 304 /* 305 * AXS103 configurations for SMP/QUAD configurations share device tree 306 * which defaults to 100 MHz. However recent failures of Quad config 307 * revealed P&R timing violations so clamp it down to safe 50 MHz 308 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack 309 * of fudging the freq in DT 310 */ 311 #define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000 312 313 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; 314 if (num_cores > 2) { 315 u32 freq; 316 int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); 317 const struct fdt_property *prop; 318 319 prop = fdt_get_property(initial_boot_params, off, 320 "assigned-clock-rates", NULL); 321 freq = be32_to_cpu(*(u32 *)(prop->data)); 322 323 /* Patching .dtb in-place with new core clock value */ 324 if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) { 325 freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ); 326 fdt_setprop_inplace(initial_boot_params, off, 327 "assigned-clock-rates", &freq, sizeof(freq)); 328 } 329 } 330 #endif 331 332 /* Memory maps already config in pre-bootloader */ 333 334 /* set GPIO mux to UART */ 335 iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); 336 337 iowrite32((0x00100000U | 0x000C0000U | 0x00003322U), 338 (void __iomem *) CREG_CPU_TUN_IO_CTRL); 339 340 /* Set up the AXS_MB interrupt system.*/ 341 iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX 342 + (AXC003_MST_HS38 << 2))); 343 344 /* connect ICTL - Main Board with GPIO line */ 345 iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); 346 347 axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card"); 348 349 axs10x_early_init(); 350 } 351 #endif 352 353 #ifdef CONFIG_AXS101 354 355 static const char *axs101_compat[] __initconst = { 356 "snps,axs101", 357 NULL, 358 }; 359 360 MACHINE_START(AXS101, "axs101") 361 .dt_compat = axs101_compat, 362 .init_early = axs101_early_init, 363 MACHINE_END 364 365 #endif /* CONFIG_AXS101 */ 366 367 #ifdef CONFIG_AXS103 368 369 static const char *axs103_compat[] __initconst = { 370 "snps,axs103", 371 NULL, 372 }; 373 374 MACHINE_START(AXS103, "axs103") 375 .dt_compat = axs103_compat, 376 .init_early = axs103_early_init, 377 MACHINE_END 378 379 /* 380 * For the VDK OS-kit, to get the offset to pid and command fields 381 */ 382 char coware_swa_pid_offset[TASK_PID]; 383 char coware_swa_comm_offset[TASK_COMM]; 384 385 #endif /* CONFIG_AXS103 */ 386