xref: /openbmc/linux/arch/arc/plat-axs10x/axs10x.c (revision 99fee508)
1 /*
2  * AXS101/AXS103 Software Development Platform
3  *
4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16 
17 #include <linux/of_fdt.h>
18 #include <linux/of_platform.h>
19 #include <linux/libfdt.h>
20 
21 #include <asm/asm-offsets.h>
22 #include <asm/io.h>
23 #include <asm/mach_desc.h>
24 #include <soc/arc/mcip.h>
25 
26 #define AXS_MB_CGU		0xE0010000
27 #define AXS_MB_CREG		0xE0011000
28 
29 #define CREG_MB_IRQ_MUX		(AXS_MB_CREG + 0x214)
30 #define CREG_MB_SW_RESET	(AXS_MB_CREG + 0x220)
31 #define CREG_MB_VER		(AXS_MB_CREG + 0x230)
32 #define CREG_MB_CONFIG		(AXS_MB_CREG + 0x234)
33 
34 #define AXC001_CREG		0xF0001000
35 #define AXC001_GPIO_INTC	0xF0003000
36 
37 static void __init axs10x_enable_gpio_intc_wire(void)
38 {
39 	/*
40 	 * Peripherals on CPU Card and Mother Board are wired to cpu intc via
41 	 * intermediate DW APB GPIO blocks (mainly for debouncing)
42 	 *
43 	 *         ---------------------
44 	 *        |  snps,arc700-intc |
45 	 *        ---------------------
46 	 *          | #7          | #15
47 	 * -------------------   -------------------
48 	 * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
49 	 * -------------------   -------------------
50 	 *        | #12                     |
51 	 *        |                 [ Debug UART on cpu card ]
52 	 *        |
53 	 * ------------------------
54 	 * | snps,dw-apb-intc (MB)|
55 	 * ------------------------
56 	 *  |      |       |      |
57 	 * [eth] [uart]        [... other perip on Main Board]
58 	 *
59 	 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
60 	 * with stacked INTCs. In particular problem happens if its master INTC
61 	 * not yet instantiated. See discussion here -
62 	 * https://lkml.org/lkml/2015/3/4/755
63 	 *
64 	 * So setup the first gpio block as a passive pass thru and hide it from
65 	 * DT hardware topology - connect MB intc directly to cpu intc
66 	 * The GPIO "wire" needs to be init nevertheless (here)
67 	 *
68 	 * One side adv is that peripheral interrupt handling avoids one nested
69 	 * intc ISR hop
70 	 */
71 #define GPIO_INTEN		(AXC001_GPIO_INTC + 0x30)
72 #define GPIO_INTMASK		(AXC001_GPIO_INTC + 0x34)
73 #define GPIO_INTTYPE_LEVEL	(AXC001_GPIO_INTC + 0x38)
74 #define GPIO_INT_POLARITY	(AXC001_GPIO_INTC + 0x3c)
75 #define MB_TO_GPIO_IRQ		12
76 
77 	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
78 	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
79 	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
80 	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
81 }
82 
83 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
84 {
85 	union ver {
86 		struct {
87 #ifdef CONFIG_CPU_BIG_ENDIAN
88 			unsigned int pad:11, y:12, m:4, d:5;
89 #else
90 			unsigned int d:5, m:4, y:12, pad:11;
91 #endif
92 		};
93 		unsigned int val;
94 	} board;
95 
96 	board.val = ioread32((void __iomem *)creg);
97 	pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
98 		board.y);
99 }
100 
101 static void __init axs10x_early_init(void)
102 {
103 	int mb_rev;
104 	char mb[32];
105 
106 	/* Determine motherboard version */
107 	if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
108 		mb_rev = 3;	/* HT-3 (rev3.0) */
109 	else
110 		mb_rev = 2;	/* HT-2 (rev2.0) */
111 
112 	axs10x_enable_gpio_intc_wire();
113 
114 	/*
115 	 * Reset ethernet IP core.
116 	 * TODO: get rid of this quirk after axs10x reset driver (or simple
117 	 * reset driver) will be available in upstream.
118 	 */
119 	iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
120 
121 	scnprintf(mb, 32, "MainBoard v%d", mb_rev);
122 	axs10x_print_board_ver(CREG_MB_VER, mb);
123 }
124 
125 #ifdef CONFIG_AXS101
126 
127 #define CREG_CPU_ADDR_770	(AXC001_CREG + 0x20)
128 #define CREG_CPU_ADDR_TUNN	(AXC001_CREG + 0x60)
129 #define CREG_CPU_ADDR_770_UPD	(AXC001_CREG + 0x34)
130 #define CREG_CPU_ADDR_TUNN_UPD	(AXC001_CREG + 0x74)
131 
132 #define CREG_CPU_ARC770_IRQ_MUX	(AXC001_CREG + 0x114)
133 #define CREG_CPU_GPIO_UART_MUX	(AXC001_CREG + 0x120)
134 
135 /*
136  * Set up System Memory Map for ARC cpu / peripherals controllers
137  *
138  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
139  * of which maps to a corresponding 256MB aperture in Target slave memory map.
140  *
141  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
142  * (0x0000_0000) of DDR Port 0 (slave #1)
143  *
144  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
145  * which has master/slaves on both ends.
146  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
147  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
148  * MB AXI Tunnel Master, which also has a mem map setup
149  *
150  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
151  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
152  */
153 struct aperture {
154 	unsigned int slave_sel:4, slave_off:4, pad:24;
155 };
156 
157 /* CPU Card target slaves */
158 #define AXC001_SLV_NONE			0
159 #define AXC001_SLV_DDR_PORT0		1
160 #define AXC001_SLV_SRAM			2
161 #define AXC001_SLV_AXI_TUNNEL		3
162 #define AXC001_SLV_AXI2APB		6
163 #define AXC001_SLV_DDR_PORT1		7
164 
165 /* MB AXI Target slaves */
166 #define AXS_MB_SLV_NONE			0
167 #define AXS_MB_SLV_AXI_TUNNEL_CPU	1
168 #define AXS_MB_SLV_AXI_TUNNEL_HAPS	2
169 #define AXS_MB_SLV_SRAM			3
170 #define AXS_MB_SLV_CONTROL		4
171 
172 /* MB AXI masters */
173 #define AXS_MB_MST_TUNNEL_CPU		0
174 #define AXS_MB_MST_USB_OHCI		10
175 
176 /*
177  * memmap for ARC core on CPU Card
178  */
179 static const struct aperture axc001_memmap[16] = {
180 	{AXC001_SLV_AXI_TUNNEL,		0x0},
181 	{AXC001_SLV_AXI_TUNNEL,		0x1},
182 	{AXC001_SLV_SRAM,		0x0}, /* 0x2000_0000: Local SRAM */
183 	{AXC001_SLV_NONE,		0x0},
184 	{AXC001_SLV_NONE,		0x0},
185 	{AXC001_SLV_NONE,		0x0},
186 	{AXC001_SLV_NONE,		0x0},
187 	{AXC001_SLV_NONE,		0x0},
188 	{AXC001_SLV_DDR_PORT0,		0x0}, /* 0x8000_0000: DDR   0..256M */
189 	{AXC001_SLV_DDR_PORT0,		0x1}, /* 0x9000_0000: DDR 256..512M */
190 	{AXC001_SLV_DDR_PORT0,		0x2},
191 	{AXC001_SLV_DDR_PORT0,		0x3},
192 	{AXC001_SLV_NONE,		0x0},
193 	{AXC001_SLV_AXI_TUNNEL,		0xD},
194 	{AXC001_SLV_AXI_TUNNEL,		0xE}, /* MB: CREG, CGU... */
195 	{AXC001_SLV_AXI2APB,		0x0}, /* CPU Card local CREG, CGU... */
196 };
197 
198 /*
199  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
200  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
201  */
202 static const struct aperture axc001_axi_tunnel_memmap[16] = {
203 	{AXC001_SLV_AXI_TUNNEL,		0x0},
204 	{AXC001_SLV_AXI_TUNNEL,		0x1},
205 	{AXC001_SLV_SRAM,		0x0},
206 	{AXC001_SLV_NONE,		0x0},
207 	{AXC001_SLV_NONE,		0x0},
208 	{AXC001_SLV_NONE,		0x0},
209 	{AXC001_SLV_NONE,		0x0},
210 	{AXC001_SLV_NONE,		0x0},
211 	{AXC001_SLV_DDR_PORT1,		0x0},
212 	{AXC001_SLV_DDR_PORT1,		0x1},
213 	{AXC001_SLV_DDR_PORT1,		0x2},
214 	{AXC001_SLV_DDR_PORT1,		0x3},
215 	{AXC001_SLV_NONE,		0x0},
216 	{AXC001_SLV_AXI_TUNNEL,		0xD},
217 	{AXC001_SLV_AXI_TUNNEL,		0xE},
218 	{AXC001_SLV_AXI2APB,		0x0},
219 };
220 
221 /*
222  * memmap for MB AXI Masters
223  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
224  */
225 static const struct aperture axs_mb_memmap[16] = {
226 	{AXS_MB_SLV_SRAM,		0x0},
227 	{AXS_MB_SLV_SRAM,		0x0},
228 	{AXS_MB_SLV_NONE,		0x0},
229 	{AXS_MB_SLV_NONE,		0x0},
230 	{AXS_MB_SLV_NONE,		0x0},
231 	{AXS_MB_SLV_NONE,		0x0},
232 	{AXS_MB_SLV_NONE,		0x0},
233 	{AXS_MB_SLV_NONE,		0x0},
234 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x8},	/* DDR on CPU Card */
235 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x9},	/* DDR on CPU Card */
236 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xA},
237 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xB},
238 	{AXS_MB_SLV_NONE,		0x0},
239 	{AXS_MB_SLV_AXI_TUNNEL_HAPS,	0xD},
240 	{AXS_MB_SLV_CONTROL,		0x0},	/* MB Local CREG, CGU... */
241 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xF},
242 };
243 
244 static noinline void __init
245 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
246 {
247 	unsigned int slave_select, slave_offset;
248 	int i;
249 
250 	slave_select = slave_offset = 0;
251 	for (i = 0; i < 8; i++) {
252 		slave_select |= map[i].slave_sel << (i << 2);
253 		slave_offset |= map[i].slave_off << (i << 2);
254 	}
255 
256 	iowrite32(slave_select, base + 0x0);	/* SLV0 */
257 	iowrite32(slave_offset, base + 0x8);	/* OFFSET0 */
258 
259 	slave_select = slave_offset = 0;
260 	for (i = 0; i < 8; i++) {
261 		slave_select |= map[i+8].slave_sel << (i << 2);
262 		slave_offset |= map[i+8].slave_off << (i << 2);
263 	}
264 
265 	iowrite32(slave_select, base + 0x4);	/* SLV1 */
266 	iowrite32(slave_offset, base + 0xC);	/* OFFSET1 */
267 }
268 
269 static void __init axs101_early_init(void)
270 {
271 	int i;
272 
273 	/* ARC 770D memory view */
274 	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
275 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
276 
277 	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */
278 	axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
279 			      axc001_axi_tunnel_memmap);
280 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
281 
282 	/* MB peripherals memory map */
283 	for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
284 		axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
285 				      axs_mb_memmap);
286 
287 	iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
288 
289 	/* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
290 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
291 
292 	/* Set up the MB interrupt system: mux interrupts to GPIO7) */
293 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
294 
295 	/* reset ethernet and ULPI interfaces */
296 	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
297 
298 	/* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
299 	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
300 
301 	axs10x_early_init();
302 }
303 
304 #endif	/* CONFIG_AXS101 */
305 
306 #ifdef CONFIG_AXS103
307 
308 #define AXC003_CREG	0xF0001000
309 #define AXC003_MST_AXI_TUNNEL	0
310 #define AXC003_MST_HS38		1
311 
312 #define CREG_CPU_AXI_M0_IRQ_MUX	(AXC003_CREG + 0x440)
313 #define CREG_CPU_GPIO_UART_MUX	(AXC003_CREG + 0x480)
314 #define CREG_CPU_TUN_IO_CTRL	(AXC003_CREG + 0x494)
315 
316 
317 static void __init axs103_early_init(void)
318 {
319 #ifdef CONFIG_ARC_MCIP
320 	/*
321 	 * AXS103 configurations for SMP/QUAD configurations share device tree
322 	 * which defaults to 100 MHz. However recent failures of Quad config
323 	 * revealed P&R timing violations so clamp it down to safe 50 MHz
324 	 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
325 	 * of fudging the freq in DT
326 	 */
327 	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
328 	if (num_cores > 2) {
329 		u32 freq = 50, orig;
330 		/*
331 		 * TODO: use cpu node "cpu-freq" param instead of platform-specific
332 		 * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
333 		 */
334 		int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
335 		const struct fdt_property *prop;
336 
337 		prop = fdt_get_property(initial_boot_params, off,
338 					"clock-frequency", NULL);
339 		orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
340 
341 		/* Patching .dtb in-place with new core clock value */
342 		if (freq != orig ) {
343 			freq = cpu_to_be32(freq * 1000000);
344 			fdt_setprop_inplace(initial_boot_params, off,
345 					    "clock-frequency", &freq, sizeof(freq));
346 		}
347 	}
348 #endif
349 
350 	/* Memory maps already config in pre-bootloader */
351 
352 	/* set GPIO mux to UART */
353 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
354 
355 	iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
356 		  (void __iomem *) CREG_CPU_TUN_IO_CTRL);
357 
358 	/* Set up the AXS_MB interrupt system.*/
359 	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
360 					 + (AXC003_MST_HS38 << 2)));
361 
362 	/* connect ICTL - Main Board with GPIO line */
363 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
364 
365 	axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
366 
367 	axs10x_early_init();
368 }
369 #endif
370 
371 #ifdef CONFIG_AXS101
372 
373 static const char *axs101_compat[] __initconst = {
374 	"snps,axs101",
375 	NULL,
376 };
377 
378 MACHINE_START(AXS101, "axs101")
379 	.dt_compat	= axs101_compat,
380 	.init_early	= axs101_early_init,
381 MACHINE_END
382 
383 #endif	/* CONFIG_AXS101 */
384 
385 #ifdef CONFIG_AXS103
386 
387 static const char *axs103_compat[] __initconst = {
388 	"snps,axs103",
389 	NULL,
390 };
391 
392 MACHINE_START(AXS103, "axs103")
393 	.dt_compat	= axs103_compat,
394 	.init_early	= axs103_early_init,
395 MACHINE_END
396 
397 /*
398  * For the VDK OS-kit, to get the offset to pid and command fields
399  */
400 char coware_swa_pid_offset[TASK_PID];
401 char coware_swa_comm_offset[TASK_COMM];
402 
403 #endif	/* CONFIG_AXS103 */
404