1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 /* 10 * DMA Coherent API Notes 11 * 12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is 13 * implemented by accessing it using a kernel virtual address, with 14 * Cache bit off in the TLB entry. 15 * 16 * The default DMA address == Phy address which is 0x8000_0000 based. 17 */ 18 19 #include <linux/dma-mapping.h> 20 #include <asm/cache.h> 21 #include <asm/cacheflush.h> 22 23 24 static void *arc_dma_alloc(struct device *dev, size_t size, 25 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 26 { 27 unsigned long order = get_order(size); 28 struct page *page; 29 phys_addr_t paddr; 30 void *kvaddr; 31 int need_coh = 1, need_kvaddr = 0; 32 33 page = alloc_pages(gfp, order); 34 if (!page) 35 return NULL; 36 37 /* 38 * IOC relies on all data (even coherent DMA data) being in cache 39 * Thus allocate normal cached memory 40 * 41 * The gains with IOC are two pronged: 42 * -For streaming data, elides need for cache maintenance, saving 43 * cycles in flush code, and bus bandwidth as all the lines of a 44 * buffer need to be flushed out to memory 45 * -For coherent data, Read/Write to buffers terminate early in cache 46 * (vs. always going to memory - thus are faster) 47 */ 48 if ((is_isa_arcv2() && ioc_exists) || 49 (attrs & DMA_ATTR_NON_CONSISTENT)) 50 need_coh = 0; 51 52 /* 53 * - A coherent buffer needs MMU mapping to enforce non-cachability 54 * - A highmem page needs a virtual handle (hence MMU mapping) 55 * independent of cachability 56 */ 57 if (PageHighMem(page) || need_coh) 58 need_kvaddr = 1; 59 60 /* This is linear addr (0x8000_0000 based) */ 61 paddr = page_to_phys(page); 62 63 *dma_handle = plat_phys_to_dma(dev, paddr); 64 65 /* This is kernel Virtual address (0x7000_0000 based) */ 66 if (need_kvaddr) { 67 kvaddr = ioremap_nocache(paddr, size); 68 if (kvaddr == NULL) { 69 __free_pages(page, order); 70 return NULL; 71 } 72 } else { 73 kvaddr = (void *)(u32)paddr; 74 } 75 76 /* 77 * Evict any existing L1 and/or L2 lines for the backing page 78 * in case it was used earlier as a normal "cached" page. 79 * Yeah this bit us - STAR 9000898266 80 * 81 * Although core does call flush_cache_vmap(), it gets kvaddr hence 82 * can't be used to efficiently flush L1 and/or L2 which need paddr 83 * Currently flush_cache_vmap nukes the L1 cache completely which 84 * will be optimized as a separate commit 85 */ 86 if (need_coh) 87 dma_cache_wback_inv(paddr, size); 88 89 return kvaddr; 90 } 91 92 static void arc_dma_free(struct device *dev, size_t size, void *vaddr, 93 dma_addr_t dma_handle, unsigned long attrs) 94 { 95 phys_addr_t paddr = plat_dma_to_phys(dev, dma_handle); 96 struct page *page = virt_to_page(paddr); 97 int is_non_coh = 1; 98 99 is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) || 100 (is_isa_arcv2() && ioc_exists); 101 102 if (PageHighMem(page) || !is_non_coh) 103 iounmap((void __force __iomem *)vaddr); 104 105 __free_pages(page, get_order(size)); 106 } 107 108 /* 109 * streaming DMA Mapping API... 110 * CPU accesses page via normal paddr, thus needs to explicitly made 111 * consistent before each use 112 */ 113 static void _dma_cache_sync(phys_addr_t paddr, size_t size, 114 enum dma_data_direction dir) 115 { 116 switch (dir) { 117 case DMA_FROM_DEVICE: 118 dma_cache_inv(paddr, size); 119 break; 120 case DMA_TO_DEVICE: 121 dma_cache_wback(paddr, size); 122 break; 123 case DMA_BIDIRECTIONAL: 124 dma_cache_wback_inv(paddr, size); 125 break; 126 default: 127 pr_err("Invalid DMA dir [%d] for OP @ %pa[p]\n", dir, &paddr); 128 } 129 } 130 131 static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, 132 unsigned long offset, size_t size, enum dma_data_direction dir, 133 unsigned long attrs) 134 { 135 phys_addr_t paddr = page_to_phys(page) + offset; 136 _dma_cache_sync(paddr, size, dir); 137 return plat_phys_to_dma(dev, paddr); 138 } 139 140 static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, 141 int nents, enum dma_data_direction dir, unsigned long attrs) 142 { 143 struct scatterlist *s; 144 int i; 145 146 for_each_sg(sg, s, nents, i) 147 s->dma_address = dma_map_page(dev, sg_page(s), s->offset, 148 s->length, dir); 149 150 return nents; 151 } 152 153 static void arc_dma_sync_single_for_cpu(struct device *dev, 154 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) 155 { 156 _dma_cache_sync(plat_dma_to_phys(dev, dma_handle), size, DMA_FROM_DEVICE); 157 } 158 159 static void arc_dma_sync_single_for_device(struct device *dev, 160 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) 161 { 162 _dma_cache_sync(plat_dma_to_phys(dev, dma_handle), size, DMA_TO_DEVICE); 163 } 164 165 static void arc_dma_sync_sg_for_cpu(struct device *dev, 166 struct scatterlist *sglist, int nelems, 167 enum dma_data_direction dir) 168 { 169 int i; 170 struct scatterlist *sg; 171 172 for_each_sg(sglist, sg, nelems, i) 173 _dma_cache_sync(sg_phys(sg), sg->length, dir); 174 } 175 176 static void arc_dma_sync_sg_for_device(struct device *dev, 177 struct scatterlist *sglist, int nelems, 178 enum dma_data_direction dir) 179 { 180 int i; 181 struct scatterlist *sg; 182 183 for_each_sg(sglist, sg, nelems, i) 184 _dma_cache_sync(sg_phys(sg), sg->length, dir); 185 } 186 187 static int arc_dma_supported(struct device *dev, u64 dma_mask) 188 { 189 /* Support 32 bit DMA mask exclusively */ 190 return dma_mask == DMA_BIT_MASK(32); 191 } 192 193 struct dma_map_ops arc_dma_ops = { 194 .alloc = arc_dma_alloc, 195 .free = arc_dma_free, 196 .map_page = arc_dma_map_page, 197 .map_sg = arc_dma_map_sg, 198 .sync_single_for_device = arc_dma_sync_single_for_device, 199 .sync_single_for_cpu = arc_dma_sync_single_for_cpu, 200 .sync_sg_for_cpu = arc_dma_sync_sg_for_cpu, 201 .sync_sg_for_device = arc_dma_sync_sg_for_device, 202 .dma_supported = arc_dma_supported, 203 }; 204 EXPORT_SYMBOL(arc_dma_ops); 205