18362c389SVineet Gupta /* 28362c389SVineet Gupta * ARC700 VIPT Cache Management 38362c389SVineet Gupta * 48362c389SVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 58362c389SVineet Gupta * 68362c389SVineet Gupta * This program is free software; you can redistribute it and/or modify 78362c389SVineet Gupta * it under the terms of the GNU General Public License version 2 as 88362c389SVineet Gupta * published by the Free Software Foundation. 98362c389SVineet Gupta * 108362c389SVineet Gupta * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs 118362c389SVineet Gupta * -flush_cache_dup_mm (fork) 128362c389SVineet Gupta * -likewise for flush_cache_mm (exit/execve) 138362c389SVineet Gupta * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break) 148362c389SVineet Gupta * 158362c389SVineet Gupta * vineetg: Apr 2011 168362c389SVineet Gupta * -Now that MMU can support larger pg sz (16K), the determiniation of 178362c389SVineet Gupta * aliasing shd not be based on assumption of 8k pg 188362c389SVineet Gupta * 198362c389SVineet Gupta * vineetg: Mar 2011 208362c389SVineet Gupta * -optimised version of flush_icache_range( ) for making I/D coherent 218362c389SVineet Gupta * when vaddr is available (agnostic of num of aliases) 228362c389SVineet Gupta * 238362c389SVineet Gupta * vineetg: Mar 2011 248362c389SVineet Gupta * -Added documentation about I-cache aliasing on ARC700 and the way it 258362c389SVineet Gupta * was handled up until MMU V2. 268362c389SVineet Gupta * -Spotted a three year old bug when killing the 4 aliases, which needs 278362c389SVineet Gupta * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03} 288362c389SVineet Gupta * instead of paddr | {0x00, 0x01, 0x10, 0x11} 298362c389SVineet Gupta * (Rajesh you owe me one now) 308362c389SVineet Gupta * 318362c389SVineet Gupta * vineetg: Dec 2010 328362c389SVineet Gupta * -Off-by-one error when computing num_of_lines to flush 338362c389SVineet Gupta * This broke signal handling with bionic which uses synthetic sigret stub 348362c389SVineet Gupta * 358362c389SVineet Gupta * vineetg: Mar 2010 368362c389SVineet Gupta * -GCC can't generate ZOL for core cache flush loops. 378362c389SVineet Gupta * Conv them into iterations based as opposed to while (start < end) types 388362c389SVineet Gupta * 398362c389SVineet Gupta * Vineetg: July 2009 408362c389SVineet Gupta * -In I-cache flush routine we used to chk for aliasing for every line INV. 418362c389SVineet Gupta * Instead now we setup routines per cache geometry and invoke them 428362c389SVineet Gupta * via function pointers. 438362c389SVineet Gupta * 448362c389SVineet Gupta * Vineetg: Jan 2009 458362c389SVineet Gupta * -Cache Line flush routines used to flush an extra line beyond end addr 468362c389SVineet Gupta * because check was while (end >= start) instead of (end > start) 478362c389SVineet Gupta * =Some call sites had to work around by doing -1, -4 etc to end param 488362c389SVineet Gupta * =Some callers didnt care. This was spec bad in case of INV routines 498362c389SVineet Gupta * which would discard valid data (cause of the horrible ext2 bug 508362c389SVineet Gupta * in ARC IDE driver) 518362c389SVineet Gupta * 528362c389SVineet Gupta * vineetg: June 11th 2008: Fixed flush_icache_range( ) 538362c389SVineet Gupta * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need 548362c389SVineet Gupta * to be flushed, which it was not doing. 558362c389SVineet Gupta * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API, 568362c389SVineet Gupta * however ARC cache maintenance OPs require PHY addr. Thus need to do 578362c389SVineet Gupta * vmalloc_to_phy. 588362c389SVineet Gupta * -Also added optimisation there, that for range > PAGE SIZE we flush the 598362c389SVineet Gupta * entire cache in one shot rather than line by line. For e.g. a module 608362c389SVineet Gupta * with Code sz 600k, old code flushed 600k worth of cache (line-by-line), 618362c389SVineet Gupta * while cache is only 16 or 32k. 628362c389SVineet Gupta */ 638362c389SVineet Gupta 648362c389SVineet Gupta #include <linux/module.h> 658362c389SVineet Gupta #include <linux/mm.h> 668362c389SVineet Gupta #include <linux/sched.h> 678362c389SVineet Gupta #include <linux/cache.h> 688362c389SVineet Gupta #include <linux/mmu_context.h> 698362c389SVineet Gupta #include <linux/syscalls.h> 708362c389SVineet Gupta #include <linux/uaccess.h> 718362c389SVineet Gupta #include <linux/pagemap.h> 728362c389SVineet Gupta #include <asm/cacheflush.h> 738362c389SVineet Gupta #include <asm/cachectl.h> 748362c389SVineet Gupta #include <asm/setup.h> 758362c389SVineet Gupta 768362c389SVineet Gupta char *arc_cache_mumbojumbo(int c, char *buf, int len) 778362c389SVineet Gupta { 788362c389SVineet Gupta int n = 0; 798362c389SVineet Gupta 808362c389SVineet Gupta #define PR_CACHE(p, cfg, str) \ 818362c389SVineet Gupta if (!(p)->ver) \ 828362c389SVineet Gupta n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ 838362c389SVineet Gupta else \ 848362c389SVineet Gupta n += scnprintf(buf + n, len - n, \ 858362c389SVineet Gupta str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ 868362c389SVineet Gupta (p)->sz_k, (p)->assoc, (p)->line_len, \ 878362c389SVineet Gupta (p)->vipt ? "VIPT" : "PIPT", \ 888362c389SVineet Gupta (p)->alias ? " aliasing" : "", \ 898362c389SVineet Gupta IS_ENABLED(cfg) ? "" : " (not used)"); 908362c389SVineet Gupta 918362c389SVineet Gupta PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); 928362c389SVineet Gupta PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); 938362c389SVineet Gupta 948362c389SVineet Gupta return buf; 958362c389SVineet Gupta } 968362c389SVineet Gupta 978362c389SVineet Gupta /* 988362c389SVineet Gupta * Read the Cache Build Confuration Registers, Decode them and save into 998362c389SVineet Gupta * the cpuinfo structure for later use. 1008362c389SVineet Gupta * No Validation done here, simply read/convert the BCRs 1018362c389SVineet Gupta */ 1028362c389SVineet Gupta void read_decode_cache_bcr(void) 1038362c389SVineet Gupta { 1048362c389SVineet Gupta struct cpuinfo_arc_cache *p_ic, *p_dc; 1058362c389SVineet Gupta unsigned int cpu = smp_processor_id(); 1068362c389SVineet Gupta struct bcr_cache { 1078362c389SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN 1088362c389SVineet Gupta unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 1098362c389SVineet Gupta #else 1108362c389SVineet Gupta unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 1118362c389SVineet Gupta #endif 1128362c389SVineet Gupta } ibcr, dbcr; 1138362c389SVineet Gupta 1148362c389SVineet Gupta p_ic = &cpuinfo_arc700[cpu].icache; 1158362c389SVineet Gupta READ_BCR(ARC_REG_IC_BCR, ibcr); 1168362c389SVineet Gupta 1178362c389SVineet Gupta if (!ibcr.ver) 1188362c389SVineet Gupta goto dc_chk; 1198362c389SVineet Gupta 1208362c389SVineet Gupta BUG_ON(ibcr.config != 3); 1218362c389SVineet Gupta p_ic->assoc = 2; /* Fixed to 2w set assoc */ 1228362c389SVineet Gupta p_ic->line_len = 8 << ibcr.line_len; 1238362c389SVineet Gupta p_ic->sz_k = 1 << (ibcr.sz - 1); 1248362c389SVineet Gupta p_ic->ver = ibcr.ver; 1258362c389SVineet Gupta p_ic->vipt = 1; 1268362c389SVineet Gupta p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; 1278362c389SVineet Gupta 1288362c389SVineet Gupta dc_chk: 1298362c389SVineet Gupta p_dc = &cpuinfo_arc700[cpu].dcache; 1308362c389SVineet Gupta READ_BCR(ARC_REG_DC_BCR, dbcr); 1318362c389SVineet Gupta 1328362c389SVineet Gupta if (!dbcr.ver) 1338362c389SVineet Gupta return; 1348362c389SVineet Gupta 1358362c389SVineet Gupta BUG_ON(dbcr.config != 2); 1368362c389SVineet Gupta p_dc->assoc = 4; /* Fixed to 4w set assoc */ 1378362c389SVineet Gupta p_dc->line_len = 16 << dbcr.line_len; 1388362c389SVineet Gupta p_dc->sz_k = 1 << (dbcr.sz - 1); 1398362c389SVineet Gupta p_dc->ver = dbcr.ver; 1408362c389SVineet Gupta p_dc->vipt = 1; 1418362c389SVineet Gupta p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; 1428362c389SVineet Gupta } 1438362c389SVineet Gupta 1448362c389SVineet Gupta /* 1458362c389SVineet Gupta * 1. Validate the Cache Geomtery (compile time config matches hardware) 1468362c389SVineet Gupta * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) 1478362c389SVineet Gupta * (aliasing D-cache configurations are not supported YET) 1488362c389SVineet Gupta * 3. Enable the Caches, setup default flush mode for D-Cache 1498362c389SVineet Gupta * 3. Calculate the SHMLBA used by user space 1508362c389SVineet Gupta */ 1518362c389SVineet Gupta void arc_cache_init(void) 1528362c389SVineet Gupta { 1538362c389SVineet Gupta unsigned int __maybe_unused cpu = smp_processor_id(); 1548362c389SVineet Gupta char str[256]; 1558362c389SVineet Gupta 1568362c389SVineet Gupta printk(arc_cache_mumbojumbo(0, str, sizeof(str))); 1578362c389SVineet Gupta 1588362c389SVineet Gupta if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { 1598362c389SVineet Gupta struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; 1608362c389SVineet Gupta 1618362c389SVineet Gupta if (!ic->ver) 1628362c389SVineet Gupta panic("cache support enabled but non-existent cache\n"); 1638362c389SVineet Gupta 1648362c389SVineet Gupta if (ic->line_len != L1_CACHE_BYTES) 1658362c389SVineet Gupta panic("ICache line [%d] != kernel Config [%d]", 1668362c389SVineet Gupta ic->line_len, L1_CACHE_BYTES); 1678362c389SVineet Gupta 1688362c389SVineet Gupta if (ic->ver != CONFIG_ARC_MMU_VER) 1698362c389SVineet Gupta panic("Cache ver [%d] doesn't match MMU ver [%d]\n", 1708362c389SVineet Gupta ic->ver, CONFIG_ARC_MMU_VER); 1718362c389SVineet Gupta } 1728362c389SVineet Gupta 1738362c389SVineet Gupta if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { 1748362c389SVineet Gupta struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; 1758362c389SVineet Gupta int handled; 1768362c389SVineet Gupta 1778362c389SVineet Gupta if (!dc->ver) 1788362c389SVineet Gupta panic("cache support enabled but non-existent cache\n"); 1798362c389SVineet Gupta 1808362c389SVineet Gupta if (dc->line_len != L1_CACHE_BYTES) 1818362c389SVineet Gupta panic("DCache line [%d] != kernel Config [%d]", 1828362c389SVineet Gupta dc->line_len, L1_CACHE_BYTES); 1838362c389SVineet Gupta 1848362c389SVineet Gupta /* check for D-Cache aliasing */ 1858362c389SVineet Gupta handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); 1868362c389SVineet Gupta 1878362c389SVineet Gupta if (dc->alias && !handled) 1888362c389SVineet Gupta panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 1898362c389SVineet Gupta else if (!dc->alias && handled) 1908362c389SVineet Gupta panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); 1918362c389SVineet Gupta } 1928362c389SVineet Gupta } 1938362c389SVineet Gupta 1948362c389SVineet Gupta #define OP_INV 0x1 1958362c389SVineet Gupta #define OP_FLUSH 0x2 1968362c389SVineet Gupta #define OP_FLUSH_N_INV 0x3 1978362c389SVineet Gupta #define OP_INV_IC 0x4 1988362c389SVineet Gupta 1998362c389SVineet Gupta /* 2008362c389SVineet Gupta * Common Helper for Line Operations on {I,D}-Cache 2018362c389SVineet Gupta */ 2028362c389SVineet Gupta static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, 2038362c389SVineet Gupta unsigned long sz, const int cacheop) 2048362c389SVineet Gupta { 2058362c389SVineet Gupta unsigned int aux_cmd, aux_tag; 2068362c389SVineet Gupta int num_lines; 2078362c389SVineet Gupta const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; 2088362c389SVineet Gupta 2098362c389SVineet Gupta if (cacheop == OP_INV_IC) { 2108362c389SVineet Gupta aux_cmd = ARC_REG_IC_IVIL; 2118362c389SVineet Gupta #if (CONFIG_ARC_MMU_VER > 2) 2128362c389SVineet Gupta aux_tag = ARC_REG_IC_PTAG; 2138362c389SVineet Gupta #endif 2148362c389SVineet Gupta } 2158362c389SVineet Gupta else { 2168362c389SVineet Gupta /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 2178362c389SVineet Gupta aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; 2188362c389SVineet Gupta #if (CONFIG_ARC_MMU_VER > 2) 2198362c389SVineet Gupta aux_tag = ARC_REG_DC_PTAG; 2208362c389SVineet Gupta #endif 2218362c389SVineet Gupta } 2228362c389SVineet Gupta 2238362c389SVineet Gupta /* Ensure we properly floor/ceil the non-line aligned/sized requests 2248362c389SVineet Gupta * and have @paddr - aligned to cache line and integral @num_lines. 2258362c389SVineet Gupta * This however can be avoided for page sized since: 2268362c389SVineet Gupta * -@paddr will be cache-line aligned already (being page aligned) 2278362c389SVineet Gupta * -@sz will be integral multiple of line size (being page sized). 2288362c389SVineet Gupta */ 2298362c389SVineet Gupta if (!full_page_op) { 2308362c389SVineet Gupta sz += paddr & ~CACHE_LINE_MASK; 2318362c389SVineet Gupta paddr &= CACHE_LINE_MASK; 2328362c389SVineet Gupta vaddr &= CACHE_LINE_MASK; 2338362c389SVineet Gupta } 2348362c389SVineet Gupta 2358362c389SVineet Gupta num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); 2368362c389SVineet Gupta 2378362c389SVineet Gupta #if (CONFIG_ARC_MMU_VER <= 2) 2388362c389SVineet Gupta /* MMUv2 and before: paddr contains stuffed vaddrs bits */ 2398362c389SVineet Gupta paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; 2408362c389SVineet Gupta #else 2418362c389SVineet Gupta /* if V-P const for loop, PTAG can be written once outside loop */ 2428362c389SVineet Gupta if (full_page_op) 2438362c389SVineet Gupta write_aux_reg(aux_tag, paddr); 2448362c389SVineet Gupta #endif 2458362c389SVineet Gupta 2468362c389SVineet Gupta while (num_lines-- > 0) { 2478362c389SVineet Gupta #if (CONFIG_ARC_MMU_VER > 2) 2488362c389SVineet Gupta /* MMUv3, cache ops require paddr seperately */ 2498362c389SVineet Gupta if (!full_page_op) { 2508362c389SVineet Gupta write_aux_reg(aux_tag, paddr); 2518362c389SVineet Gupta paddr += L1_CACHE_BYTES; 2528362c389SVineet Gupta } 2538362c389SVineet Gupta 2548362c389SVineet Gupta write_aux_reg(aux_cmd, vaddr); 2558362c389SVineet Gupta vaddr += L1_CACHE_BYTES; 2568362c389SVineet Gupta #else 2578362c389SVineet Gupta write_aux_reg(aux_cmd, paddr); 2588362c389SVineet Gupta paddr += L1_CACHE_BYTES; 2598362c389SVineet Gupta #endif 2608362c389SVineet Gupta } 2618362c389SVineet Gupta } 2628362c389SVineet Gupta 2638362c389SVineet Gupta #ifdef CONFIG_ARC_HAS_DCACHE 2648362c389SVineet Gupta 2658362c389SVineet Gupta /*************************************************************** 2668362c389SVineet Gupta * Machine specific helpers for Entire D-Cache or Per Line ops 2678362c389SVineet Gupta */ 2688362c389SVineet Gupta 2698362c389SVineet Gupta static inline unsigned int __before_dc_op(const int op) 2708362c389SVineet Gupta { 2718362c389SVineet Gupta unsigned int reg = reg; 2728362c389SVineet Gupta 2738362c389SVineet Gupta if (op == OP_FLUSH_N_INV) { 2748362c389SVineet Gupta /* Dcache provides 2 cmd: FLUSH or INV 2758362c389SVineet Gupta * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE 2768362c389SVineet Gupta * flush-n-inv is achieved by INV cmd but with IM=1 2778362c389SVineet Gupta * So toggle INV sub-mode depending on op request and default 2788362c389SVineet Gupta */ 2798362c389SVineet Gupta reg = read_aux_reg(ARC_REG_DC_CTRL); 2808362c389SVineet Gupta write_aux_reg(ARC_REG_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH) 2818362c389SVineet Gupta ; 2828362c389SVineet Gupta } 2838362c389SVineet Gupta 2848362c389SVineet Gupta return reg; 2858362c389SVineet Gupta } 2868362c389SVineet Gupta 2878362c389SVineet Gupta static inline void __after_dc_op(const int op, unsigned int reg) 2888362c389SVineet Gupta { 2898362c389SVineet Gupta if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 2908362c389SVineet Gupta while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 2918362c389SVineet Gupta 2928362c389SVineet Gupta /* Switch back to default Invalidate mode */ 2938362c389SVineet Gupta if (op == OP_FLUSH_N_INV) 2948362c389SVineet Gupta write_aux_reg(ARC_REG_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); 2958362c389SVineet Gupta } 2968362c389SVineet Gupta 2978362c389SVineet Gupta /* 2988362c389SVineet Gupta * Operation on Entire D-Cache 2998362c389SVineet Gupta * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} 3008362c389SVineet Gupta * Note that constant propagation ensures all the checks are gone 3018362c389SVineet Gupta * in generated code 3028362c389SVineet Gupta */ 3038362c389SVineet Gupta static inline void __dc_entire_op(const int cacheop) 3048362c389SVineet Gupta { 3058362c389SVineet Gupta unsigned int ctrl_reg; 3068362c389SVineet Gupta int aux; 3078362c389SVineet Gupta 3088362c389SVineet Gupta ctrl_reg = __before_dc_op(cacheop); 3098362c389SVineet Gupta 3108362c389SVineet Gupta if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 3118362c389SVineet Gupta aux = ARC_REG_DC_IVDC; 3128362c389SVineet Gupta else 3138362c389SVineet Gupta aux = ARC_REG_DC_FLSH; 3148362c389SVineet Gupta 3158362c389SVineet Gupta write_aux_reg(aux, 0x1); 3168362c389SVineet Gupta 3178362c389SVineet Gupta __after_dc_op(cacheop, ctrl_reg); 3188362c389SVineet Gupta } 3198362c389SVineet Gupta 3208362c389SVineet Gupta /* For kernel mappings cache operation: index is same as paddr */ 3218362c389SVineet Gupta #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) 3228362c389SVineet Gupta 3238362c389SVineet Gupta /* 3248362c389SVineet Gupta * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback) 3258362c389SVineet Gupta */ 3268362c389SVineet Gupta static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, 3278362c389SVineet Gupta unsigned long sz, const int cacheop) 3288362c389SVineet Gupta { 3298362c389SVineet Gupta unsigned long flags; 3308362c389SVineet Gupta unsigned int ctrl_reg; 3318362c389SVineet Gupta 3328362c389SVineet Gupta local_irq_save(flags); 3338362c389SVineet Gupta 3348362c389SVineet Gupta ctrl_reg = __before_dc_op(cacheop); 3358362c389SVineet Gupta 3368362c389SVineet Gupta __cache_line_loop(paddr, vaddr, sz, cacheop); 3378362c389SVineet Gupta 3388362c389SVineet Gupta __after_dc_op(cacheop, ctrl_reg); 3398362c389SVineet Gupta 3408362c389SVineet Gupta local_irq_restore(flags); 3418362c389SVineet Gupta } 3428362c389SVineet Gupta 3438362c389SVineet Gupta #else 3448362c389SVineet Gupta 3458362c389SVineet Gupta #define __dc_entire_op(cacheop) 3468362c389SVineet Gupta #define __dc_line_op(paddr, vaddr, sz, cacheop) 3478362c389SVineet Gupta #define __dc_line_op_k(paddr, sz, cacheop) 3488362c389SVineet Gupta 3498362c389SVineet Gupta #endif /* CONFIG_ARC_HAS_DCACHE */ 3508362c389SVineet Gupta 3518362c389SVineet Gupta 3528362c389SVineet Gupta #ifdef CONFIG_ARC_HAS_ICACHE 3538362c389SVineet Gupta 3548362c389SVineet Gupta /* 3558362c389SVineet Gupta * I-Cache Aliasing in ARC700 VIPT caches 3568362c389SVineet Gupta * 3578362c389SVineet Gupta * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. 3588362c389SVineet Gupta * The orig Cache Management Module "CDU" only required paddr to invalidate a 3598362c389SVineet Gupta * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. 3608362c389SVineet Gupta * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching 3618362c389SVineet Gupta * the exact same line. 3628362c389SVineet Gupta * 3638362c389SVineet Gupta * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, 3648362c389SVineet Gupta * paddr alone could not be used to correctly index the cache. 3658362c389SVineet Gupta * 3668362c389SVineet Gupta * ------------------ 3678362c389SVineet Gupta * MMU v1/v2 (Fixed Page Size 8k) 3688362c389SVineet Gupta * ------------------ 3698362c389SVineet Gupta * The solution was to provide CDU with these additonal vaddr bits. These 3708362c389SVineet Gupta * would be bits [x:13], x would depend on cache-geometry, 13 comes from 3718362c389SVineet Gupta * standard page size of 8k. 3728362c389SVineet Gupta * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits 3738362c389SVineet Gupta * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the 3748362c389SVineet Gupta * orig 5 bits of paddr were anyways ignored by CDU line ops, as they 3758362c389SVineet Gupta * represent the offset within cache-line. The adv of using this "clumsy" 3768362c389SVineet Gupta * interface for additional info was no new reg was needed in CDU programming 3778362c389SVineet Gupta * model. 3788362c389SVineet Gupta * 3798362c389SVineet Gupta * 17:13 represented the max num of bits passable, actual bits needed were 3808362c389SVineet Gupta * fewer, based on the num-of-aliases possible. 3818362c389SVineet Gupta * -for 2 alias possibility, only bit 13 needed (32K cache) 3828362c389SVineet Gupta * -for 4 alias possibility, bits 14:13 needed (64K cache) 3838362c389SVineet Gupta * 3848362c389SVineet Gupta * ------------------ 3858362c389SVineet Gupta * MMU v3 3868362c389SVineet Gupta * ------------------ 3878362c389SVineet Gupta * This ver of MMU supports variable page sizes (1k-16k): although Linux will 3888362c389SVineet Gupta * only support 8k (default), 16k and 4k. 3898362c389SVineet Gupta * However from hardware perspective, smaller page sizes aggrevate aliasing 3908362c389SVineet Gupta * meaning more vaddr bits needed to disambiguate the cache-line-op ; 3918362c389SVineet Gupta * the existing scheme of piggybacking won't work for certain configurations. 3928362c389SVineet Gupta * Two new registers IC_PTAG and DC_PTAG inttoduced. 3938362c389SVineet Gupta * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs 3948362c389SVineet Gupta */ 3958362c389SVineet Gupta 3968362c389SVineet Gupta /*********************************************************** 3978362c389SVineet Gupta * Machine specific helper for per line I-Cache invalidate. 3988362c389SVineet Gupta */ 3998362c389SVineet Gupta 4008362c389SVineet Gupta static inline void __ic_entire_inv(void) 4018362c389SVineet Gupta { 4028362c389SVineet Gupta write_aux_reg(ARC_REG_IC_IVIC, 1); 4038362c389SVineet Gupta read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ 4048362c389SVineet Gupta } 4058362c389SVineet Gupta 4068362c389SVineet Gupta static inline void 4078362c389SVineet Gupta __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, 4088362c389SVineet Gupta unsigned long sz) 4098362c389SVineet Gupta { 4108362c389SVineet Gupta unsigned long flags; 4118362c389SVineet Gupta 4128362c389SVineet Gupta local_irq_save(flags); 4138362c389SVineet Gupta __cache_line_loop(paddr, vaddr, sz, OP_INV_IC); 4148362c389SVineet Gupta local_irq_restore(flags); 4158362c389SVineet Gupta } 4168362c389SVineet Gupta 4178362c389SVineet Gupta #ifndef CONFIG_SMP 4188362c389SVineet Gupta 4198362c389SVineet Gupta #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) 4208362c389SVineet Gupta 4218362c389SVineet Gupta #else 4228362c389SVineet Gupta 4238362c389SVineet Gupta struct ic_inv_args { 4248362c389SVineet Gupta unsigned long paddr, vaddr; 4258362c389SVineet Gupta int sz; 4268362c389SVineet Gupta }; 4278362c389SVineet Gupta 4288362c389SVineet Gupta static void __ic_line_inv_vaddr_helper(void *info) 4298362c389SVineet Gupta { 4308362c389SVineet Gupta struct ic_inv_args *ic_inv = info; 4318362c389SVineet Gupta 4328362c389SVineet Gupta __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); 4338362c389SVineet Gupta } 4348362c389SVineet Gupta 4358362c389SVineet Gupta static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, 4368362c389SVineet Gupta unsigned long sz) 4378362c389SVineet Gupta { 4388362c389SVineet Gupta struct ic_inv_args ic_inv = { 4398362c389SVineet Gupta .paddr = paddr, 4408362c389SVineet Gupta .vaddr = vaddr, 4418362c389SVineet Gupta .sz = sz 4428362c389SVineet Gupta }; 4438362c389SVineet Gupta 4448362c389SVineet Gupta on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); 4458362c389SVineet Gupta } 4468362c389SVineet Gupta 4478362c389SVineet Gupta #endif /* CONFIG_SMP */ 4488362c389SVineet Gupta 4498362c389SVineet Gupta #else /* !CONFIG_ARC_HAS_ICACHE */ 4508362c389SVineet Gupta 4518362c389SVineet Gupta #define __ic_entire_inv() 4528362c389SVineet Gupta #define __ic_line_inv_vaddr(pstart, vstart, sz) 4538362c389SVineet Gupta 4548362c389SVineet Gupta #endif /* CONFIG_ARC_HAS_ICACHE */ 4558362c389SVineet Gupta 4568362c389SVineet Gupta 4578362c389SVineet Gupta /*********************************************************** 4588362c389SVineet Gupta * Exported APIs 4598362c389SVineet Gupta */ 4608362c389SVineet Gupta 4618362c389SVineet Gupta /* 4628362c389SVineet Gupta * Handle cache congruency of kernel and userspace mappings of page when kernel 4638362c389SVineet Gupta * writes-to/reads-from 4648362c389SVineet Gupta * 4658362c389SVineet Gupta * The idea is to defer flushing of kernel mapping after a WRITE, possible if: 4668362c389SVineet Gupta * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent 4678362c389SVineet Gupta * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) 4688362c389SVineet Gupta * -In SMP, if hardware caches are coherent 4698362c389SVineet Gupta * 4708362c389SVineet Gupta * There's a corollary case, where kernel READs from a userspace mapped page. 4718362c389SVineet Gupta * If the U-mapping is not congruent to to K-mapping, former needs flushing. 4728362c389SVineet Gupta */ 4738362c389SVineet Gupta void flush_dcache_page(struct page *page) 4748362c389SVineet Gupta { 4758362c389SVineet Gupta struct address_space *mapping; 4768362c389SVineet Gupta 4778362c389SVineet Gupta if (!cache_is_vipt_aliasing()) { 4788362c389SVineet Gupta clear_bit(PG_dc_clean, &page->flags); 4798362c389SVineet Gupta return; 4808362c389SVineet Gupta } 4818362c389SVineet Gupta 4828362c389SVineet Gupta /* don't handle anon pages here */ 4838362c389SVineet Gupta mapping = page_mapping(page); 4848362c389SVineet Gupta if (!mapping) 4858362c389SVineet Gupta return; 4868362c389SVineet Gupta 4878362c389SVineet Gupta /* 4888362c389SVineet Gupta * pagecache page, file not yet mapped to userspace 4898362c389SVineet Gupta * Make a note that K-mapping is dirty 4908362c389SVineet Gupta */ 4918362c389SVineet Gupta if (!mapping_mapped(mapping)) { 4928362c389SVineet Gupta clear_bit(PG_dc_clean, &page->flags); 4938362c389SVineet Gupta } else if (page_mapped(page)) { 4948362c389SVineet Gupta 4958362c389SVineet Gupta /* kernel reading from page with U-mapping */ 4968362c389SVineet Gupta unsigned long paddr = (unsigned long)page_address(page); 4978362c389SVineet Gupta unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; 4988362c389SVineet Gupta 4998362c389SVineet Gupta if (addr_not_cache_congruent(paddr, vaddr)) 5008362c389SVineet Gupta __flush_dcache_page(paddr, vaddr); 5018362c389SVineet Gupta } 5028362c389SVineet Gupta } 5038362c389SVineet Gupta EXPORT_SYMBOL(flush_dcache_page); 5048362c389SVineet Gupta 5058362c389SVineet Gupta 5068362c389SVineet Gupta void dma_cache_wback_inv(unsigned long start, unsigned long sz) 5078362c389SVineet Gupta { 5088362c389SVineet Gupta __dc_line_op_k(start, sz, OP_FLUSH_N_INV); 5098362c389SVineet Gupta } 5108362c389SVineet Gupta EXPORT_SYMBOL(dma_cache_wback_inv); 5118362c389SVineet Gupta 5128362c389SVineet Gupta void dma_cache_inv(unsigned long start, unsigned long sz) 5138362c389SVineet Gupta { 5148362c389SVineet Gupta __dc_line_op_k(start, sz, OP_INV); 5158362c389SVineet Gupta } 5168362c389SVineet Gupta EXPORT_SYMBOL(dma_cache_inv); 5178362c389SVineet Gupta 5188362c389SVineet Gupta void dma_cache_wback(unsigned long start, unsigned long sz) 5198362c389SVineet Gupta { 5208362c389SVineet Gupta __dc_line_op_k(start, sz, OP_FLUSH); 5218362c389SVineet Gupta } 5228362c389SVineet Gupta EXPORT_SYMBOL(dma_cache_wback); 5238362c389SVineet Gupta 5248362c389SVineet Gupta /* 5258362c389SVineet Gupta * This is API for making I/D Caches consistent when modifying 5268362c389SVineet Gupta * kernel code (loadable modules, kprobes, kgdb...) 5278362c389SVineet Gupta * This is called on insmod, with kernel virtual address for CODE of 5288362c389SVineet Gupta * the module. ARC cache maintenance ops require PHY address thus we 5298362c389SVineet Gupta * need to convert vmalloc addr to PHY addr 5308362c389SVineet Gupta */ 5318362c389SVineet Gupta void flush_icache_range(unsigned long kstart, unsigned long kend) 5328362c389SVineet Gupta { 5338362c389SVineet Gupta unsigned int tot_sz; 5348362c389SVineet Gupta 5358362c389SVineet Gupta WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); 5368362c389SVineet Gupta 5378362c389SVineet Gupta /* Shortcut for bigger flush ranges. 5388362c389SVineet Gupta * Here we don't care if this was kernel virtual or phy addr 5398362c389SVineet Gupta */ 5408362c389SVineet Gupta tot_sz = kend - kstart; 5418362c389SVineet Gupta if (tot_sz > PAGE_SIZE) { 5428362c389SVineet Gupta flush_cache_all(); 5438362c389SVineet Gupta return; 5448362c389SVineet Gupta } 5458362c389SVineet Gupta 5468362c389SVineet Gupta /* Case: Kernel Phy addr (0x8000_0000 onwards) */ 5478362c389SVineet Gupta if (likely(kstart > PAGE_OFFSET)) { 5488362c389SVineet Gupta /* 5498362c389SVineet Gupta * The 2nd arg despite being paddr will be used to index icache 5508362c389SVineet Gupta * This is OK since no alternate virtual mappings will exist 5518362c389SVineet Gupta * given the callers for this case: kprobe/kgdb in built-in 5528362c389SVineet Gupta * kernel code only. 5538362c389SVineet Gupta */ 5548362c389SVineet Gupta __sync_icache_dcache(kstart, kstart, kend - kstart); 5558362c389SVineet Gupta return; 5568362c389SVineet Gupta } 5578362c389SVineet Gupta 5588362c389SVineet Gupta /* 5598362c389SVineet Gupta * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) 5608362c389SVineet Gupta * (1) ARC Cache Maintenance ops only take Phy addr, hence special 5618362c389SVineet Gupta * handling of kernel vaddr. 5628362c389SVineet Gupta * 5638362c389SVineet Gupta * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), 5648362c389SVineet Gupta * it still needs to handle a 2 page scenario, where the range 5658362c389SVineet Gupta * straddles across 2 virtual pages and hence need for loop 5668362c389SVineet Gupta */ 5678362c389SVineet Gupta while (tot_sz > 0) { 5688362c389SVineet Gupta unsigned int off, sz; 5698362c389SVineet Gupta unsigned long phy, pfn; 5708362c389SVineet Gupta 5718362c389SVineet Gupta off = kstart % PAGE_SIZE; 5728362c389SVineet Gupta pfn = vmalloc_to_pfn((void *)kstart); 5738362c389SVineet Gupta phy = (pfn << PAGE_SHIFT) + off; 5748362c389SVineet Gupta sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); 5758362c389SVineet Gupta __sync_icache_dcache(phy, kstart, sz); 5768362c389SVineet Gupta kstart += sz; 5778362c389SVineet Gupta tot_sz -= sz; 5788362c389SVineet Gupta } 5798362c389SVineet Gupta } 5808362c389SVineet Gupta EXPORT_SYMBOL(flush_icache_range); 5818362c389SVineet Gupta 5828362c389SVineet Gupta /* 5838362c389SVineet Gupta * General purpose helper to make I and D cache lines consistent. 5848362c389SVineet Gupta * @paddr is phy addr of region 5858362c389SVineet Gupta * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) 5868362c389SVineet Gupta * However in one instance, when called by kprobe (for a breakpt in 5878362c389SVineet Gupta * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will 5888362c389SVineet Gupta * use a paddr to index the cache (despite VIPT). This is fine since since a 5898362c389SVineet Gupta * builtin kernel page will not have any virtual mappings. 5908362c389SVineet Gupta * kprobe on loadable module will be kernel vaddr. 5918362c389SVineet Gupta */ 5928362c389SVineet Gupta void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) 5938362c389SVineet Gupta { 5948362c389SVineet Gupta __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); 5958362c389SVineet Gupta __ic_line_inv_vaddr(paddr, vaddr, len); 5968362c389SVineet Gupta } 5978362c389SVineet Gupta 5988362c389SVineet Gupta /* wrapper to compile time eliminate alignment checks in flush loop */ 5998362c389SVineet Gupta void __inv_icache_page(unsigned long paddr, unsigned long vaddr) 6008362c389SVineet Gupta { 6018362c389SVineet Gupta __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); 6028362c389SVineet Gupta } 6038362c389SVineet Gupta 6048362c389SVineet Gupta /* 6058362c389SVineet Gupta * wrapper to clearout kernel or userspace mappings of a page 6068362c389SVineet Gupta * For kernel mappings @vaddr == @paddr 6078362c389SVineet Gupta */ 6088362c389SVineet Gupta void __flush_dcache_page(unsigned long paddr, unsigned long vaddr) 6098362c389SVineet Gupta { 6108362c389SVineet Gupta __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); 6118362c389SVineet Gupta } 6128362c389SVineet Gupta 6138362c389SVineet Gupta noinline void flush_cache_all(void) 6148362c389SVineet Gupta { 6158362c389SVineet Gupta unsigned long flags; 6168362c389SVineet Gupta 6178362c389SVineet Gupta local_irq_save(flags); 6188362c389SVineet Gupta 6198362c389SVineet Gupta __ic_entire_inv(); 6208362c389SVineet Gupta __dc_entire_op(OP_FLUSH_N_INV); 6218362c389SVineet Gupta 6228362c389SVineet Gupta local_irq_restore(flags); 6238362c389SVineet Gupta 6248362c389SVineet Gupta } 6258362c389SVineet Gupta 6268362c389SVineet Gupta #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING 6278362c389SVineet Gupta 6288362c389SVineet Gupta void flush_cache_mm(struct mm_struct *mm) 6298362c389SVineet Gupta { 6308362c389SVineet Gupta flush_cache_all(); 6318362c389SVineet Gupta } 6328362c389SVineet Gupta 6338362c389SVineet Gupta void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, 6348362c389SVineet Gupta unsigned long pfn) 6358362c389SVineet Gupta { 6368362c389SVineet Gupta unsigned int paddr = pfn << PAGE_SHIFT; 6378362c389SVineet Gupta 6388362c389SVineet Gupta u_vaddr &= PAGE_MASK; 6398362c389SVineet Gupta 6408362c389SVineet Gupta __flush_dcache_page(paddr, u_vaddr); 6418362c389SVineet Gupta 6428362c389SVineet Gupta if (vma->vm_flags & VM_EXEC) 6438362c389SVineet Gupta __inv_icache_page(paddr, u_vaddr); 6448362c389SVineet Gupta } 6458362c389SVineet Gupta 6468362c389SVineet Gupta void flush_cache_range(struct vm_area_struct *vma, unsigned long start, 6478362c389SVineet Gupta unsigned long end) 6488362c389SVineet Gupta { 6498362c389SVineet Gupta flush_cache_all(); 6508362c389SVineet Gupta } 6518362c389SVineet Gupta 6528362c389SVineet Gupta void flush_anon_page(struct vm_area_struct *vma, struct page *page, 6538362c389SVineet Gupta unsigned long u_vaddr) 6548362c389SVineet Gupta { 6558362c389SVineet Gupta /* TBD: do we really need to clear the kernel mapping */ 6568362c389SVineet Gupta __flush_dcache_page(page_address(page), u_vaddr); 6578362c389SVineet Gupta __flush_dcache_page(page_address(page), page_address(page)); 6588362c389SVineet Gupta 6598362c389SVineet Gupta } 6608362c389SVineet Gupta 6618362c389SVineet Gupta #endif 6628362c389SVineet Gupta 6638362c389SVineet Gupta void copy_user_highpage(struct page *to, struct page *from, 6648362c389SVineet Gupta unsigned long u_vaddr, struct vm_area_struct *vma) 6658362c389SVineet Gupta { 6668362c389SVineet Gupta unsigned long kfrom = (unsigned long)page_address(from); 6678362c389SVineet Gupta unsigned long kto = (unsigned long)page_address(to); 6688362c389SVineet Gupta int clean_src_k_mappings = 0; 6698362c389SVineet Gupta 6708362c389SVineet Gupta /* 6718362c389SVineet Gupta * If SRC page was already mapped in userspace AND it's U-mapping is 6728362c389SVineet Gupta * not congruent with K-mapping, sync former to physical page so that 6738362c389SVineet Gupta * K-mapping in memcpy below, sees the right data 6748362c389SVineet Gupta * 6758362c389SVineet Gupta * Note that while @u_vaddr refers to DST page's userspace vaddr, it is 6768362c389SVineet Gupta * equally valid for SRC page as well 6778362c389SVineet Gupta */ 6788362c389SVineet Gupta if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { 6798362c389SVineet Gupta __flush_dcache_page(kfrom, u_vaddr); 6808362c389SVineet Gupta clean_src_k_mappings = 1; 6818362c389SVineet Gupta } 6828362c389SVineet Gupta 6838362c389SVineet Gupta copy_page((void *)kto, (void *)kfrom); 6848362c389SVineet Gupta 6858362c389SVineet Gupta /* 6868362c389SVineet Gupta * Mark DST page K-mapping as dirty for a later finalization by 6878362c389SVineet Gupta * update_mmu_cache(). Although the finalization could have been done 6888362c389SVineet Gupta * here as well (given that both vaddr/paddr are available). 6898362c389SVineet Gupta * But update_mmu_cache() already has code to do that for other 6908362c389SVineet Gupta * non copied user pages (e.g. read faults which wire in pagecache page 6918362c389SVineet Gupta * directly). 6928362c389SVineet Gupta */ 6938362c389SVineet Gupta clear_bit(PG_dc_clean, &to->flags); 6948362c389SVineet Gupta 6958362c389SVineet Gupta /* 6968362c389SVineet Gupta * if SRC was already usermapped and non-congruent to kernel mapping 6978362c389SVineet Gupta * sync the kernel mapping back to physical page 6988362c389SVineet Gupta */ 6998362c389SVineet Gupta if (clean_src_k_mappings) { 7008362c389SVineet Gupta __flush_dcache_page(kfrom, kfrom); 7018362c389SVineet Gupta set_bit(PG_dc_clean, &from->flags); 7028362c389SVineet Gupta } else { 7038362c389SVineet Gupta clear_bit(PG_dc_clean, &from->flags); 7048362c389SVineet Gupta } 7058362c389SVineet Gupta } 7068362c389SVineet Gupta 7078362c389SVineet Gupta void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) 7088362c389SVineet Gupta { 7098362c389SVineet Gupta clear_page(to); 7108362c389SVineet Gupta clear_bit(PG_dc_clean, &page->flags); 7118362c389SVineet Gupta } 7128362c389SVineet Gupta 7138362c389SVineet Gupta 7148362c389SVineet Gupta /********************************************************************** 7158362c389SVineet Gupta * Explicit Cache flush request from user space via syscall 7168362c389SVineet Gupta * Needed for JITs which generate code on the fly 7178362c389SVineet Gupta */ 7188362c389SVineet Gupta SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) 7198362c389SVineet Gupta { 7208362c389SVineet Gupta /* TBD: optimize this */ 7218362c389SVineet Gupta flush_cache_all(); 7228362c389SVineet Gupta return 0; 7238362c389SVineet Gupta } 724