1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/seq_file.h> 10 #include <linux/fs.h> 11 #include <linux/delay.h> 12 #include <linux/root_dev.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clocksource.h> 16 #include <linux/console.h> 17 #include <linux/module.h> 18 #include <linux/cpu.h> 19 #include <linux/of_fdt.h> 20 #include <linux/of.h> 21 #include <linux/cache.h> 22 #include <uapi/linux/mount.h> 23 #include <asm/sections.h> 24 #include <asm/arcregs.h> 25 #include <asm/tlb.h> 26 #include <asm/setup.h> 27 #include <asm/page.h> 28 #include <asm/irq.h> 29 #include <asm/unwind.h> 30 #include <asm/mach_desc.h> 31 #include <asm/smp.h> 32 33 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 34 35 unsigned int intr_to_DE_cnt; 36 37 /* Part of U-boot ABI: see head.S */ 38 int __initdata uboot_tag; 39 char __initdata *uboot_arg; 40 41 const struct machine_desc *machine_desc; 42 43 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 44 45 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 46 47 static const struct id_to_str arc_cpu_rel[] = { 48 #ifdef CONFIG_ISA_ARCOMPACT 49 { 0x34, "R4.10"}, 50 { 0x35, "R4.11"}, 51 #else 52 { 0x51, "R2.0" }, 53 { 0x52, "R2.1" }, 54 { 0x53, "R3.0" }, 55 { 0x54, "R3.10a" }, 56 #endif 57 { 0x00, NULL } 58 }; 59 60 static const struct id_to_str arc_cpu_nm[] = { 61 #ifdef CONFIG_ISA_ARCOMPACT 62 { 0x20, "ARC 600" }, 63 { 0x30, "ARC 770" }, /* 750 identified seperately */ 64 #else 65 { 0x40, "ARC EM" }, 66 { 0x50, "ARC HS38" }, 67 { 0x54, "ARC HS48" }, 68 #endif 69 { 0x00, "Unknown" } 70 }; 71 72 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 73 { 74 if (is_isa_arcompact()) { 75 struct bcr_iccm_arcompact iccm; 76 struct bcr_dccm_arcompact dccm; 77 78 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 79 if (iccm.ver) { 80 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ 81 cpu->iccm.base_addr = iccm.base << 16; 82 } 83 84 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 85 if (dccm.ver) { 86 unsigned long base; 87 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ 88 89 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); 90 cpu->dccm.base_addr = base & ~0xF; 91 } 92 } else { 93 struct bcr_iccm_arcv2 iccm; 94 struct bcr_dccm_arcv2 dccm; 95 unsigned long region; 96 97 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 98 if (iccm.ver) { 99 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ 100 if (iccm.sz00 == 0xF && iccm.sz01 > 0) 101 cpu->iccm.sz <<= iccm.sz01; 102 103 region = read_aux_reg(ARC_REG_AUX_ICCM); 104 cpu->iccm.base_addr = region & 0xF0000000; 105 } 106 107 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 108 if (dccm.ver) { 109 cpu->dccm.sz = 256 << dccm.sz0; 110 if (dccm.sz0 == 0xF && dccm.sz1 > 0) 111 cpu->dccm.sz <<= dccm.sz1; 112 113 region = read_aux_reg(ARC_REG_AUX_DCCM); 114 cpu->dccm.base_addr = region & 0xF0000000; 115 } 116 } 117 } 118 119 static void read_arc_build_cfg_regs(void) 120 { 121 struct bcr_timer timer; 122 struct bcr_generic bcr; 123 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 124 const struct id_to_str *tbl; 125 struct bcr_isa_arcv2 isa; 126 127 FIX_PTR(cpu); 128 129 READ_BCR(AUX_IDENTITY, cpu->core); 130 131 for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) { 132 if (cpu->core.family == tbl->id) { 133 cpu->details = tbl->str; 134 break; 135 } 136 } 137 138 for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) { 139 if ((cpu->core.family & 0xF4) == tbl->id) 140 break; 141 } 142 cpu->name = tbl->str; 143 144 READ_BCR(ARC_REG_TIMERS_BCR, timer); 145 cpu->extn.timer0 = timer.t0; 146 cpu->extn.timer1 = timer.t1; 147 cpu->extn.rtc = timer.rtc; 148 149 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 150 151 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 152 153 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ 154 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ 155 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ 156 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; 157 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ 158 cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 : 159 IS_ENABLED(CONFIG_ARC_HAS_SWAPE); 160 161 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); 162 163 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 164 read_decode_ccm_bcr(cpu); 165 166 read_decode_mmu_bcr(); 167 read_decode_cache_bcr(); 168 169 if (is_isa_arcompact()) { 170 struct bcr_fp_arcompact sp, dp; 171 struct bcr_bpu_arcompact bpu; 172 173 READ_BCR(ARC_REG_FP_BCR, sp); 174 READ_BCR(ARC_REG_DPFP_BCR, dp); 175 cpu->extn.fpu_sp = sp.ver ? 1 : 0; 176 cpu->extn.fpu_dp = dp.ver ? 1 : 0; 177 178 READ_BCR(ARC_REG_BPU_BCR, bpu); 179 cpu->bpu.ver = bpu.ver; 180 cpu->bpu.full = bpu.fam ? 1 : 0; 181 if (bpu.ent) { 182 cpu->bpu.num_cache = 256 << (bpu.ent - 1); 183 cpu->bpu.num_pred = 256 << (bpu.ent - 1); 184 } 185 } else { 186 struct bcr_fp_arcv2 spdp; 187 struct bcr_bpu_arcv2 bpu; 188 189 READ_BCR(ARC_REG_FP_V2_BCR, spdp); 190 cpu->extn.fpu_sp = spdp.sp ? 1 : 0; 191 cpu->extn.fpu_dp = spdp.dp ? 1 : 0; 192 193 READ_BCR(ARC_REG_BPU_BCR, bpu); 194 cpu->bpu.ver = bpu.ver; 195 cpu->bpu.full = bpu.ft; 196 cpu->bpu.num_cache = 256 << bpu.bce; 197 cpu->bpu.num_pred = 2048 << bpu.pte; 198 199 if (cpu->core.family >= 0x54) { 200 unsigned int exec_ctrl; 201 202 READ_BCR(AUX_EXEC_CTRL, exec_ctrl); 203 cpu->extn.dual_enb = !(exec_ctrl & 1); 204 205 /* dual issue always present for this core */ 206 cpu->extn.dual = 1; 207 } 208 } 209 210 READ_BCR(ARC_REG_AP_BCR, bcr); 211 cpu->extn.ap = bcr.ver ? 1 : 0; 212 213 READ_BCR(ARC_REG_SMART_BCR, bcr); 214 cpu->extn.smart = bcr.ver ? 1 : 0; 215 216 READ_BCR(ARC_REG_RTT_BCR, bcr); 217 cpu->extn.rtt = bcr.ver ? 1 : 0; 218 219 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; 220 221 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); 222 223 /* some hacks for lack of feature BCR info in old ARC700 cores */ 224 if (is_isa_arcompact()) { 225 if (!isa.ver) /* ISA BCR absent, use Kconfig info */ 226 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); 227 else { 228 /* ARC700_BUILD only has 2 bits of isa info */ 229 struct bcr_generic bcr = *(struct bcr_generic *)&isa; 230 cpu->isa.atomic = bcr.info & 1; 231 } 232 233 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); 234 235 /* there's no direct way to distinguish 750 vs. 770 */ 236 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) 237 cpu->name = "ARC750"; 238 } else { 239 cpu->isa = isa; 240 } 241 } 242 243 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 244 { 245 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 246 struct bcr_identity *core = &cpu->core; 247 int i, n = 0, ua = 0; 248 249 FIX_PTR(cpu); 250 251 n += scnprintf(buf + n, len - n, 252 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", 253 core->family, core->cpu_id, core->chip_id); 254 255 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", 256 cpu_id, cpu->name, cpu->details, 257 is_isa_arcompact() ? "ARCompact" : "ARCv2", 258 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), 259 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); 260 261 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", 262 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), 263 IS_AVAIL1(cpu->extn.timer1, "Timer1 "), 264 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), 265 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); 266 267 #ifdef __ARC_UNALIGNED__ 268 ua = 1; 269 #endif 270 n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s%s", 271 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), 272 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), 273 IS_AVAIL1(cpu->isa.unalign, "unalign "), IS_USED_RUN(ua)); 274 275 if (i) 276 n += scnprintf(buf + n, len - n, "\n\t\t: "); 277 278 if (cpu->extn_mpy.ver) { 279 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ 280 n += scnprintf(buf + n, len - n, "mpy "); 281 } else { 282 int opt = 2; /* stock MPY/MPYH */ 283 284 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 285 opt = cpu->extn_mpy.dsp + 6; 286 287 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); 288 } 289 } 290 291 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 292 IS_AVAIL1(cpu->isa.div_rem, "div_rem "), 293 IS_AVAIL1(cpu->extn.norm, "norm "), 294 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), 295 IS_AVAIL1(cpu->extn.swap, "swap "), 296 IS_AVAIL1(cpu->extn.minmax, "minmax "), 297 IS_AVAIL1(cpu->extn.crc, "crc "), 298 IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE)); 299 300 if (cpu->bpu.ver) 301 n += scnprintf(buf + n, len - n, 302 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d", 303 IS_AVAIL1(cpu->bpu.full, "full"), 304 IS_AVAIL1(!cpu->bpu.full, "partial"), 305 cpu->bpu.num_cache, cpu->bpu.num_pred); 306 307 if (is_isa_arcv2()) { 308 struct bcr_lpb lpb; 309 310 READ_BCR(ARC_REG_LPB_BUILD, lpb); 311 if (lpb.ver) { 312 unsigned int ctl; 313 ctl = read_aux_reg(ARC_REG_LPB_CTRL); 314 315 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", 316 lpb.entries, 317 IS_DISABLED_RUN(!ctl)); 318 } 319 } 320 321 n += scnprintf(buf + n, len - n, "\n"); 322 return buf; 323 } 324 325 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 326 { 327 int n = 0; 328 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 329 330 FIX_PTR(cpu); 331 332 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); 333 334 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) 335 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", 336 IS_AVAIL1(cpu->extn.fpu_sp, "SP "), 337 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); 338 339 if (cpu->extn.debug) 340 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", 341 IS_AVAIL1(cpu->extn.ap, "ActionPoint "), 342 IS_AVAIL1(cpu->extn.smart, "smaRT "), 343 IS_AVAIL1(cpu->extn.rtt, "RTT ")); 344 345 if (cpu->dccm.sz || cpu->iccm.sz) 346 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", 347 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), 348 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 349 350 if (is_isa_arcv2()) { 351 352 /* Error Protection: ECC/Parity */ 353 struct bcr_erp erp; 354 READ_BCR(ARC_REG_ERP_BUILD, erp); 355 356 if (erp.ver) { 357 struct ctl_erp ctl; 358 READ_BCR(ARC_REG_ERP_CTRL, ctl); 359 360 /* inverted bits: 0 means enabled */ 361 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", 362 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), 363 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), 364 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); 365 } 366 } 367 368 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", 369 EF_ARC_OSABI_CURRENT >> 8, 370 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? 371 "no-legacy-syscalls" : "64-bit data any register aligned"); 372 373 return buf; 374 } 375 376 static void arc_chk_core_config(void) 377 { 378 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 379 int saved = 0, present = 0; 380 char *opt_nm = NULL; 381 382 if (!cpu->extn.timer0) 383 panic("Timer0 is not present!\n"); 384 385 if (!cpu->extn.timer1) 386 panic("Timer1 is not present!\n"); 387 388 #ifdef CONFIG_ARC_HAS_DCCM 389 /* 390 * DCCM can be arbit placed in hardware. 391 * Make sure it's placement/sz matches what Linux is built with 392 */ 393 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) 394 panic("Linux built with incorrect DCCM Base address\n"); 395 396 if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) 397 panic("Linux built with incorrect DCCM Size\n"); 398 #endif 399 400 #ifdef CONFIG_ARC_HAS_ICCM 401 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 402 panic("Linux built with incorrect ICCM Size\n"); 403 #endif 404 405 /* 406 * FP hardware/software config sanity 407 * -If hardware present, kernel needs to save/restore FPU state 408 * -If not, it will crash trying to save/restore the non-existant regs 409 */ 410 411 if (is_isa_arcompact()) { 412 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE"; 413 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); 414 415 /* only DPDP checked since SP has no arch visible regs */ 416 present = cpu->extn.fpu_dp; 417 } else { 418 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS"; 419 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS); 420 421 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ 422 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; 423 } 424 425 if (present && !saved) 426 pr_warn("Enable %s for working apps\n", opt_nm); 427 else if (!present && saved) 428 panic("Disable %s, hardware NOT present\n", opt_nm); 429 } 430 431 /* 432 * Initialize and setup the processor core 433 * This is called by all the CPUs thus should not do special case stuff 434 * such as only for boot CPU etc 435 */ 436 437 void setup_processor(void) 438 { 439 char str[512]; 440 int cpu_id = smp_processor_id(); 441 442 read_arc_build_cfg_regs(); 443 arc_init_IRQ(); 444 445 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); 446 447 arc_mmu_init(); 448 arc_cache_init(); 449 450 pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 451 pr_info("%s", arc_platform_smp_cpuinfo()); 452 453 arc_chk_core_config(); 454 } 455 456 static inline int is_kernel(unsigned long addr) 457 { 458 if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) 459 return 1; 460 return 0; 461 } 462 463 void __init setup_arch(char **cmdline_p) 464 { 465 #ifdef CONFIG_ARC_UBOOT_SUPPORT 466 /* make sure that uboot passed pointer to cmdline/dtb is valid */ 467 if (uboot_tag && is_kernel((unsigned long)uboot_arg)) 468 panic("Invalid uboot arg\n"); 469 470 /* See if u-boot passed an external Device Tree blob */ 471 machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */ 472 if (!machine_desc) 473 #endif 474 { 475 /* No, so try the embedded one */ 476 machine_desc = setup_machine_fdt(__dtb_start); 477 if (!machine_desc) 478 panic("Embedded DT invalid\n"); 479 480 /* 481 * If we are here, it is established that @uboot_arg didn't 482 * point to DT blob. Instead if u-boot says it is cmdline, 483 * append to embedded DT cmdline. 484 * setup_machine_fdt() would have populated @boot_command_line 485 */ 486 if (uboot_tag == 1) { 487 /* Ensure a whitespace between the 2 cmdlines */ 488 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); 489 strlcat(boot_command_line, uboot_arg, 490 COMMAND_LINE_SIZE); 491 } 492 } 493 494 /* Save unparsed command line copy for /proc/cmdline */ 495 *cmdline_p = boot_command_line; 496 497 /* To force early parsing of things like mem=xxx */ 498 parse_early_param(); 499 500 /* Platform/board specific: e.g. early console registration */ 501 if (machine_desc->init_early) 502 machine_desc->init_early(); 503 504 smp_init_cpus(); 505 506 setup_processor(); 507 setup_arch_memory(); 508 509 /* copy flat DT out of .init and then unflatten it */ 510 unflatten_and_copy_device_tree(); 511 512 /* Can be issue if someone passes cmd line arg "ro" 513 * But that is unlikely so keeping it as it is 514 */ 515 root_mountflags &= ~MS_RDONLY; 516 517 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 518 conswitchp = &dummy_con; 519 #endif 520 521 arc_unwind_init(); 522 } 523 524 /* 525 * Called from start_kernel() - boot CPU only 526 */ 527 void __init time_init(void) 528 { 529 of_clk_init(NULL); 530 timer_probe(); 531 } 532 533 static int __init customize_machine(void) 534 { 535 if (machine_desc->init_machine) 536 machine_desc->init_machine(); 537 538 return 0; 539 } 540 arch_initcall(customize_machine); 541 542 static int __init init_late_machine(void) 543 { 544 if (machine_desc->init_late) 545 machine_desc->init_late(); 546 547 return 0; 548 } 549 late_initcall(init_late_machine); 550 /* 551 * Get CPU information for use by the procfs. 552 */ 553 554 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) 555 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) 556 557 static int show_cpuinfo(struct seq_file *m, void *v) 558 { 559 char *str; 560 int cpu_id = ptr_to_cpu(v); 561 struct device *cpu_dev = get_cpu_device(cpu_id); 562 struct clk *cpu_clk; 563 unsigned long freq = 0; 564 565 if (!cpu_online(cpu_id)) { 566 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); 567 goto done; 568 } 569 570 str = (char *)__get_free_page(GFP_KERNEL); 571 if (!str) 572 goto done; 573 574 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 575 576 cpu_clk = clk_get(cpu_dev, NULL); 577 if (IS_ERR(cpu_clk)) { 578 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", 579 cpu_id); 580 } else { 581 freq = clk_get_rate(cpu_clk); 582 } 583 if (freq) 584 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", 585 freq / 1000000, (freq / 10000) % 100); 586 587 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", 588 loops_per_jiffy / (500000 / HZ), 589 (loops_per_jiffy / (5000 / HZ)) % 100); 590 591 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 592 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 593 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 594 seq_printf(m, arc_platform_smp_cpuinfo()); 595 596 free_page((unsigned long)str); 597 done: 598 seq_printf(m, "\n"); 599 600 return 0; 601 } 602 603 static void *c_start(struct seq_file *m, loff_t *pos) 604 { 605 /* 606 * Callback returns cpu-id to iterator for show routine, NULL to stop. 607 * However since NULL is also a valid cpu-id (0), we use a round-about 608 * way to pass it w/o having to kmalloc/free a 2 byte string. 609 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. 610 */ 611 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; 612 } 613 614 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 615 { 616 ++*pos; 617 return c_start(m, pos); 618 } 619 620 static void c_stop(struct seq_file *m, void *v) 621 { 622 } 623 624 const struct seq_operations cpuinfo_op = { 625 .start = c_start, 626 .next = c_next, 627 .stop = c_stop, 628 .show = show_cpuinfo 629 }; 630 631 static DEFINE_PER_CPU(struct cpu, cpu_topology); 632 633 static int __init topology_init(void) 634 { 635 int cpu; 636 637 for_each_present_cpu(cpu) 638 register_cpu(&per_cpu(cpu_topology, cpu), cpu); 639 640 return 0; 641 } 642 643 subsys_initcall(topology_init); 644