1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/seq_file.h> 10 #include <linux/fs.h> 11 #include <linux/delay.h> 12 #include <linux/root_dev.h> 13 #include <linux/console.h> 14 #include <linux/module.h> 15 #include <linux/cpu.h> 16 #include <linux/of_fdt.h> 17 #include <linux/of.h> 18 #include <linux/cache.h> 19 #include <asm/sections.h> 20 #include <asm/arcregs.h> 21 #include <asm/tlb.h> 22 #include <asm/setup.h> 23 #include <asm/page.h> 24 #include <asm/irq.h> 25 #include <asm/unwind.h> 26 #include <asm/mach_desc.h> 27 #include <asm/smp.h> 28 29 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 30 31 unsigned int intr_to_DE_cnt; 32 33 /* Part of U-boot ABI: see head.S */ 34 int __initdata uboot_tag; 35 char __initdata *uboot_arg; 36 37 const struct machine_desc *machine_desc; 38 39 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 40 41 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 42 43 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 44 { 45 if (is_isa_arcompact()) { 46 struct bcr_iccm_arcompact iccm; 47 struct bcr_dccm_arcompact dccm; 48 49 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 50 if (iccm.ver) { 51 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ 52 cpu->iccm.base_addr = iccm.base << 16; 53 } 54 55 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 56 if (dccm.ver) { 57 unsigned long base; 58 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ 59 60 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); 61 cpu->dccm.base_addr = base & ~0xF; 62 } 63 } else { 64 struct bcr_iccm_arcv2 iccm; 65 struct bcr_dccm_arcv2 dccm; 66 unsigned long region; 67 68 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 69 if (iccm.ver) { 70 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ 71 if (iccm.sz00 == 0xF && iccm.sz01 > 0) 72 cpu->iccm.sz <<= iccm.sz01; 73 74 region = read_aux_reg(ARC_REG_AUX_ICCM); 75 cpu->iccm.base_addr = region & 0xF0000000; 76 } 77 78 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 79 if (dccm.ver) { 80 cpu->dccm.sz = 256 << dccm.sz0; 81 if (dccm.sz0 == 0xF && dccm.sz1 > 0) 82 cpu->dccm.sz <<= dccm.sz1; 83 84 region = read_aux_reg(ARC_REG_AUX_DCCM); 85 cpu->dccm.base_addr = region & 0xF0000000; 86 } 87 } 88 } 89 90 static void read_arc_build_cfg_regs(void) 91 { 92 struct bcr_timer timer; 93 struct bcr_generic bcr; 94 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 95 FIX_PTR(cpu); 96 97 READ_BCR(AUX_IDENTITY, cpu->core); 98 READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); 99 100 READ_BCR(ARC_REG_TIMERS_BCR, timer); 101 cpu->extn.timer0 = timer.t0; 102 cpu->extn.timer1 = timer.t1; 103 cpu->extn.rtc = timer.rtc; 104 105 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 106 107 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 108 109 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ 110 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ 111 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ 112 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; 113 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ 114 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); 115 116 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 117 read_decode_ccm_bcr(cpu); 118 119 read_decode_mmu_bcr(); 120 read_decode_cache_bcr(); 121 122 if (is_isa_arcompact()) { 123 struct bcr_fp_arcompact sp, dp; 124 struct bcr_bpu_arcompact bpu; 125 126 READ_BCR(ARC_REG_FP_BCR, sp); 127 READ_BCR(ARC_REG_DPFP_BCR, dp); 128 cpu->extn.fpu_sp = sp.ver ? 1 : 0; 129 cpu->extn.fpu_dp = dp.ver ? 1 : 0; 130 131 READ_BCR(ARC_REG_BPU_BCR, bpu); 132 cpu->bpu.ver = bpu.ver; 133 cpu->bpu.full = bpu.fam ? 1 : 0; 134 if (bpu.ent) { 135 cpu->bpu.num_cache = 256 << (bpu.ent - 1); 136 cpu->bpu.num_pred = 256 << (bpu.ent - 1); 137 } 138 } else { 139 struct bcr_fp_arcv2 spdp; 140 struct bcr_bpu_arcv2 bpu; 141 142 READ_BCR(ARC_REG_FP_V2_BCR, spdp); 143 cpu->extn.fpu_sp = spdp.sp ? 1 : 0; 144 cpu->extn.fpu_dp = spdp.dp ? 1 : 0; 145 146 READ_BCR(ARC_REG_BPU_BCR, bpu); 147 cpu->bpu.ver = bpu.ver; 148 cpu->bpu.full = bpu.ft; 149 cpu->bpu.num_cache = 256 << bpu.bce; 150 cpu->bpu.num_pred = 2048 << bpu.pte; 151 } 152 153 READ_BCR(ARC_REG_AP_BCR, bcr); 154 cpu->extn.ap = bcr.ver ? 1 : 0; 155 156 READ_BCR(ARC_REG_SMART_BCR, bcr); 157 cpu->extn.smart = bcr.ver ? 1 : 0; 158 159 READ_BCR(ARC_REG_RTT_BCR, bcr); 160 cpu->extn.rtt = bcr.ver ? 1 : 0; 161 162 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; 163 } 164 165 static const struct cpuinfo_data arc_cpu_tbl[] = { 166 #ifdef CONFIG_ISA_ARCOMPACT 167 { {0x20, "ARC 600" }, 0x2F}, 168 { {0x30, "ARC 700" }, 0x33}, 169 { {0x34, "ARC 700 R4.10"}, 0x34}, 170 { {0x35, "ARC 700 R4.11"}, 0x35}, 171 #else 172 { {0x50, "ARC HS38 R2.0"}, 0x51}, 173 { {0x52, "ARC HS38 R2.1"}, 0x52}, 174 #endif 175 { {0x00, NULL } } 176 }; 177 178 179 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 180 { 181 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 182 struct bcr_identity *core = &cpu->core; 183 const struct cpuinfo_data *tbl; 184 char *isa_nm; 185 int i, be, atomic; 186 int n = 0; 187 188 FIX_PTR(cpu); 189 190 if (is_isa_arcompact()) { 191 isa_nm = "ARCompact"; 192 be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); 193 194 atomic = cpu->isa.atomic1; 195 if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ 196 atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); 197 } else { 198 isa_nm = "ARCv2"; 199 be = cpu->isa.be; 200 atomic = cpu->isa.atomic; 201 } 202 203 n += scnprintf(buf + n, len - n, 204 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", 205 core->family, core->cpu_id, core->chip_id); 206 207 for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { 208 if ((core->family >= tbl->info.id) && 209 (core->family <= tbl->up_range)) { 210 n += scnprintf(buf + n, len - n, 211 "processor [%d]\t: %s (%s ISA) %s\n", 212 cpu_id, tbl->info.str, isa_nm, 213 IS_AVAIL1(be, "[Big-Endian]")); 214 break; 215 } 216 } 217 218 if (tbl->info.id == 0) 219 n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n"); 220 221 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", 222 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), 223 IS_AVAIL1(cpu->extn.timer1, "Timer1 "), 224 IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", 225 CONFIG_ARC_HAS_RTC)); 226 227 n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", 228 IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC), 229 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), 230 IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); 231 232 if (i) 233 n += scnprintf(buf + n, len - n, "\n\t\t: "); 234 235 if (cpu->extn_mpy.ver) { 236 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ 237 n += scnprintf(buf + n, len - n, "mpy "); 238 } else { 239 int opt = 2; /* stock MPY/MPYH */ 240 241 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 242 opt = cpu->extn_mpy.dsp + 6; 243 244 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); 245 } 246 } 247 248 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 249 IS_AVAIL1(cpu->isa.div_rem, "div_rem "), 250 IS_AVAIL1(cpu->extn.norm, "norm "), 251 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), 252 IS_AVAIL1(cpu->extn.swap, "swap "), 253 IS_AVAIL1(cpu->extn.minmax, "minmax "), 254 IS_AVAIL1(cpu->extn.crc, "crc "), 255 IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); 256 257 if (cpu->bpu.ver) 258 n += scnprintf(buf + n, len - n, 259 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", 260 IS_AVAIL1(cpu->bpu.full, "full"), 261 IS_AVAIL1(!cpu->bpu.full, "partial"), 262 cpu->bpu.num_cache, cpu->bpu.num_pred); 263 264 return buf; 265 } 266 267 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 268 { 269 int n = 0; 270 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 271 272 FIX_PTR(cpu); 273 274 n += scnprintf(buf + n, len - n, 275 "Vector Table\t: %#x\nUncached Base\t: %#lx\n", 276 cpu->vec_base, perip_base); 277 278 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) 279 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", 280 IS_AVAIL1(cpu->extn.fpu_sp, "SP "), 281 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); 282 283 if (cpu->extn.debug) 284 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", 285 IS_AVAIL1(cpu->extn.ap, "ActionPoint "), 286 IS_AVAIL1(cpu->extn.smart, "smaRT "), 287 IS_AVAIL1(cpu->extn.rtt, "RTT ")); 288 289 if (cpu->dccm.sz || cpu->iccm.sz) 290 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", 291 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), 292 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 293 294 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", 295 EF_ARC_OSABI_CURRENT >> 8, 296 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? 297 "no-legacy-syscalls" : "64-bit data any register aligned"); 298 299 return buf; 300 } 301 302 static void arc_chk_core_config(void) 303 { 304 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 305 int fpu_enabled; 306 307 if (!cpu->extn.timer0) 308 panic("Timer0 is not present!\n"); 309 310 if (!cpu->extn.timer1) 311 panic("Timer1 is not present!\n"); 312 313 #ifdef CONFIG_ARC_HAS_DCCM 314 /* 315 * DCCM can be arbit placed in hardware. 316 * Make sure it's placement/sz matches what Linux is built with 317 */ 318 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) 319 panic("Linux built with incorrect DCCM Base address\n"); 320 321 if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) 322 panic("Linux built with incorrect DCCM Size\n"); 323 #endif 324 325 #ifdef CONFIG_ARC_HAS_ICCM 326 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 327 panic("Linux built with incorrect ICCM Size\n"); 328 #endif 329 330 /* 331 * FP hardware/software config sanity 332 * -If hardware contains DPFP, kernel needs to save/restore FPU state 333 * -If not, it will crash trying to save/restore the non-existant regs 334 * 335 * (only DPDP checked since SP has no arch visible regs) 336 */ 337 fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); 338 339 if (cpu->extn.fpu_dp && !fpu_enabled) 340 pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n"); 341 else if (!cpu->extn.fpu_dp && fpu_enabled) 342 panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n"); 343 } 344 345 /* 346 * Initialize and setup the processor core 347 * This is called by all the CPUs thus should not do special case stuff 348 * such as only for boot CPU etc 349 */ 350 351 void setup_processor(void) 352 { 353 char str[512]; 354 int cpu_id = smp_processor_id(); 355 356 read_arc_build_cfg_regs(); 357 arc_init_IRQ(); 358 359 printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); 360 361 arc_mmu_init(); 362 arc_cache_init(); 363 364 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 365 printk(arc_platform_smp_cpuinfo()); 366 367 arc_chk_core_config(); 368 } 369 370 static inline int is_kernel(unsigned long addr) 371 { 372 if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) 373 return 1; 374 return 0; 375 } 376 377 void __init setup_arch(char **cmdline_p) 378 { 379 #ifdef CONFIG_ARC_UBOOT_SUPPORT 380 /* make sure that uboot passed pointer to cmdline/dtb is valid */ 381 if (uboot_tag && is_kernel((unsigned long)uboot_arg)) 382 panic("Invalid uboot arg\n"); 383 384 /* See if u-boot passed an external Device Tree blob */ 385 machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */ 386 if (!machine_desc) 387 #endif 388 { 389 /* No, so try the embedded one */ 390 machine_desc = setup_machine_fdt(__dtb_start); 391 if (!machine_desc) 392 panic("Embedded DT invalid\n"); 393 394 /* 395 * If we are here, it is established that @uboot_arg didn't 396 * point to DT blob. Instead if u-boot says it is cmdline, 397 * append to embedded DT cmdline. 398 * setup_machine_fdt() would have populated @boot_command_line 399 */ 400 if (uboot_tag == 1) { 401 /* Ensure a whitespace between the 2 cmdlines */ 402 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); 403 strlcat(boot_command_line, uboot_arg, 404 COMMAND_LINE_SIZE); 405 } 406 } 407 408 /* Save unparsed command line copy for /proc/cmdline */ 409 *cmdline_p = boot_command_line; 410 411 /* To force early parsing of things like mem=xxx */ 412 parse_early_param(); 413 414 /* Platform/board specific: e.g. early console registration */ 415 if (machine_desc->init_early) 416 machine_desc->init_early(); 417 418 smp_init_cpus(); 419 420 setup_processor(); 421 setup_arch_memory(); 422 423 /* copy flat DT out of .init and then unflatten it */ 424 unflatten_and_copy_device_tree(); 425 426 /* Can be issue if someone passes cmd line arg "ro" 427 * But that is unlikely so keeping it as it is 428 */ 429 root_mountflags &= ~MS_RDONLY; 430 431 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 432 conswitchp = &dummy_con; 433 #endif 434 435 arc_unwind_init(); 436 } 437 438 static int __init customize_machine(void) 439 { 440 if (machine_desc->init_machine) 441 machine_desc->init_machine(); 442 443 return 0; 444 } 445 arch_initcall(customize_machine); 446 447 static int __init init_late_machine(void) 448 { 449 if (machine_desc->init_late) 450 machine_desc->init_late(); 451 452 return 0; 453 } 454 late_initcall(init_late_machine); 455 /* 456 * Get CPU information for use by the procfs. 457 */ 458 459 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) 460 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) 461 462 static int show_cpuinfo(struct seq_file *m, void *v) 463 { 464 char *str; 465 int cpu_id = ptr_to_cpu(v); 466 struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk"); 467 u32 freq = 0; 468 469 if (!cpu_online(cpu_id)) { 470 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); 471 goto done; 472 } 473 474 str = (char *)__get_free_page(GFP_TEMPORARY); 475 if (!str) 476 goto done; 477 478 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 479 480 of_property_read_u32(core_clk, "clock-frequency", &freq); 481 if (freq) 482 seq_printf(m, "CPU speed\t: %u.%02u Mhz\n", 483 freq / 1000000, (freq / 10000) % 100); 484 485 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", 486 loops_per_jiffy / (500000 / HZ), 487 (loops_per_jiffy / (5000 / HZ)) % 100); 488 489 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 490 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 491 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 492 seq_printf(m, arc_platform_smp_cpuinfo()); 493 494 free_page((unsigned long)str); 495 done: 496 seq_printf(m, "\n"); 497 498 return 0; 499 } 500 501 static void *c_start(struct seq_file *m, loff_t *pos) 502 { 503 /* 504 * Callback returns cpu-id to iterator for show routine, NULL to stop. 505 * However since NULL is also a valid cpu-id (0), we use a round-about 506 * way to pass it w/o having to kmalloc/free a 2 byte string. 507 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. 508 */ 509 return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL; 510 } 511 512 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 513 { 514 ++*pos; 515 return c_start(m, pos); 516 } 517 518 static void c_stop(struct seq_file *m, void *v) 519 { 520 } 521 522 const struct seq_operations cpuinfo_op = { 523 .start = c_start, 524 .next = c_next, 525 .stop = c_stop, 526 .show = show_cpuinfo 527 }; 528 529 static DEFINE_PER_CPU(struct cpu, cpu_topology); 530 531 static int __init topology_init(void) 532 { 533 int cpu; 534 535 for_each_present_cpu(cpu) 536 register_cpu(&per_cpu(cpu_topology, cpu), cpu); 537 538 return 0; 539 } 540 541 subsys_initcall(topology_init); 542