1 /* 2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/smp.h> 12 #include <linux/irq.h> 13 #include <linux/spinlock.h> 14 #include <soc/arc/mcip.h> 15 #include <asm/irqflags-arcv2.h> 16 #include <asm/setup.h> 17 18 static DEFINE_RAW_SPINLOCK(mcip_lock); 19 20 #ifdef CONFIG_SMP 21 22 static char smp_cpuinfo_buf[128]; 23 24 static void mcip_setup_per_cpu(int cpu) 25 { 26 smp_ipi_irq_setup(cpu, IPI_IRQ); 27 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); 28 } 29 30 static void mcip_ipi_send(int cpu) 31 { 32 unsigned long flags; 33 int ipi_was_pending; 34 35 /* ARConnect can only send IPI to others */ 36 if (unlikely(cpu == raw_smp_processor_id())) { 37 arc_softirq_trigger(SOFTIRQ_IRQ); 38 return; 39 } 40 41 raw_spin_lock_irqsave(&mcip_lock, flags); 42 43 /* 44 * If receiver already has a pending interrupt, elide sending this one. 45 * Linux cross core calling works well with concurrent IPIs 46 * coalesced into one 47 * see arch/arc/kernel/smp.c: ipi_send_msg_one() 48 */ 49 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); 50 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); 51 if (!ipi_was_pending) 52 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); 53 54 raw_spin_unlock_irqrestore(&mcip_lock, flags); 55 } 56 57 static void mcip_ipi_clear(int irq) 58 { 59 unsigned int cpu, c; 60 unsigned long flags; 61 62 if (unlikely(irq == SOFTIRQ_IRQ)) { 63 arc_softirq_clear(irq); 64 return; 65 } 66 67 raw_spin_lock_irqsave(&mcip_lock, flags); 68 69 /* Who sent the IPI */ 70 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); 71 72 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ 73 74 /* 75 * In rare case, multiple concurrent IPIs sent to same target can 76 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be 77 * "vectored" (multiple bits sets) as opposed to typical single bit 78 */ 79 do { 80 c = __ffs(cpu); /* 0,1,2,3 */ 81 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); 82 cpu &= ~(1U << c); 83 } while (cpu); 84 85 raw_spin_unlock_irqrestore(&mcip_lock, flags); 86 } 87 88 static void mcip_probe_n_setup(void) 89 { 90 struct mcip_bcr mp; 91 92 READ_BCR(ARC_REG_MCIP_BCR, mp); 93 94 sprintf(smp_cpuinfo_buf, 95 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n", 96 mp.ver, mp.num_cores, 97 IS_AVAIL1(mp.ipi, "IPI "), 98 IS_AVAIL1(mp.idu, "IDU "), 99 IS_AVAIL1(mp.llm, "LLM "), 100 IS_AVAIL1(mp.dbg, "DEBUG "), 101 IS_AVAIL1(mp.gfrc, "GFRC")); 102 103 cpuinfo_arc700[0].extn.gfrc = mp.gfrc; 104 105 if (mp.dbg) { 106 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 107 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 108 } 109 } 110 111 struct plat_smp_ops plat_smp_ops = { 112 .info = smp_cpuinfo_buf, 113 .init_early_smp = mcip_probe_n_setup, 114 .init_per_cpu = mcip_setup_per_cpu, 115 .ipi_send = mcip_ipi_send, 116 .ipi_clear = mcip_ipi_clear, 117 }; 118 119 #endif 120 121 /*************************************************************************** 122 * ARCv2 Interrupt Distribution Unit (IDU) 123 * 124 * Connects external "COMMON" IRQs to core intc, providing: 125 * -dynamic routing (IRQ affinity) 126 * -load balancing (Round Robin interrupt distribution) 127 * -1:N distribution 128 * 129 * It physically resides in the MCIP hw block 130 */ 131 132 #include <linux/irqchip.h> 133 #include <linux/of.h> 134 #include <linux/of_irq.h> 135 136 /* 137 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) 138 */ 139 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) 140 { 141 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); 142 } 143 144 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, 145 unsigned int distr) 146 { 147 union { 148 unsigned int word; 149 struct { 150 unsigned int distr:2, pad:2, lvl:1, pad2:27; 151 }; 152 } data; 153 154 data.distr = distr; 155 data.lvl = lvl; 156 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); 157 } 158 159 static void idu_irq_mask(struct irq_data *data) 160 { 161 unsigned long flags; 162 163 raw_spin_lock_irqsave(&mcip_lock, flags); 164 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); 165 raw_spin_unlock_irqrestore(&mcip_lock, flags); 166 } 167 168 static void idu_irq_unmask(struct irq_data *data) 169 { 170 unsigned long flags; 171 172 raw_spin_lock_irqsave(&mcip_lock, flags); 173 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); 174 raw_spin_unlock_irqrestore(&mcip_lock, flags); 175 } 176 177 #ifdef CONFIG_SMP 178 static int 179 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, 180 bool force) 181 { 182 unsigned long flags; 183 cpumask_t online; 184 unsigned int destination_bits; 185 unsigned int distribution_mode; 186 187 /* errout if no online cpu per @cpumask */ 188 if (!cpumask_and(&online, cpumask, cpu_online_mask)) 189 return -EINVAL; 190 191 raw_spin_lock_irqsave(&mcip_lock, flags); 192 193 destination_bits = cpumask_bits(&online)[0]; 194 idu_set_dest(data->hwirq, destination_bits); 195 196 if (ffs(destination_bits) == fls(destination_bits)) 197 distribution_mode = IDU_M_DISTRI_DEST; 198 else 199 distribution_mode = IDU_M_DISTRI_RR; 200 201 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode); 202 203 raw_spin_unlock_irqrestore(&mcip_lock, flags); 204 205 return IRQ_SET_MASK_OK; 206 } 207 #endif 208 209 static struct irq_chip idu_irq_chip = { 210 .name = "MCIP IDU Intc", 211 .irq_mask = idu_irq_mask, 212 .irq_unmask = idu_irq_unmask, 213 #ifdef CONFIG_SMP 214 .irq_set_affinity = idu_irq_set_affinity, 215 #endif 216 217 }; 218 219 static irq_hw_number_t idu_first_hwirq; 220 221 static void idu_cascade_isr(struct irq_desc *desc) 222 { 223 struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); 224 irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); 225 irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq; 226 227 generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); 228 } 229 230 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) 231 { 232 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); 233 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 234 235 return 0; 236 } 237 238 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, 239 const u32 *intspec, unsigned int intsize, 240 irq_hw_number_t *out_hwirq, unsigned int *out_type) 241 { 242 irq_hw_number_t hwirq = *out_hwirq = intspec[0]; 243 int distri = intspec[1]; 244 unsigned long flags; 245 246 *out_type = IRQ_TYPE_NONE; 247 248 /* XXX: validate distribution scheme again online cpu mask */ 249 if (distri == 0) { 250 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ 251 raw_spin_lock_irqsave(&mcip_lock, flags); 252 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); 253 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 254 raw_spin_unlock_irqrestore(&mcip_lock, flags); 255 } else { 256 /* 257 * DEST based distribution for Level Triggered intr can only 258 * have 1 CPU, so generalize it to always contain 1 cpu 259 */ 260 int cpu = ffs(distri); 261 262 if (cpu != fls(distri)) 263 pr_warn("IDU irq %lx distri mode set to cpu %x\n", 264 hwirq, cpu); 265 266 raw_spin_lock_irqsave(&mcip_lock, flags); 267 idu_set_dest(hwirq, cpu); 268 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); 269 raw_spin_unlock_irqrestore(&mcip_lock, flags); 270 } 271 272 return 0; 273 } 274 275 static const struct irq_domain_ops idu_irq_ops = { 276 .xlate = idu_irq_xlate, 277 .map = idu_irq_map, 278 }; 279 280 /* 281 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) 282 * [24, 23+C]: If C > 0 then "C" common IRQs 283 * [24+C, N]: Not statically assigned, private-per-core 284 */ 285 286 287 static int __init 288 idu_of_init(struct device_node *intc, struct device_node *parent) 289 { 290 struct irq_domain *domain; 291 /* Read IDU BCR to confirm nr_irqs */ 292 int nr_irqs = of_irq_count(intc); 293 int i, virq; 294 struct mcip_bcr mp; 295 296 READ_BCR(ARC_REG_MCIP_BCR, mp); 297 298 if (!mp.idu) 299 panic("IDU not detected, but DeviceTree using it"); 300 301 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); 302 303 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); 304 305 /* Parent interrupts (core-intc) are already mapped */ 306 307 for (i = 0; i < nr_irqs; i++) { 308 /* 309 * Return parent uplink IRQs (towards core intc) 24,25,..... 310 * this step has been done before already 311 * however we need it to get the parent virq and set IDU handler 312 * as first level isr 313 */ 314 virq = irq_of_parse_and_map(intc, i); 315 if (!i) 316 idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); 317 318 irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain); 319 } 320 321 __mcip_cmd(CMD_IDU_ENABLE, 0); 322 323 return 0; 324 } 325 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); 326