1 /* 2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/smp.h> 12 #include <linux/irq.h> 13 #include <linux/spinlock.h> 14 #include <asm/mcip.h> 15 #include <asm/setup.h> 16 17 static char smp_cpuinfo_buf[128]; 18 static int idu_detected; 19 20 static DEFINE_RAW_SPINLOCK(mcip_lock); 21 22 static void mcip_setup_per_cpu(int cpu) 23 { 24 smp_ipi_irq_setup(cpu, IPI_IRQ); 25 } 26 27 static void mcip_ipi_send(int cpu) 28 { 29 unsigned long flags; 30 int ipi_was_pending; 31 32 /* 33 * NOTE: We must spin here if the other cpu hasn't yet 34 * serviced a previous message. This can burn lots 35 * of time, but we MUST follows this protocol or 36 * ipi messages can be lost!!! 37 * Also, we must release the lock in this loop because 38 * the other side may get to this same loop and not 39 * be able to ack -- thus causing deadlock. 40 */ 41 42 do { 43 raw_spin_lock_irqsave(&mcip_lock, flags); 44 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); 45 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); 46 if (ipi_was_pending == 0) 47 break; /* break out but keep lock */ 48 raw_spin_unlock_irqrestore(&mcip_lock, flags); 49 } while (1); 50 51 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); 52 raw_spin_unlock_irqrestore(&mcip_lock, flags); 53 54 #ifdef CONFIG_ARC_IPI_DBG 55 if (ipi_was_pending) 56 pr_info("IPI ACK delayed from cpu %d\n", cpu); 57 #endif 58 } 59 60 static void mcip_ipi_clear(int irq) 61 { 62 unsigned int cpu, c; 63 unsigned long flags; 64 unsigned int __maybe_unused copy; 65 66 raw_spin_lock_irqsave(&mcip_lock, flags); 67 68 /* Who sent the IPI */ 69 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); 70 71 copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ 72 73 /* 74 * In rare case, multiple concurrent IPIs sent to same target can 75 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be 76 * "vectored" (multiple bits sets) as opposed to typical single bit 77 */ 78 do { 79 c = __ffs(cpu); /* 0,1,2,3 */ 80 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); 81 cpu &= ~(1U << c); 82 } while (cpu); 83 84 raw_spin_unlock_irqrestore(&mcip_lock, flags); 85 86 #ifdef CONFIG_ARC_IPI_DBG 87 if (c != __ffs(copy)) 88 pr_info("IPIs from %x coalesced to %x\n", 89 copy, raw_smp_processor_id()); 90 #endif 91 } 92 93 static void mcip_probe_n_setup(void) 94 { 95 struct mcip_bcr { 96 #ifdef CONFIG_CPU_BIG_ENDIAN 97 unsigned int pad3:8, 98 idu:1, llm:1, num_cores:6, 99 iocoh:1, grtc:1, dbg:1, pad2:1, 100 msg:1, sem:1, ipi:1, pad:1, 101 ver:8; 102 #else 103 unsigned int ver:8, 104 pad:1, ipi:1, sem:1, msg:1, 105 pad2:1, dbg:1, grtc:1, iocoh:1, 106 num_cores:6, llm:1, idu:1, 107 pad3:8; 108 #endif 109 } mp; 110 111 READ_BCR(ARC_REG_MCIP_BCR, mp); 112 113 sprintf(smp_cpuinfo_buf, 114 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", 115 mp.ver, mp.num_cores, 116 IS_AVAIL1(mp.ipi, "IPI "), 117 IS_AVAIL1(mp.idu, "IDU "), 118 IS_AVAIL1(mp.dbg, "DEBUG "), 119 IS_AVAIL1(mp.grtc, "GRTC")); 120 121 idu_detected = mp.idu; 122 123 if (mp.dbg) { 124 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 125 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 126 } 127 128 if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) 129 panic("kernel trying to use non-existent GRTC\n"); 130 } 131 132 struct plat_smp_ops plat_smp_ops = { 133 .info = smp_cpuinfo_buf, 134 .init_early_smp = mcip_probe_n_setup, 135 .init_per_cpu = mcip_setup_per_cpu, 136 .ipi_send = mcip_ipi_send, 137 .ipi_clear = mcip_ipi_clear, 138 }; 139 140 /*************************************************************************** 141 * ARCv2 Interrupt Distribution Unit (IDU) 142 * 143 * Connects external "COMMON" IRQs to core intc, providing: 144 * -dynamic routing (IRQ affinity) 145 * -load balancing (Round Robin interrupt distribution) 146 * -1:N distribution 147 * 148 * It physically resides in the MCIP hw block 149 */ 150 151 #include <linux/irqchip.h> 152 #include <linux/of.h> 153 #include <linux/of_irq.h> 154 155 /* 156 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) 157 */ 158 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) 159 { 160 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); 161 } 162 163 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, 164 unsigned int distr) 165 { 166 union { 167 unsigned int word; 168 struct { 169 unsigned int distr:2, pad:2, lvl:1, pad2:27; 170 }; 171 } data; 172 173 data.distr = distr; 174 data.lvl = lvl; 175 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); 176 } 177 178 static void idu_irq_mask(struct irq_data *data) 179 { 180 unsigned long flags; 181 182 raw_spin_lock_irqsave(&mcip_lock, flags); 183 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); 184 raw_spin_unlock_irqrestore(&mcip_lock, flags); 185 } 186 187 static void idu_irq_unmask(struct irq_data *data) 188 { 189 unsigned long flags; 190 191 raw_spin_lock_irqsave(&mcip_lock, flags); 192 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); 193 raw_spin_unlock_irqrestore(&mcip_lock, flags); 194 } 195 196 #ifdef CONFIG_SMP 197 static int 198 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, 199 bool force) 200 { 201 unsigned long flags; 202 cpumask_t online; 203 204 /* errout if no online cpu per @cpumask */ 205 if (!cpumask_and(&online, cpumask, cpu_online_mask)) 206 return -EINVAL; 207 208 raw_spin_lock_irqsave(&mcip_lock, flags); 209 210 idu_set_dest(data->hwirq, cpumask_bits(&online)[0]); 211 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 212 213 raw_spin_unlock_irqrestore(&mcip_lock, flags); 214 215 return IRQ_SET_MASK_OK; 216 } 217 #endif 218 219 static struct irq_chip idu_irq_chip = { 220 .name = "MCIP IDU Intc", 221 .irq_mask = idu_irq_mask, 222 .irq_unmask = idu_irq_unmask, 223 #ifdef CONFIG_SMP 224 .irq_set_affinity = idu_irq_set_affinity, 225 #endif 226 227 }; 228 229 static int idu_first_irq; 230 231 static void idu_cascade_isr(struct irq_desc *desc) 232 { 233 struct irq_domain *domain = irq_desc_get_handler_data(desc); 234 unsigned int core_irq = irq_desc_get_irq(desc); 235 unsigned int idu_irq; 236 237 idu_irq = core_irq - idu_first_irq; 238 generic_handle_irq(irq_find_mapping(domain, idu_irq)); 239 } 240 241 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) 242 { 243 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); 244 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 245 246 return 0; 247 } 248 249 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, 250 const u32 *intspec, unsigned int intsize, 251 irq_hw_number_t *out_hwirq, unsigned int *out_type) 252 { 253 irq_hw_number_t hwirq = *out_hwirq = intspec[0]; 254 int distri = intspec[1]; 255 unsigned long flags; 256 257 *out_type = IRQ_TYPE_NONE; 258 259 /* XXX: validate distribution scheme again online cpu mask */ 260 if (distri == 0) { 261 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ 262 raw_spin_lock_irqsave(&mcip_lock, flags); 263 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); 264 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 265 raw_spin_unlock_irqrestore(&mcip_lock, flags); 266 } else { 267 /* 268 * DEST based distribution for Level Triggered intr can only 269 * have 1 CPU, so generalize it to always contain 1 cpu 270 */ 271 int cpu = ffs(distri); 272 273 if (cpu != fls(distri)) 274 pr_warn("IDU irq %lx distri mode set to cpu %x\n", 275 hwirq, cpu); 276 277 raw_spin_lock_irqsave(&mcip_lock, flags); 278 idu_set_dest(hwirq, cpu); 279 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); 280 raw_spin_unlock_irqrestore(&mcip_lock, flags); 281 } 282 283 return 0; 284 } 285 286 static const struct irq_domain_ops idu_irq_ops = { 287 .xlate = idu_irq_xlate, 288 .map = idu_irq_map, 289 }; 290 291 /* 292 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) 293 * [24, 23+C]: If C > 0 then "C" common IRQs 294 * [24+C, N]: Not statically assigned, private-per-core 295 */ 296 297 298 static int __init 299 idu_of_init(struct device_node *intc, struct device_node *parent) 300 { 301 struct irq_domain *domain; 302 /* Read IDU BCR to confirm nr_irqs */ 303 int nr_irqs = of_irq_count(intc); 304 int i, irq; 305 306 if (!idu_detected) 307 panic("IDU not detected, but DeviceTree using it"); 308 309 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); 310 311 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); 312 313 /* Parent interrupts (core-intc) are already mapped */ 314 315 for (i = 0; i < nr_irqs; i++) { 316 /* 317 * Return parent uplink IRQs (towards core intc) 24,25,..... 318 * this step has been done before already 319 * however we need it to get the parent virq and set IDU handler 320 * as first level isr 321 */ 322 irq = irq_of_parse_and_map(intc, i); 323 if (!i) 324 idu_first_irq = irq; 325 326 irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain); 327 } 328 329 __mcip_cmd(CMD_IDU_ENABLE, 0); 330 331 return 0; 332 } 333 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); 334