1 /* 2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/smp.h> 12 #include <linux/irq.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/spinlock.h> 15 #include <soc/arc/mcip.h> 16 #include <asm/irqflags-arcv2.h> 17 #include <asm/setup.h> 18 19 static DEFINE_RAW_SPINLOCK(mcip_lock); 20 21 #ifdef CONFIG_SMP 22 23 static char smp_cpuinfo_buf[128]; 24 25 static void mcip_setup_per_cpu(int cpu) 26 { 27 smp_ipi_irq_setup(cpu, IPI_IRQ); 28 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); 29 } 30 31 static void mcip_ipi_send(int cpu) 32 { 33 unsigned long flags; 34 int ipi_was_pending; 35 36 /* ARConnect can only send IPI to others */ 37 if (unlikely(cpu == raw_smp_processor_id())) { 38 arc_softirq_trigger(SOFTIRQ_IRQ); 39 return; 40 } 41 42 raw_spin_lock_irqsave(&mcip_lock, flags); 43 44 /* 45 * If receiver already has a pending interrupt, elide sending this one. 46 * Linux cross core calling works well with concurrent IPIs 47 * coalesced into one 48 * see arch/arc/kernel/smp.c: ipi_send_msg_one() 49 */ 50 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); 51 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); 52 if (!ipi_was_pending) 53 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); 54 55 raw_spin_unlock_irqrestore(&mcip_lock, flags); 56 } 57 58 static void mcip_ipi_clear(int irq) 59 { 60 unsigned int cpu, c; 61 unsigned long flags; 62 63 if (unlikely(irq == SOFTIRQ_IRQ)) { 64 arc_softirq_clear(irq); 65 return; 66 } 67 68 raw_spin_lock_irqsave(&mcip_lock, flags); 69 70 /* Who sent the IPI */ 71 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); 72 73 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ 74 75 /* 76 * In rare case, multiple concurrent IPIs sent to same target can 77 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be 78 * "vectored" (multiple bits sets) as opposed to typical single bit 79 */ 80 do { 81 c = __ffs(cpu); /* 0,1,2,3 */ 82 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); 83 cpu &= ~(1U << c); 84 } while (cpu); 85 86 raw_spin_unlock_irqrestore(&mcip_lock, flags); 87 } 88 89 static void mcip_probe_n_setup(void) 90 { 91 struct mcip_bcr mp; 92 93 READ_BCR(ARC_REG_MCIP_BCR, mp); 94 95 sprintf(smp_cpuinfo_buf, 96 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", 97 mp.ver, mp.num_cores, 98 IS_AVAIL1(mp.ipi, "IPI "), 99 IS_AVAIL1(mp.idu, "IDU "), 100 IS_AVAIL1(mp.dbg, "DEBUG "), 101 IS_AVAIL1(mp.gfrc, "GFRC")); 102 103 cpuinfo_arc700[0].extn.gfrc = mp.gfrc; 104 105 if (mp.dbg) { 106 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 107 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 108 } 109 } 110 111 struct plat_smp_ops plat_smp_ops = { 112 .info = smp_cpuinfo_buf, 113 .init_early_smp = mcip_probe_n_setup, 114 .init_per_cpu = mcip_setup_per_cpu, 115 .ipi_send = mcip_ipi_send, 116 .ipi_clear = mcip_ipi_clear, 117 }; 118 119 #endif 120 121 /*************************************************************************** 122 * ARCv2 Interrupt Distribution Unit (IDU) 123 * 124 * Connects external "COMMON" IRQs to core intc, providing: 125 * -dynamic routing (IRQ affinity) 126 * -load balancing (Round Robin interrupt distribution) 127 * -1:N distribution 128 * 129 * It physically resides in the MCIP hw block 130 */ 131 132 #include <linux/irqchip.h> 133 #include <linux/of.h> 134 #include <linux/of_irq.h> 135 136 /* 137 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) 138 */ 139 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) 140 { 141 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); 142 } 143 144 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, 145 unsigned int distr) 146 { 147 union { 148 unsigned int word; 149 struct { 150 unsigned int distr:2, pad:2, lvl:1, pad2:27; 151 }; 152 } data; 153 154 data.distr = distr; 155 data.lvl = lvl; 156 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); 157 } 158 159 static void idu_irq_mask_raw(irq_hw_number_t hwirq) 160 { 161 unsigned long flags; 162 163 raw_spin_lock_irqsave(&mcip_lock, flags); 164 __mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1); 165 raw_spin_unlock_irqrestore(&mcip_lock, flags); 166 } 167 168 static void idu_irq_mask(struct irq_data *data) 169 { 170 idu_irq_mask_raw(data->hwirq); 171 } 172 173 static void idu_irq_unmask(struct irq_data *data) 174 { 175 unsigned long flags; 176 177 raw_spin_lock_irqsave(&mcip_lock, flags); 178 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); 179 raw_spin_unlock_irqrestore(&mcip_lock, flags); 180 } 181 182 static int 183 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, 184 bool force) 185 { 186 unsigned long flags; 187 cpumask_t online; 188 unsigned int destination_bits; 189 unsigned int distribution_mode; 190 191 /* errout if no online cpu per @cpumask */ 192 if (!cpumask_and(&online, cpumask, cpu_online_mask)) 193 return -EINVAL; 194 195 raw_spin_lock_irqsave(&mcip_lock, flags); 196 197 destination_bits = cpumask_bits(&online)[0]; 198 idu_set_dest(data->hwirq, destination_bits); 199 200 if (ffs(destination_bits) == fls(destination_bits)) 201 distribution_mode = IDU_M_DISTRI_DEST; 202 else 203 distribution_mode = IDU_M_DISTRI_RR; 204 205 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode); 206 207 raw_spin_unlock_irqrestore(&mcip_lock, flags); 208 209 return IRQ_SET_MASK_OK; 210 } 211 212 static void idu_irq_enable(struct irq_data *data) 213 { 214 /* 215 * By default send all common interrupts to all available online CPUs. 216 * The affinity of common interrupts in IDU must be set manually since 217 * in some cases the kernel will not call irq_set_affinity() by itself: 218 * 1. When the kernel is not configured with support of SMP. 219 * 2. When the kernel is configured with support of SMP but upper 220 * interrupt controllers does not support setting of the affinity 221 * and cannot propagate it to IDU. 222 */ 223 idu_irq_set_affinity(data, cpu_online_mask, false); 224 idu_irq_unmask(data); 225 } 226 227 static struct irq_chip idu_irq_chip = { 228 .name = "MCIP IDU Intc", 229 .irq_mask = idu_irq_mask, 230 .irq_unmask = idu_irq_unmask, 231 .irq_enable = idu_irq_enable, 232 #ifdef CONFIG_SMP 233 .irq_set_affinity = idu_irq_set_affinity, 234 #endif 235 236 }; 237 238 static void idu_cascade_isr(struct irq_desc *desc) 239 { 240 struct irq_domain *idu_domain = irq_desc_get_handler_data(desc); 241 struct irq_chip *core_chip = irq_desc_get_chip(desc); 242 irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc)); 243 irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ; 244 245 chained_irq_enter(core_chip, desc); 246 generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq)); 247 chained_irq_exit(core_chip, desc); 248 } 249 250 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) 251 { 252 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); 253 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops idu_irq_ops = { 259 .xlate = irq_domain_xlate_onecell, 260 .map = idu_irq_map, 261 }; 262 263 /* 264 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) 265 * [24, 23+C]: If C > 0 then "C" common IRQs 266 * [24+C, N]: Not statically assigned, private-per-core 267 */ 268 269 270 static int __init 271 idu_of_init(struct device_node *intc, struct device_node *parent) 272 { 273 struct irq_domain *domain; 274 int nr_irqs; 275 int i, virq; 276 struct mcip_bcr mp; 277 struct mcip_idu_bcr idu_bcr; 278 279 READ_BCR(ARC_REG_MCIP_BCR, mp); 280 281 if (!mp.idu) 282 panic("IDU not detected, but DeviceTree using it"); 283 284 READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr); 285 nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr); 286 287 pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs); 288 289 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); 290 291 /* Parent interrupts (core-intc) are already mapped */ 292 293 for (i = 0; i < nr_irqs; i++) { 294 /* Mask all common interrupts by default */ 295 idu_irq_mask_raw(i); 296 297 /* 298 * Return parent uplink IRQs (towards core intc) 24,25,..... 299 * this step has been done before already 300 * however we need it to get the parent virq and set IDU handler 301 * as first level isr 302 */ 303 virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ); 304 BUG_ON(!virq); 305 irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain); 306 } 307 308 __mcip_cmd(CMD_IDU_ENABLE, 0); 309 310 return 0; 311 } 312 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); 313