1 /* 2 * ARC ARConnect (MultiCore IP) support (formerly known as MCIP) 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/smp.h> 12 #include <linux/irq.h> 13 #include <linux/spinlock.h> 14 #include <asm/irqflags-arcv2.h> 15 #include <asm/mcip.h> 16 #include <asm/setup.h> 17 18 #define IPI_IRQ 19 19 #define SOFTIRQ_IRQ 21 20 21 static char smp_cpuinfo_buf[128]; 22 static int idu_detected; 23 24 static DEFINE_RAW_SPINLOCK(mcip_lock); 25 26 static void mcip_setup_per_cpu(int cpu) 27 { 28 smp_ipi_irq_setup(cpu, IPI_IRQ); 29 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); 30 } 31 32 static void mcip_ipi_send(int cpu) 33 { 34 unsigned long flags; 35 int ipi_was_pending; 36 37 /* ARConnect can only send IPI to others */ 38 if (unlikely(cpu == raw_smp_processor_id())) { 39 arc_softirq_trigger(SOFTIRQ_IRQ); 40 return; 41 } 42 43 raw_spin_lock_irqsave(&mcip_lock, flags); 44 45 /* 46 * If receiver already has a pending interrupt, elide sending this one. 47 * Linux cross core calling works well with concurrent IPIs 48 * coalesced into one 49 * see arch/arc/kernel/smp.c: ipi_send_msg_one() 50 */ 51 __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu); 52 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); 53 if (!ipi_was_pending) 54 __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu); 55 56 raw_spin_unlock_irqrestore(&mcip_lock, flags); 57 } 58 59 static void mcip_ipi_clear(int irq) 60 { 61 unsigned int cpu, c; 62 unsigned long flags; 63 64 if (unlikely(irq == SOFTIRQ_IRQ)) { 65 arc_softirq_clear(irq); 66 return; 67 } 68 69 raw_spin_lock_irqsave(&mcip_lock, flags); 70 71 /* Who sent the IPI */ 72 __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0); 73 74 cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ 75 76 /* 77 * In rare case, multiple concurrent IPIs sent to same target can 78 * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be 79 * "vectored" (multiple bits sets) as opposed to typical single bit 80 */ 81 do { 82 c = __ffs(cpu); /* 0,1,2,3 */ 83 __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c); 84 cpu &= ~(1U << c); 85 } while (cpu); 86 87 raw_spin_unlock_irqrestore(&mcip_lock, flags); 88 } 89 90 static void mcip_probe_n_setup(void) 91 { 92 struct mcip_bcr { 93 #ifdef CONFIG_CPU_BIG_ENDIAN 94 unsigned int pad3:8, 95 idu:1, llm:1, num_cores:6, 96 iocoh:1, gfrc:1, dbg:1, pad2:1, 97 msg:1, sem:1, ipi:1, pad:1, 98 ver:8; 99 #else 100 unsigned int ver:8, 101 pad:1, ipi:1, sem:1, msg:1, 102 pad2:1, dbg:1, gfrc:1, iocoh:1, 103 num_cores:6, llm:1, idu:1, 104 pad3:8; 105 #endif 106 } mp; 107 108 READ_BCR(ARC_REG_MCIP_BCR, mp); 109 110 sprintf(smp_cpuinfo_buf, 111 "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s%s\n", 112 mp.ver, mp.num_cores, 113 IS_AVAIL1(mp.ipi, "IPI "), 114 IS_AVAIL1(mp.idu, "IDU "), 115 IS_AVAIL1(mp.llm, "LLM "), 116 IS_AVAIL1(mp.dbg, "DEBUG "), 117 IS_AVAIL1(mp.gfrc, "GFRC")); 118 119 idu_detected = mp.idu; 120 121 if (mp.dbg) { 122 __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); 123 __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); 124 } 125 126 if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc) 127 panic("kernel trying to use non-existent GFRC\n"); 128 } 129 130 struct plat_smp_ops plat_smp_ops = { 131 .info = smp_cpuinfo_buf, 132 .init_early_smp = mcip_probe_n_setup, 133 .init_per_cpu = mcip_setup_per_cpu, 134 .ipi_send = mcip_ipi_send, 135 .ipi_clear = mcip_ipi_clear, 136 }; 137 138 /*************************************************************************** 139 * ARCv2 Interrupt Distribution Unit (IDU) 140 * 141 * Connects external "COMMON" IRQs to core intc, providing: 142 * -dynamic routing (IRQ affinity) 143 * -load balancing (Round Robin interrupt distribution) 144 * -1:N distribution 145 * 146 * It physically resides in the MCIP hw block 147 */ 148 149 #include <linux/irqchip.h> 150 #include <linux/of.h> 151 #include <linux/of_irq.h> 152 153 /* 154 * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) 155 */ 156 static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) 157 { 158 __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); 159 } 160 161 static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, 162 unsigned int distr) 163 { 164 union { 165 unsigned int word; 166 struct { 167 unsigned int distr:2, pad:2, lvl:1, pad2:27; 168 }; 169 } data; 170 171 data.distr = distr; 172 data.lvl = lvl; 173 __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); 174 } 175 176 static void idu_irq_mask(struct irq_data *data) 177 { 178 unsigned long flags; 179 180 raw_spin_lock_irqsave(&mcip_lock, flags); 181 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1); 182 raw_spin_unlock_irqrestore(&mcip_lock, flags); 183 } 184 185 static void idu_irq_unmask(struct irq_data *data) 186 { 187 unsigned long flags; 188 189 raw_spin_lock_irqsave(&mcip_lock, flags); 190 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); 191 raw_spin_unlock_irqrestore(&mcip_lock, flags); 192 } 193 194 #ifdef CONFIG_SMP 195 static int 196 idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask, 197 bool force) 198 { 199 unsigned long flags; 200 cpumask_t online; 201 202 /* errout if no online cpu per @cpumask */ 203 if (!cpumask_and(&online, cpumask, cpu_online_mask)) 204 return -EINVAL; 205 206 raw_spin_lock_irqsave(&mcip_lock, flags); 207 208 idu_set_dest(data->hwirq, cpumask_bits(&online)[0]); 209 idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 210 211 raw_spin_unlock_irqrestore(&mcip_lock, flags); 212 213 return IRQ_SET_MASK_OK; 214 } 215 #endif 216 217 static struct irq_chip idu_irq_chip = { 218 .name = "MCIP IDU Intc", 219 .irq_mask = idu_irq_mask, 220 .irq_unmask = idu_irq_unmask, 221 #ifdef CONFIG_SMP 222 .irq_set_affinity = idu_irq_set_affinity, 223 #endif 224 225 }; 226 227 static int idu_first_irq; 228 229 static void idu_cascade_isr(struct irq_desc *desc) 230 { 231 struct irq_domain *domain = irq_desc_get_handler_data(desc); 232 unsigned int core_irq = irq_desc_get_irq(desc); 233 unsigned int idu_irq; 234 235 idu_irq = core_irq - idu_first_irq; 236 generic_handle_irq(irq_find_mapping(domain, idu_irq)); 237 } 238 239 static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) 240 { 241 irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq); 242 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 243 244 return 0; 245 } 246 247 static int idu_irq_xlate(struct irq_domain *d, struct device_node *n, 248 const u32 *intspec, unsigned int intsize, 249 irq_hw_number_t *out_hwirq, unsigned int *out_type) 250 { 251 irq_hw_number_t hwirq = *out_hwirq = intspec[0]; 252 int distri = intspec[1]; 253 unsigned long flags; 254 255 *out_type = IRQ_TYPE_NONE; 256 257 /* XXX: validate distribution scheme again online cpu mask */ 258 if (distri == 0) { 259 /* 0 - Round Robin to all cpus, otherwise 1 bit per core */ 260 raw_spin_lock_irqsave(&mcip_lock, flags); 261 idu_set_dest(hwirq, BIT(num_online_cpus()) - 1); 262 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR); 263 raw_spin_unlock_irqrestore(&mcip_lock, flags); 264 } else { 265 /* 266 * DEST based distribution for Level Triggered intr can only 267 * have 1 CPU, so generalize it to always contain 1 cpu 268 */ 269 int cpu = ffs(distri); 270 271 if (cpu != fls(distri)) 272 pr_warn("IDU irq %lx distri mode set to cpu %x\n", 273 hwirq, cpu); 274 275 raw_spin_lock_irqsave(&mcip_lock, flags); 276 idu_set_dest(hwirq, cpu); 277 idu_set_mode(hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_DEST); 278 raw_spin_unlock_irqrestore(&mcip_lock, flags); 279 } 280 281 return 0; 282 } 283 284 static const struct irq_domain_ops idu_irq_ops = { 285 .xlate = idu_irq_xlate, 286 .map = idu_irq_map, 287 }; 288 289 /* 290 * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI) 291 * [24, 23+C]: If C > 0 then "C" common IRQs 292 * [24+C, N]: Not statically assigned, private-per-core 293 */ 294 295 296 static int __init 297 idu_of_init(struct device_node *intc, struct device_node *parent) 298 { 299 struct irq_domain *domain; 300 /* Read IDU BCR to confirm nr_irqs */ 301 int nr_irqs = of_irq_count(intc); 302 int i, irq; 303 304 if (!idu_detected) 305 panic("IDU not detected, but DeviceTree using it"); 306 307 pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs); 308 309 domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL); 310 311 /* Parent interrupts (core-intc) are already mapped */ 312 313 for (i = 0; i < nr_irqs; i++) { 314 /* 315 * Return parent uplink IRQs (towards core intc) 24,25,..... 316 * this step has been done before already 317 * however we need it to get the parent virq and set IDU handler 318 * as first level isr 319 */ 320 irq = irq_of_parse_and_map(intc, i); 321 if (!i) 322 idu_first_irq = irq; 323 324 irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain); 325 } 326 327 __mcip_cmd(CMD_IDU_ENABLE, 0); 328 329 return 0; 330 } 331 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init); 332