1 /* 2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip.h> 15 #include "../../drivers/irqchip/irqchip.h" 16 #include <asm/sections.h> 17 #include <asm/irq.h> 18 #include <asm/mach_desc.h> 19 20 /* 21 * Early Hardware specific Interrupt setup 22 * -Called very early (start_kernel -> setup_arch -> setup_processor) 23 * -Platform Independent (must for any ARC700) 24 * -Needed for each CPU (hence not foldable into init_IRQ) 25 * 26 * what it does ? 27 * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000 28 * -Disable all IRQs (on CPU side) 29 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 30 */ 31 void arc_init_IRQ(void) 32 { 33 int level_mask = 0; 34 35 /* Disable all IRQs: enable them as devices request */ 36 write_aux_reg(AUX_IENABLE, 0); 37 38 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ 39 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; 40 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; 41 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; 42 43 if (level_mask) { 44 pr_info("Level-2 interrupts bitset %x\n", level_mask); 45 write_aux_reg(AUX_IRQ_LEV, level_mask); 46 } 47 } 48 49 /* 50 * ARC700 core includes a simple on-chip intc supporting 51 * -per IRQ enable/disable 52 * -2 levels of interrupts (high/low) 53 * -all interrupts being level triggered 54 * 55 * To reduce platform code, we assume all IRQs directly hooked-up into intc. 56 * Platforms with external intc, hence cascaded IRQs, are free to over-ride 57 * below, per IRQ. 58 */ 59 60 static void arc_mask_irq(struct irq_data *data) 61 { 62 arch_mask_irq(data->irq); 63 } 64 65 static void arc_unmask_irq(struct irq_data *data) 66 { 67 arch_unmask_irq(data->irq); 68 } 69 70 static struct irq_chip onchip_intc = { 71 .name = "ARC In-core Intc", 72 .irq_mask = arc_mask_irq, 73 .irq_unmask = arc_unmask_irq, 74 }; 75 76 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 77 irq_hw_number_t hw) 78 { 79 if (irq == TIMER0_IRQ) 80 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 81 else 82 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); 83 84 return 0; 85 } 86 87 static const struct irq_domain_ops arc_intc_domain_ops = { 88 .xlate = irq_domain_xlate_onecell, 89 .map = arc_intc_domain_map, 90 }; 91 92 static struct irq_domain *root_domain; 93 94 static int __init 95 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 96 { 97 if (parent) 98 panic("DeviceTree incore intc not a root irq controller\n"); 99 100 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, 101 &arc_intc_domain_ops, NULL); 102 103 if (!root_domain) 104 panic("root irq domain not avail\n"); 105 106 /* with this we don't need to export root_domain */ 107 irq_set_default_host(root_domain); 108 109 return 0; 110 } 111 112 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); 113 114 /* 115 * Late Interrupt system init called from start_kernel for Boot CPU only 116 * 117 * Since slab must already be initialized, platforms can start doing any 118 * needed request_irq( )s 119 */ 120 void __init init_IRQ(void) 121 { 122 /* Any external intc can be setup here */ 123 if (machine_desc->init_irq) 124 machine_desc->init_irq(); 125 126 /* process the entire interrupt tree in one go */ 127 irqchip_init(); 128 129 #ifdef CONFIG_SMP 130 /* Master CPU can initialize it's side of IPI */ 131 if (machine_desc->init_smp) 132 machine_desc->init_smp(smp_processor_id()); 133 #endif 134 } 135 136 /* 137 * "C" Entry point for any ARC ISR, called from low level vector handler 138 * @irq is the vector number read from ICAUSE reg of on-chip intc 139 */ 140 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs) 141 { 142 struct pt_regs *old_regs = set_irq_regs(regs); 143 144 irq_enter(); 145 generic_handle_irq(irq); 146 irq_exit(); 147 set_irq_regs(old_regs); 148 } 149 150 int __init get_hw_config_num_irq(void) 151 { 152 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR); 153 154 switch (val & 0x03) { 155 case 0: 156 return 16; 157 case 1: 158 return 32; 159 case 2: 160 return 8; 161 default: 162 return 0; 163 } 164 165 return 0; 166 } 167 168 /* 169 * arch_local_irq_enable - Enable interrupts. 170 * 171 * 1. Explicitly called to re-enable interrupts 172 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc 173 * which maybe in hard ISR itself 174 * 175 * Semantics of this function change depending on where it is called from: 176 * 177 * -If called from hard-ISR, it must not invert interrupt priorities 178 * e.g. suppose TIMER is high priority (Level 2) IRQ 179 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. 180 * Here local_irq_enable( ) shd not re-enable lower priority interrupts 181 * -If called from soft-ISR, it must re-enable all interrupts 182 * soft ISR are low prioity jobs which can be very slow, thus all IRQs 183 * must be enabled while they run. 184 * Now hardware context wise we may still be in L2 ISR (not done rtie) 185 * still we must re-enable both L1 and L2 IRQs 186 * Another twist is prev scenario with flow being 187 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR 188 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get 189 * over-written (this is deficiency in ARC700 Interrupt mechanism) 190 */ 191 192 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ 193 194 void arch_local_irq_enable(void) 195 { 196 197 unsigned long flags; 198 flags = arch_local_save_flags(); 199 200 /* Allow both L1 and L2 at the onset */ 201 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 202 203 /* Called from hard ISR (between irq_enter and irq_exit) */ 204 if (in_irq()) { 205 206 /* If in L2 ISR, don't re-enable any further IRQs as this can 207 * cause IRQ priorities to get upside down. e.g. it could allow 208 * L1 be taken while in L2 hard ISR which is wrong not only in 209 * theory, it can also cause the dreaded L1-L2-L1 scenario 210 */ 211 if (flags & STATUS_A2_MASK) 212 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); 213 214 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */ 215 else if (flags & STATUS_A1_MASK) 216 flags &= ~(STATUS_E1_MASK); 217 } 218 219 /* called from soft IRQ, ideally we want to re-enable all levels */ 220 221 else if (in_softirq()) { 222 223 /* However if this is case of L1 interrupted by L2, 224 * re-enabling both may cause whaco L1-L2-L1 scenario 225 * because ARC700 allows level 1 to interrupt an active L2 ISR 226 * Thus we disable both 227 * However some code, executing in soft ISR wants some IRQs 228 * to be enabled so we re-enable L2 only 229 * 230 * How do we determine L1 intr by L2 231 * -A2 is set (means in L2 ISR) 232 * -E1 is set in this ISR's pt_regs->status32 which is 233 * saved copy of status32_l2 when l2 ISR happened 234 */ 235 struct pt_regs *pt = get_irq_regs(); 236 if ((flags & STATUS_A2_MASK) && pt && 237 (pt->status32 & STATUS_A1_MASK)) { 238 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */ 239 flags &= ~(STATUS_E1_MASK); 240 } 241 } 242 243 arch_local_irq_restore(flags); 244 } 245 246 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */ 247 248 /* 249 * Simpler version for only 1 level of interrupt 250 * Here we only Worry about Level 1 Bits 251 */ 252 void arch_local_irq_enable(void) 253 { 254 unsigned long flags; 255 256 /* 257 * ARC IDE Drivers tries to re-enable interrupts from hard-isr 258 * context which is simply wrong 259 */ 260 if (in_irq()) { 261 WARN_ONCE(1, "IRQ enabled from hard-isr"); 262 return; 263 } 264 265 flags = arch_local_save_flags(); 266 flags |= (STATUS_E1_MASK | STATUS_E2_MASK); 267 arch_local_irq_restore(flags); 268 } 269 #endif 270 EXPORT_SYMBOL(arch_local_irq_enable); 271