1 /* 2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip.h> 15 #include <asm/irq.h> 16 17 #define NR_CPU_IRQS 32 /* number of irq lines coming in */ 18 #define TIMER0_IRQ 3 /* Fixed by ISA */ 19 20 /* 21 * Early Hardware specific Interrupt setup 22 * -Platform independent, needed for each CPU (not foldable into init_IRQ) 23 * -Called very early (start_kernel -> setup_arch -> setup_processor) 24 * 25 * what it does ? 26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 27 */ 28 void arc_init_IRQ(void) 29 { 30 int level_mask = 0; 31 32 /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */ 33 level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ; 34 35 /* 36 * Write to register, even if no LV2 IRQs configured to reset it 37 * in case bootloader had mucked with it 38 */ 39 write_aux_reg(AUX_IRQ_LEV, level_mask); 40 41 if (level_mask) 42 pr_info("Level-2 interrupts bitset %x\n", level_mask); 43 } 44 45 /* 46 * ARC700 core includes a simple on-chip intc supporting 47 * -per IRQ enable/disable 48 * -2 levels of interrupts (high/low) 49 * -all interrupts being level triggered 50 * 51 * To reduce platform code, we assume all IRQs directly hooked-up into intc. 52 * Platforms with external intc, hence cascaded IRQs, are free to over-ride 53 * below, per IRQ. 54 */ 55 56 static void arc_irq_mask(struct irq_data *data) 57 { 58 unsigned int ienb; 59 60 ienb = read_aux_reg(AUX_IENABLE); 61 ienb &= ~(1 << data->hwirq); 62 write_aux_reg(AUX_IENABLE, ienb); 63 } 64 65 static void arc_irq_unmask(struct irq_data *data) 66 { 67 unsigned int ienb; 68 69 ienb = read_aux_reg(AUX_IENABLE); 70 ienb |= (1 << data->hwirq); 71 write_aux_reg(AUX_IENABLE, ienb); 72 } 73 74 static struct irq_chip onchip_intc = { 75 .name = "ARC In-core Intc", 76 .irq_mask = arc_irq_mask, 77 .irq_unmask = arc_irq_unmask, 78 }; 79 80 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 81 irq_hw_number_t hw) 82 { 83 switch (hw) { 84 case TIMER0_IRQ: 85 irq_set_percpu_devid(irq); 86 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 87 break; 88 default: 89 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); 90 } 91 return 0; 92 } 93 94 static const struct irq_domain_ops arc_intc_domain_ops = { 95 .xlate = irq_domain_xlate_onecell, 96 .map = arc_intc_domain_map, 97 }; 98 99 static int __init 100 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 101 { 102 struct irq_domain *root_domain; 103 104 if (parent) 105 panic("DeviceTree incore intc not a root irq controller\n"); 106 107 root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, 108 &arc_intc_domain_ops, NULL); 109 if (!root_domain) 110 panic("root irq domain not avail\n"); 111 112 /* 113 * Needed for primary domain lookup to succeed 114 * This is a primary irqchip, and can never have a parent 115 */ 116 irq_set_default_host(root_domain); 117 118 return 0; 119 } 120 121 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); 122 123 /* 124 * arch_local_irq_enable - Enable interrupts. 125 * 126 * 1. Explicitly called to re-enable interrupts 127 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc 128 * which maybe in hard ISR itself 129 * 130 * Semantics of this function change depending on where it is called from: 131 * 132 * -If called from hard-ISR, it must not invert interrupt priorities 133 * e.g. suppose TIMER is high priority (Level 2) IRQ 134 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. 135 * Here local_irq_enable( ) shd not re-enable lower priority interrupts 136 * -If called from soft-ISR, it must re-enable all interrupts 137 * soft ISR are low prioity jobs which can be very slow, thus all IRQs 138 * must be enabled while they run. 139 * Now hardware context wise we may still be in L2 ISR (not done rtie) 140 * still we must re-enable both L1 and L2 IRQs 141 * Another twist is prev scenario with flow being 142 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR 143 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get 144 * over-written (this is deficiency in ARC700 Interrupt mechanism) 145 */ 146 147 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ 148 149 void arch_local_irq_enable(void) 150 { 151 unsigned long flags = arch_local_save_flags(); 152 153 if (flags & STATUS_A2_MASK) 154 flags |= STATUS_E2_MASK; 155 else if (flags & STATUS_A1_MASK) 156 flags |= STATUS_E1_MASK; 157 158 arch_local_irq_restore(flags); 159 } 160 161 EXPORT_SYMBOL(arch_local_irq_enable); 162 #endif 163