1 /* 2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip.h> 15 #include <asm/irq.h> 16 17 #define TIMER0_IRQ 3 /* Fixed by ISA */ 18 19 /* 20 * Early Hardware specific Interrupt setup 21 * -Platform independent, needed for each CPU (not foldable into init_IRQ) 22 * -Called very early (start_kernel -> setup_arch -> setup_processor) 23 * 24 * what it does ? 25 * -Optionally, setup the High priority Interrupts as Level 2 IRQs 26 */ 27 void arc_init_IRQ(void) 28 { 29 int level_mask = 0; 30 31 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */ 32 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3; 33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5; 34 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6; 35 36 /* 37 * Write to register, even if no LV2 IRQs configured to reset it 38 * in case bootloader had mucked with it 39 */ 40 write_aux_reg(AUX_IRQ_LEV, level_mask); 41 42 if (level_mask) 43 pr_info("Level-2 interrupts bitset %x\n", level_mask); 44 } 45 46 /* 47 * ARC700 core includes a simple on-chip intc supporting 48 * -per IRQ enable/disable 49 * -2 levels of interrupts (high/low) 50 * -all interrupts being level triggered 51 * 52 * To reduce platform code, we assume all IRQs directly hooked-up into intc. 53 * Platforms with external intc, hence cascaded IRQs, are free to over-ride 54 * below, per IRQ. 55 */ 56 57 static void arc_irq_mask(struct irq_data *data) 58 { 59 unsigned int ienb; 60 61 ienb = read_aux_reg(AUX_IENABLE); 62 ienb &= ~(1 << data->irq); 63 write_aux_reg(AUX_IENABLE, ienb); 64 } 65 66 static void arc_irq_unmask(struct irq_data *data) 67 { 68 unsigned int ienb; 69 70 ienb = read_aux_reg(AUX_IENABLE); 71 ienb |= (1 << data->irq); 72 write_aux_reg(AUX_IENABLE, ienb); 73 } 74 75 static struct irq_chip onchip_intc = { 76 .name = "ARC In-core Intc", 77 .irq_mask = arc_irq_mask, 78 .irq_unmask = arc_irq_unmask, 79 }; 80 81 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq, 82 irq_hw_number_t hw) 83 { 84 switch (hw) { 85 case TIMER0_IRQ: 86 irq_set_percpu_devid(irq); 87 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq); 88 break; 89 default: 90 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq); 91 } 92 return 0; 93 } 94 95 static const struct irq_domain_ops arc_intc_domain_ops = { 96 .xlate = irq_domain_xlate_onecell, 97 .map = arc_intc_domain_map, 98 }; 99 100 static int __init 101 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 102 { 103 struct irq_domain *root_domain; 104 105 if (parent) 106 panic("DeviceTree incore intc not a root irq controller\n"); 107 108 root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, 109 &arc_intc_domain_ops, NULL); 110 if (!root_domain) 111 panic("root irq domain not avail\n"); 112 113 /* 114 * Needed for primary domain lookup to succeed 115 * This is a primary irqchip, and can never have a parent 116 */ 117 irq_set_default_host(root_domain); 118 119 return 0; 120 } 121 122 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ); 123 124 /* 125 * arch_local_irq_enable - Enable interrupts. 126 * 127 * 1. Explicitly called to re-enable interrupts 128 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc 129 * which maybe in hard ISR itself 130 * 131 * Semantics of this function change depending on where it is called from: 132 * 133 * -If called from hard-ISR, it must not invert interrupt priorities 134 * e.g. suppose TIMER is high priority (Level 2) IRQ 135 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times. 136 * Here local_irq_enable( ) shd not re-enable lower priority interrupts 137 * -If called from soft-ISR, it must re-enable all interrupts 138 * soft ISR are low prioity jobs which can be very slow, thus all IRQs 139 * must be enabled while they run. 140 * Now hardware context wise we may still be in L2 ISR (not done rtie) 141 * still we must re-enable both L1 and L2 IRQs 142 * Another twist is prev scenario with flow being 143 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR 144 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get 145 * over-written (this is deficiency in ARC700 Interrupt mechanism) 146 */ 147 148 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */ 149 150 void arch_local_irq_enable(void) 151 { 152 unsigned long flags = arch_local_save_flags(); 153 154 if (flags & STATUS_A2_MASK) 155 flags |= STATUS_E2_MASK; 156 else if (flags & STATUS_A1_MASK) 157 flags |= STATUS_E1_MASK; 158 159 arch_local_irq_restore(flags); 160 } 161 162 EXPORT_SYMBOL(arch_local_irq_enable); 163 #endif 164