1 /* 2 * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip.h> 15 #include <asm/irq.h> 16 17 #define NR_EXCEPTIONS 16 18 19 struct bcr_irq_arcv2 { 20 #ifdef CONFIG_CPU_BIG_ENDIAN 21 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; 22 #else 23 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3; 24 #endif 25 }; 26 27 /* 28 * Early Hardware specific Interrupt setup 29 * -Called very early (start_kernel -> setup_arch -> setup_processor) 30 * -Platform Independent (must for any ARC Core) 31 * -Needed for each CPU (hence not foldable into init_IRQ) 32 */ 33 void arc_init_IRQ(void) 34 { 35 unsigned int tmp, irq_prio, i; 36 struct bcr_irq_arcv2 irq_bcr; 37 38 struct aux_irq_ctrl { 39 #ifdef CONFIG_CPU_BIG_ENDIAN 40 unsigned int res3:18, save_idx_regs:1, res2:1, 41 save_u_to_u:1, save_lp_regs:1, save_blink:1, 42 res:4, save_nr_gpr_pairs:5; 43 #else 44 unsigned int save_nr_gpr_pairs:5, res:4, 45 save_blink:1, save_lp_regs:1, save_u_to_u:1, 46 res2:1, save_idx_regs:1, res3:18; 47 #endif 48 } ictrl; 49 50 *(unsigned int *)&ictrl = 0; 51 52 #ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE 53 ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ 54 ictrl.save_blink = 1; 55 ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ 56 ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ 57 ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ 58 #endif 59 60 WRITE_AUX(AUX_IRQ_CTRL, ictrl); 61 62 /* 63 * ARCv2 core intc provides multiple interrupt priorities (upto 16). 64 * Typical builds though have only two levels (0-high, 1-low) 65 * Linux by default uses lower prio 1 for most irqs, reserving 0 for 66 * NMI style interrupts in future (say perf) 67 */ 68 69 READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); 70 71 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ 72 pr_info("archs-intc\t: %d priority levels (default %d)%s\n", 73 irq_prio + 1, ARCV2_IRQ_DEF_PRIO, 74 irq_bcr.firq ? " FIRQ (not used)":""); 75 76 /* 77 * Set a default priority for all available interrupts to prevent 78 * switching of register banks if Fast IRQ and multiple register banks 79 * are supported by CPU. 80 * Also disable private-per-core IRQ lines so faulty external HW won't 81 * trigger interrupt that kernel is not ready to handle. 82 */ 83 for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { 84 write_aux_reg(AUX_IRQ_SELECT, i); 85 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); 86 87 /* 88 * Only mask cpu private IRQs here. 89 * "common" interrupts are masked at IDU, otherwise it would 90 * need to be unmasked at each cpu, with IPIs 91 */ 92 if (i < FIRST_EXT_IRQ) 93 write_aux_reg(AUX_IRQ_ENABLE, 0); 94 } 95 96 /* setup status32, don't enable intr yet as kernel doesn't want */ 97 tmp = read_aux_reg(ARC_REG_STATUS32); 98 tmp |= ARCV2_IRQ_DEF_PRIO << 1; 99 tmp &= ~STATUS_IE_MASK; 100 asm volatile("kflag %0 \n"::"r"(tmp)); 101 } 102 103 static void arcv2_irq_mask(struct irq_data *data) 104 { 105 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); 106 write_aux_reg(AUX_IRQ_ENABLE, 0); 107 } 108 109 static void arcv2_irq_unmask(struct irq_data *data) 110 { 111 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); 112 write_aux_reg(AUX_IRQ_ENABLE, 1); 113 } 114 115 void arcv2_irq_enable(struct irq_data *data) 116 { 117 /* set default priority */ 118 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); 119 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); 120 121 /* 122 * hw auto enables (linux unmask) all by default 123 * So no need to do IRQ_ENABLE here 124 * XXX: However OSCI LAN need it 125 */ 126 write_aux_reg(AUX_IRQ_ENABLE, 1); 127 } 128 129 static struct irq_chip arcv2_irq_chip = { 130 .name = "ARCv2 core Intc", 131 .irq_mask = arcv2_irq_mask, 132 .irq_unmask = arcv2_irq_unmask, 133 .irq_enable = arcv2_irq_enable 134 }; 135 136 static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, 137 irq_hw_number_t hw) 138 { 139 /* 140 * core intc IRQs [16, 23]: 141 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT) 142 */ 143 if (hw < FIRST_EXT_IRQ) { 144 /* 145 * A subsequent request_percpu_irq() fails if percpu_devid is 146 * not set. That in turns sets NOAUTOEN, meaning each core needs 147 * to call enable_percpu_irq() 148 */ 149 irq_set_percpu_devid(irq); 150 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); 151 } else { 152 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); 153 } 154 155 return 0; 156 } 157 158 static const struct irq_domain_ops arcv2_irq_ops = { 159 .xlate = irq_domain_xlate_onecell, 160 .map = arcv2_irq_map, 161 }; 162 163 164 static int __init 165 init_onchip_IRQ(struct device_node *intc, struct device_node *parent) 166 { 167 struct irq_domain *root_domain; 168 struct bcr_irq_arcv2 irq_bcr; 169 unsigned int nr_cpu_irqs; 170 171 READ_BCR(ARC_REG_IRQ_BCR, irq_bcr); 172 nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS; 173 174 if (parent) 175 panic("DeviceTree incore intc not a root irq controller\n"); 176 177 root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL); 178 if (!root_domain) 179 panic("root irq domain not avail\n"); 180 181 /* 182 * Needed for primary domain lookup to succeed 183 * This is a primary irqchip, and can never have a parent 184 */ 185 irq_set_default_host(root_domain); 186 187 #ifdef CONFIG_SMP 188 irq_create_mapping(root_domain, IPI_IRQ); 189 #endif 190 irq_create_mapping(root_domain, SOFTIRQ_IRQ); 191 192 return 0; 193 } 194 195 IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); 196