1/* 2 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA 3 * 4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * vineetg: May 2011 12 * -Userspace unaligned access emulation 13 * 14 * vineetg: Feb 2011 (ptrace low level code fixes) 15 * -traced syscall return code (r0) was not saved into pt_regs for restoring 16 * into user reg-file when traded task rets to user space. 17 * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs) 18 * were not invoking post-syscall trace hook (jumping directly into 19 * ret_from_system_call) 20 * 21 * vineetg: Nov 2010: 22 * -Vector table jumps (@8 bytes) converted into branches (@4 bytes) 23 * -To maintain the slot size of 8 bytes/vector, added nop, which is 24 * not executed at runtime. 25 * 26 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK) 27 * -do_signal()invoked upon TIF_RESTORE_SIGMASK as well 28 * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't 29 * need ptregs anymore 30 * 31 * Vineetg: Oct 2009 32 * -In a rare scenario, Process gets a Priv-V exception and gets scheduled 33 * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains 34 * active (AE bit enabled). This causes a double fault for a subseq valid 35 * exception. Thus FAKE RTIE needed in low level Priv-Violation handler. 36 * Instr Error could also cause similar scenario, so same there as well. 37 * 38 * Vineetg: March 2009 (Supporting 2 levels of Interrupts) 39 * 40 * Vineetg: Aug 28th 2008: Bug #94984 41 * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap 42 * Normally CPU does this automatically, however when doing FAKE rtie, 43 * we need to explicitly do this. The problem in macros 44 * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit 45 * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit, 46 * setting it and not clearing it clears ZOL context 47 * 48 * Vineetg: May 16th, 2008 49 * - r25 now contains the Current Task when in kernel 50 * 51 * Vineetg: Dec 22, 2007 52 * Minor Surgery of Low Level ISR to make it SMP safe 53 * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR 54 * - _current_task is made an array of NR_CPUS 55 * - Access of _current_task wrapped inside a macro so that if hardware 56 * team agrees for a dedicated reg, no other code is touched 57 * 58 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004 59 */ 60 61#include <linux/errno.h> 62#include <linux/linkage.h> /* {EXTRY,EXIT} */ 63#include <asm/entry.h> 64#include <asm/irqflags.h> 65 66 .cpu A7 67 68;############################ Vector Table ################################# 69 70.macro VECTOR lbl 71#if 1 /* Just in case, build breaks */ 72 j \lbl 73#else 74 b \lbl 75 nop 76#endif 77.endm 78 79 .section .vector, "ax",@progbits 80 .align 4 81 82/* Each entry in the vector table must occupy 2 words. Since it is a jump 83 * across sections (.vector to .text) we are gauranteed that 'j somewhere' 84 * will use the 'j limm' form of the intrsuction as long as somewhere is in 85 * a section other than .vector. 86 */ 87 88; ********* Critical System Events ********************** 89VECTOR res_service ; 0x0, Restart Vector (0x0) 90VECTOR mem_service ; 0x8, Mem exception (0x1) 91VECTOR instr_service ; 0x10, Instrn Error (0x2) 92 93; ******************** Device ISRs ********************** 94#ifdef CONFIG_ARC_IRQ3_LV2 95VECTOR handle_interrupt_level2 96#else 97VECTOR handle_interrupt_level1 98#endif 99 100VECTOR handle_interrupt_level1 101 102#ifdef CONFIG_ARC_IRQ5_LV2 103VECTOR handle_interrupt_level2 104#else 105VECTOR handle_interrupt_level1 106#endif 107 108#ifdef CONFIG_ARC_IRQ6_LV2 109VECTOR handle_interrupt_level2 110#else 111VECTOR handle_interrupt_level1 112#endif 113 114.rept 25 115VECTOR handle_interrupt_level1 ; Other devices 116.endr 117 118/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */ 119 120; ******************** Exceptions ********************** 121VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20) 122VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21) 123VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22) 124VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23) 125 ; or Misaligned Access 126VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24) 127VECTOR EV_Trap ; 0x128, Trap exception (0x25) 128VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26) 129 130.rept 24 131VECTOR reserved ; Reserved Exceptions 132.endr 133 134 135;##################### Scratch Mem for IRQ stack switching ############# 136 137ARCFP_DATA int1_saved_reg 138 .align 32 139 .type int1_saved_reg, @object 140 .size int1_saved_reg, 4 141int1_saved_reg: 142 .zero 4 143 144/* Each Interrupt level needs its own scratch */ 145#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS 146 147ARCFP_DATA int2_saved_reg 148 .type int2_saved_reg, @object 149 .size int2_saved_reg, 4 150int2_saved_reg: 151 .zero 4 152 153#endif 154 155; --------------------------------------------- 156 .section .text, "ax",@progbits 157 158res_service: ; processor restart 159 flag 0x1 ; not implemented 160 nop 161 nop 162 163reserved: ; processor restart 164 rtie ; jump to processor initializations 165 166;##################### Interrupt Handling ############################## 167 168#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS 169; --------------------------------------------- 170; Level 2 ISR: Can interrupt a Level 1 ISR 171; --------------------------------------------- 172ENTRY(handle_interrupt_level2) 173 174 INTERRUPT_PROLOGUE 2 175 176 ;------------------------------------------------------ 177 ; if L2 IRQ interrupted a L1 ISR, disable preemption 178 ;------------------------------------------------------ 179 180 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs) 181 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal 182 183 ; A1 is set in status32_l2 184 ; bump thread_info->preempt_count (Disable preemption) 185 GET_CURR_THR_INFO_FROM_SP r10 186 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT] 187 add r9, r9, 1 188 st r9, [r10, THREAD_INFO_PREEMPT_COUNT] 189 1901: 191 ;------------------------------------------------------ 192 ; setup params for Linux common ISR and invoke it 193 ;------------------------------------------------------ 194 lr r0, [icause2] 195 and r0, r0, 0x1f 196 197 bl.d @arch_do_IRQ 198 mov r1, sp 199 200 mov r8,0x2 201 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg 202 203 b ret_from_exception 204 205END(handle_interrupt_level2) 206 207#endif 208 209; --------------------------------------------- 210; Level 1 ISR 211; --------------------------------------------- 212ENTRY(handle_interrupt_level1) 213 214 INTERRUPT_PROLOGUE 1 215 216 lr r0, [icause1] 217 and r0, r0, 0x1f 218 219#ifdef CONFIG_TRACE_IRQFLAGS 220 ; icause1 needs to be read early, before calling tracing, which 221 ; can clobber scratch regs, hence use of stack to stash it 222 push r0 223 TRACE_ASM_IRQ_DISABLE 224 pop r0 225#endif 226 227 bl.d @arch_do_IRQ 228 mov r1, sp 229 230 mov r8,0x1 231 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg 232 233 b ret_from_exception 234END(handle_interrupt_level1) 235 236;################### Non TLB Exception Handling ############################# 237 238; --------------------------------------------- 239; Protection Violation Exception Handler 240; --------------------------------------------- 241 242ENTRY(EV_TLBProtV) 243 244 EXCEPTION_PROLOGUE 245 246 lr r2, [ecr] 247 lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above) 248 249 ; Exception auto-disables further Intr/exceptions. 250 ; Re-enable them by pretending to return from exception 251 ; (so rest of handler executes in pure K mode) 252 253 FAKE_RET_FROM_EXCPN 254 255 mov r1, sp ; Handle to pt_regs 256 257 ;------ (5) Type of Protection Violation? ---------- 258 ; 259 ; ProtV Hardware Exception is triggered for Access Faults of 2 types 260 ; -Access Violaton : 00_23_(00|01|02|03)_00 261 ; x r w r+w 262 ; -Unaligned Access : 00_23_04_00 263 ; 264 bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f 265 266 ;========= (6a) Access Violation Processing ======== 267 bl do_page_fault 268 b ret_from_exception 269 270 ;========== (6b) Non aligned access ============ 2714: 272 273 SAVE_CALLEE_SAVED_USER 274 mov r2, sp ; callee_regs 275 276 bl do_misaligned_access 277 278 ; TBD: optimize - do this only if a callee reg was involved 279 ; either a dst of emulated LD/ST or src with address-writeback 280 RESTORE_CALLEE_SAVED_USER 281 282 b ret_from_exception 283 284END(EV_TLBProtV) 285 286; Wrapper for Linux page fault handler called from EV_TLBMiss* 287; Very similar to ProtV handler case (6a) above, but avoids the extra checks 288; for Misaligned access 289; 290ENTRY(call_do_page_fault) 291 292 EXCEPTION_PROLOGUE 293 lr r0, [efa] ; Faulting Data address 294 mov r1, sp 295 FAKE_RET_FROM_EXCPN 296 297 mov blink, ret_from_exception 298 b do_page_fault 299 300END(call_do_page_fault) 301 302;############# Common Handlers for ARCompact and ARCv2 ############## 303 304#include "entry.S" 305 306;############# Return from Intr/Excp/Trap (ARC Specifics) ############## 307; 308; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 309; IRQ shd definitely not happen between now and rtie 310; All 2 entry points to here already disable interrupts 311 312.Lrestore_regs: 313 314 TRACE_ASM_IRQ_ENABLE 315 316 lr r10, [status32] 317 318 ; Restore REG File. In case multiple Events outstanding, 319 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None 320 ; Note that we use realtime STATUS32 (not pt_regs->status32) to 321 ; decide that. 322 323 ; if Returning from Exception 324 btst r10, STATUS_AE_BIT 325 bnz .Lexcep_ret 326 327 ; Not Exception so maybe Interrupts (Level 1 or 2) 328 329#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS 330 331 ; Level 2 interrupt return Path - from hardware standpoint 332 bbit0 r10, STATUS_A2_BIT, not_level2_interrupt 333 334 ;------------------------------------------------------------------ 335 ; However the context returning might not have taken L2 intr itself 336 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret 337 ; Special considerations needed for the context which took L2 intr 338 339 ld r9, [sp, PT_event] ; Ensure this is L2 intr context 340 brne r9, event_IRQ2, 149f 341 342 ;------------------------------------------------------------------ 343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier 344 ; so that sched doesn't move to new task, causing L1 to be delayed 345 ; undeterministically. Now that we've achieved that, let's reset 346 ; things to what they were, before returning from L2 context 347 ;---------------------------------------------------------------- 348 349 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs) 350 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal 351 352 ; decrement thread_info->preempt_count (re-enable preemption) 353 GET_CURR_THR_INFO_FROM_SP r10 354 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT] 355 356 ; paranoid check, given A1 was active when A2 happened, preempt count 357 ; must not be 0 because we would have incremented it. 358 ; If this does happen we simply HALT as it means a BUG !!! 359 cmp r9, 0 360 bnz 2f 361 flag 1 362 3632: 364 sub r9, r9, 1 365 st r9, [r10, THREAD_INFO_PREEMPT_COUNT] 366 367149: 368 ;return from level 2 369 INTERRUPT_EPILOGUE 2 370debug_marker_l2: 371 rtie 372 373not_level2_interrupt: 374 375#endif 376 377 bbit0 r10, STATUS_A1_BIT, .Lpure_k_mode_ret 378 379 ;return from level 1 380 INTERRUPT_EPILOGUE 1 381debug_marker_l1: 382 rtie 383 384.Lexcep_ret: 385.Lpure_k_mode_ret: 386 387 ;this case is for syscalls or Exceptions or pure kernel mode 388 389 EXCEPTION_EPILOGUE 390debug_marker_syscall: 391 rtie 392 393END(ret_from_exception) 394