1/* 2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 12#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 13#include <asm/errno.h> 14#include <asm/arcregs.h> 15#include <asm/irqflags.h> 16 17 .cpu HS 18 19#define VECTOR .word 20 21;############################ Vector Table ################################# 22 23 .section .vector,"a",@progbits 24 .align 4 25 26# Initial 16 slots are Exception Vectors 27VECTOR stext ; Restart Vector (jump to entry point) 28VECTOR mem_service ; Mem exception 29VECTOR instr_service ; Instrn Error 30VECTOR EV_MachineCheck ; Fatal Machine check 31VECTOR EV_TLBMissI ; Intruction TLB miss 32VECTOR EV_TLBMissD ; Data TLB miss 33VECTOR EV_TLBProtV ; Protection Violation 34VECTOR EV_PrivilegeV ; Privilege Violation 35VECTOR EV_SWI ; Software Breakpoint 36VECTOR EV_Trap ; Trap exception 37VECTOR EV_Extension ; Extn Instruction Exception 38VECTOR EV_DivZero ; Divide by Zero 39VECTOR EV_DCError ; Data Cache Error 40VECTOR EV_Misaligned ; Misaligned Data Access 41VECTOR reserved ; Reserved slots 42VECTOR reserved ; Reserved slots 43 44# Begin Interrupt Vectors 45VECTOR handle_interrupt ; (16) Timer0 46VECTOR handle_interrupt ; unused (Timer1) 47VECTOR handle_interrupt ; unused (WDT) 48VECTOR handle_interrupt ; (19) ICI (inter core interrupt) 49VECTOR handle_interrupt 50VECTOR handle_interrupt 51VECTOR handle_interrupt 52VECTOR handle_interrupt ; (23) End of fixed IRQs 53 54.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8 55 VECTOR handle_interrupt 56.endr 57 58 .section .text, "ax",@progbits 59 60res_service: ; processor restart 61 flag 0x1 ; not implemented 62 nop 63 nop 64 65reserved: ; processor restart 66 rtie ; jump to processor initializations 67 68;##################### Interrupt Handling ############################## 69 70ENTRY(handle_interrupt) 71 72 INTERRUPT_PROLOGUE irq 73 74 clri ; To make status32.IE agree with CPU internal state 75 76 lr r0, [ICAUSE] 77 78 mov blink, ret_from_exception 79 80 b.d arch_do_IRQ 81 mov r1, sp 82 83END(handle_interrupt) 84 85;################### Non TLB Exception Handling ############################# 86 87ENTRY(EV_SWI) 88 flag 1 89END(EV_SWI) 90 91ENTRY(EV_DivZero) 92 flag 1 93END(EV_DivZero) 94 95ENTRY(EV_DCError) 96 flag 1 97END(EV_DCError) 98 99ENTRY(EV_Misaligned) 100 101 EXCEPTION_PROLOGUE 102 103 lr r0, [efa] ; Faulting Data address 104 mov r1, sp 105 106 FAKE_RET_FROM_EXCPN 107 108 SAVE_CALLEE_SAVED_USER 109 mov r2, sp ; callee_regs 110 111 bl do_misaligned_access 112 113 ; TBD: optimize - do this only if a callee reg was involved 114 ; either a dst of emulated LD/ST or src with address-writeback 115 RESTORE_CALLEE_SAVED_USER 116 117 b ret_from_exception 118END(EV_Misaligned) 119 120; --------------------------------------------- 121; Protection Violation Exception Handler 122; --------------------------------------------- 123 124ENTRY(EV_TLBProtV) 125 126 EXCEPTION_PROLOGUE 127 128 lr r0, [efa] ; Faulting Data address 129 mov r1, sp ; pt_regs 130 131 FAKE_RET_FROM_EXCPN 132 133 mov blink, ret_from_exception 134 b do_page_fault 135 136END(EV_TLBProtV) 137 138; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 139; need to call do_page_fault(). 140; ECR in pt_regs provides whether access was R/W/X 141 142.global call_do_page_fault 143.set call_do_page_fault, EV_TLBProtV 144 145;############# Common Handlers for ARCompact and ARCv2 ############## 146 147#include "entry.S" 148 149;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 150; 151; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 152; IRQ shd definitely not happen between now and rtie 153; All 2 entry points to here already disable interrupts 154 155.Lrestore_regs: 156 157 ld r0, [sp, PT_status32] ; U/K mode at time of entry 158 lr r10, [AUX_IRQ_ACT] 159 160 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 161 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 162 163;####### Return from Intr ####### 164 165debug_marker_l1: 166 bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 167 168.Lisr_ret_fast_path: 169 ; Handle special case #1: (Entry via Exception, Return via IRQ) 170 ; 171 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 172 ; task now returning to U mode (riding the Intr) 173 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 174 ; won't be switched to correct U mode value (from AUX_SP) 175 ; So force AUX_IRQ_ACT.U for such a case 176 177 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 178 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 179 sr r11, [AUX_IRQ_ACT] 180 181 INTERRUPT_EPILOGUE irq 182 rtie 183 184;####### Return from Exception / pure kernel mode ####### 185 186.Lexcept_ret: ; Expects r0 has PT_status32 187 188debug_marker_syscall: 189 EXCEPTION_EPILOGUE 190 rtie 191 192;####### Return from Intr to insn in delay slot ####### 193 194; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 195; 196; Intr returning to a Delay Slot (DS) insn 197; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 198; entry was via Exception in DS which got preempted in kernel). 199; 200; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling 201.Lintr_ret_to_delay_slot: 202debug_marker_ds: 203 204 ld r2, [@intr_to_DE_cnt] 205 add r2, r2, 1 206 st r2, [@intr_to_DE_cnt] 207 208 ld r2, [sp, PT_ret] 209 ld r3, [sp, PT_status32] 210 211 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 212 st r0, [sp, PT_status32] 213 214 mov r1, .Lintr_ret_to_delay_slot_2 215 st r1, [sp, PT_ret] 216 217 st r2, [sp, 0] 218 st r3, [sp, 4] 219 220 b .Lisr_ret_fast_path 221 222.Lintr_ret_to_delay_slot_2: 223 sub sp, sp, SZ_PT_REGS 224 st r9, [sp, -4] 225 226 ld r9, [sp, 0] 227 sr r9, [eret] 228 229 ld r9, [sp, 4] 230 sr r9, [erstatus] 231 232 ld r9, [sp, 8] 233 sr r9, [erbta] 234 235 ld r9, [sp, -4] 236 add sp, sp, SZ_PT_REGS 237 rtie 238 239END(ret_from_exception) 240