1/* 2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 12#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 13#include <asm/errno.h> 14#include <asm/arcregs.h> 15#include <asm/irqflags.h> 16 17 .cpu HS 18 19#define VECTOR .word 20 21;############################ Vector Table ################################# 22 23 .section .vector,"a",@progbits 24 .align 4 25 26# Initial 16 slots are Exception Vectors 27VECTOR res_service ; Reset Vector 28VECTOR mem_service ; Mem exception 29VECTOR instr_service ; Instrn Error 30VECTOR EV_MachineCheck ; Fatal Machine check 31VECTOR EV_TLBMissI ; Intruction TLB miss 32VECTOR EV_TLBMissD ; Data TLB miss 33VECTOR EV_TLBProtV ; Protection Violation 34VECTOR EV_PrivilegeV ; Privilege Violation 35VECTOR EV_SWI ; Software Breakpoint 36VECTOR EV_Trap ; Trap exception 37VECTOR EV_Extension ; Extn Instruction Exception 38VECTOR EV_DivZero ; Divide by Zero 39VECTOR EV_DCError ; Data Cache Error 40VECTOR EV_Misaligned ; Misaligned Data Access 41VECTOR reserved ; Reserved slots 42VECTOR reserved ; Reserved slots 43 44# Begin Interrupt Vectors 45VECTOR handle_interrupt ; (16) Timer0 46VECTOR handle_interrupt ; unused (Timer1) 47VECTOR handle_interrupt ; unused (WDT) 48VECTOR handle_interrupt ; (19) ICI (inter core interrupt) 49VECTOR handle_interrupt 50VECTOR handle_interrupt 51VECTOR handle_interrupt 52VECTOR handle_interrupt ; (23) End of fixed IRQs 53 54.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8 55 VECTOR handle_interrupt 56.endr 57 58 .section .text, "ax",@progbits 59 60reserved: 61 flag 1 ; Unexpected event, halt 62 63;##################### Interrupt Handling ############################## 64 65ENTRY(handle_interrupt) 66 67 INTERRUPT_PROLOGUE irq 68 69 clri ; To make status32.IE agree with CPU internal state 70 71 lr r0, [ICAUSE] 72 73 mov blink, ret_from_exception 74 75 b.d arch_do_IRQ 76 mov r1, sp 77 78END(handle_interrupt) 79 80;################### Non TLB Exception Handling ############################# 81 82ENTRY(EV_SWI) 83 flag 1 84END(EV_SWI) 85 86ENTRY(EV_DivZero) 87 flag 1 88END(EV_DivZero) 89 90ENTRY(EV_DCError) 91 flag 1 92END(EV_DCError) 93 94; --------------------------------------------- 95; Memory Error Exception Handler 96; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 97; Instruction fetch or Data access, under a single Exception Vector 98; --------------------------------------------- 99 100ENTRY(mem_service) 101 102 EXCEPTION_PROLOGUE 103 104 lr r0, [efa] 105 mov r1, sp 106 107 FAKE_RET_FROM_EXCPN 108 109 bl do_memory_error 110 b ret_from_exception 111END(mem_service) 112 113ENTRY(EV_Misaligned) 114 115 EXCEPTION_PROLOGUE 116 117 lr r0, [efa] ; Faulting Data address 118 mov r1, sp 119 120 FAKE_RET_FROM_EXCPN 121 122 SAVE_CALLEE_SAVED_USER 123 mov r2, sp ; callee_regs 124 125 bl do_misaligned_access 126 127 ; TBD: optimize - do this only if a callee reg was involved 128 ; either a dst of emulated LD/ST or src with address-writeback 129 RESTORE_CALLEE_SAVED_USER 130 131 b ret_from_exception 132END(EV_Misaligned) 133 134; --------------------------------------------- 135; Protection Violation Exception Handler 136; --------------------------------------------- 137 138ENTRY(EV_TLBProtV) 139 140 EXCEPTION_PROLOGUE 141 142 lr r0, [efa] ; Faulting Data address 143 mov r1, sp ; pt_regs 144 145 FAKE_RET_FROM_EXCPN 146 147 mov blink, ret_from_exception 148 b do_page_fault 149 150END(EV_TLBProtV) 151 152; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 153; need to call do_page_fault(). 154; ECR in pt_regs provides whether access was R/W/X 155 156.global call_do_page_fault 157.set call_do_page_fault, EV_TLBProtV 158 159;############# Common Handlers for ARCompact and ARCv2 ############## 160 161#include "entry.S" 162 163;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 164; 165; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 166; IRQ shd definitely not happen between now and rtie 167; All 2 entry points to here already disable interrupts 168 169.Lrestore_regs: 170 171 ld r0, [sp, PT_status32] ; U/K mode at time of entry 172 lr r10, [AUX_IRQ_ACT] 173 174 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 175 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 176 177;####### Return from Intr ####### 178 179debug_marker_l1: 180 bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 181 182.Lisr_ret_fast_path: 183 ; Handle special case #1: (Entry via Exception, Return via IRQ) 184 ; 185 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 186 ; task now returning to U mode (riding the Intr) 187 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 188 ; won't be switched to correct U mode value (from AUX_SP) 189 ; So force AUX_IRQ_ACT.U for such a case 190 191 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 192 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 193 sr r11, [AUX_IRQ_ACT] 194 195 INTERRUPT_EPILOGUE irq 196 rtie 197 198;####### Return from Exception / pure kernel mode ####### 199 200.Lexcept_ret: ; Expects r0 has PT_status32 201 202debug_marker_syscall: 203 EXCEPTION_EPILOGUE 204 rtie 205 206;####### Return from Intr to insn in delay slot ####### 207 208; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 209; 210; Intr returning to a Delay Slot (DS) insn 211; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 212; entry was via Exception in DS which got preempted in kernel). 213; 214; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling 215.Lintr_ret_to_delay_slot: 216debug_marker_ds: 217 218 ld r2, [@intr_to_DE_cnt] 219 add r2, r2, 1 220 st r2, [@intr_to_DE_cnt] 221 222 ld r2, [sp, PT_ret] 223 ld r3, [sp, PT_status32] 224 225 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 226 st r0, [sp, PT_status32] 227 228 mov r1, .Lintr_ret_to_delay_slot_2 229 st r1, [sp, PT_ret] 230 231 st r2, [sp, 0] 232 st r3, [sp, 4] 233 234 b .Lisr_ret_fast_path 235 236.Lintr_ret_to_delay_slot_2: 237 sub sp, sp, SZ_PT_REGS 238 st r9, [sp, -4] 239 240 ld r9, [sp, 0] 241 sr r9, [eret] 242 243 ld r9, [sp, 4] 244 sr r9, [erstatus] 245 246 ld r9, [sp, 8] 247 sr r9, [erbta] 248 249 ld r9, [sp, -4] 250 add sp, sp, SZ_PT_REGS 251 rtie 252 253END(ret_from_exception) 254