1/* 2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 3 * 4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 12#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 13#include <asm/errno.h> 14#include <asm/arcregs.h> 15#include <asm/irqflags.h> 16 17 .cpu HS 18 19#define VECTOR .word 20 21;############################ Vector Table ################################# 22 23 .section .vector,"a",@progbits 24 .align 4 25 26# Initial 16 slots are Exception Vectors 27VECTOR res_service ; Reset Vector 28VECTOR mem_service ; Mem exception 29VECTOR instr_service ; Instrn Error 30VECTOR EV_MachineCheck ; Fatal Machine check 31VECTOR EV_TLBMissI ; Intruction TLB miss 32VECTOR EV_TLBMissD ; Data TLB miss 33VECTOR EV_TLBProtV ; Protection Violation 34VECTOR EV_PrivilegeV ; Privilege Violation 35VECTOR EV_SWI ; Software Breakpoint 36VECTOR EV_Trap ; Trap exception 37VECTOR EV_Extension ; Extn Instruction Exception 38VECTOR EV_DivZero ; Divide by Zero 39VECTOR EV_DCError ; Data Cache Error 40VECTOR EV_Misaligned ; Misaligned Data Access 41VECTOR reserved ; Reserved slots 42VECTOR reserved ; Reserved slots 43 44# Begin Interrupt Vectors 45VECTOR handle_interrupt ; (16) Timer0 46VECTOR handle_interrupt ; unused (Timer1) 47VECTOR handle_interrupt ; unused (WDT) 48VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI) 49VECTOR handle_interrupt ; (20) perf Interrupt 50VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI) 51VECTOR handle_interrupt ; unused 52VECTOR handle_interrupt ; (23) unused 53# End of fixed IRQs 54 55.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8 56 VECTOR handle_interrupt 57.endr 58 59 .section .text, "ax",@progbits 60 61reserved: 62 flag 1 ; Unexpected event, halt 63 64;##################### Interrupt Handling ############################## 65 66ENTRY(handle_interrupt) 67 68 INTERRUPT_PROLOGUE irq 69 70 # irq control APIs local_irq_save/restore/disable/enable fiddle with 71 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) 72 # However a taken interrupt doesn't clear these bits. Thus irqs_disabled() 73 # query in hard ISR path would return false (since .IE is set) which would 74 # trips genirq interrupt handling asserts. 75 # 76 # So do a "soft" disable of interrutps here. 77 # 78 # Note this disable is only for consistent book-keeping as further interrupts 79 # will be disabled anyways even w/o this. Hardware tracks active interrupts 80 # seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts 81 # unless this one returns (or higher prio becomes pending in 2-prio scheme) 82 83 IRQ_DISABLE 84 85 ; icause is banked: one per priority level 86 ; so a higher prio interrupt taken here won't clobber prev prio icause 87 lr r0, [ICAUSE] 88 mov blink, ret_from_exception 89 90 b.d arch_do_IRQ 91 mov r1, sp 92 93END(handle_interrupt) 94 95;################### Non TLB Exception Handling ############################# 96 97ENTRY(EV_SWI) 98 flag 1 99END(EV_SWI) 100 101ENTRY(EV_DivZero) 102 flag 1 103END(EV_DivZero) 104 105ENTRY(EV_DCError) 106 flag 1 107END(EV_DCError) 108 109; --------------------------------------------- 110; Memory Error Exception Handler 111; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 112; Instruction fetch or Data access, under a single Exception Vector 113; --------------------------------------------- 114 115ENTRY(mem_service) 116 117 EXCEPTION_PROLOGUE 118 119 lr r0, [efa] 120 mov r1, sp 121 122 FAKE_RET_FROM_EXCPN 123 124 bl do_memory_error 125 b ret_from_exception 126END(mem_service) 127 128ENTRY(EV_Misaligned) 129 130 EXCEPTION_PROLOGUE 131 132 lr r0, [efa] ; Faulting Data address 133 mov r1, sp 134 135 FAKE_RET_FROM_EXCPN 136 137 SAVE_CALLEE_SAVED_USER 138 mov r2, sp ; callee_regs 139 140 bl do_misaligned_access 141 142 ; TBD: optimize - do this only if a callee reg was involved 143 ; either a dst of emulated LD/ST or src with address-writeback 144 RESTORE_CALLEE_SAVED_USER 145 146 b ret_from_exception 147END(EV_Misaligned) 148 149; --------------------------------------------- 150; Protection Violation Exception Handler 151; --------------------------------------------- 152 153ENTRY(EV_TLBProtV) 154 155 EXCEPTION_PROLOGUE 156 157 lr r0, [efa] ; Faulting Data address 158 mov r1, sp ; pt_regs 159 160 FAKE_RET_FROM_EXCPN 161 162 mov blink, ret_from_exception 163 b do_page_fault 164 165END(EV_TLBProtV) 166 167; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 168; need to call do_page_fault(). 169; ECR in pt_regs provides whether access was R/W/X 170 171.global call_do_page_fault 172.set call_do_page_fault, EV_TLBProtV 173 174;############# Common Handlers for ARCompact and ARCv2 ############## 175 176#include "entry.S" 177 178;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 179; 180; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 181; IRQ shd definitely not happen between now and rtie 182; All 2 entry points to here already disable interrupts 183 184.Lrestore_regs: 185restore_regs: 186 187 # Interrpts are actually disabled from this point on, but will get 188 # reenabled after we return from interrupt/exception. 189 # But irq tracer needs to be told now... 190 TRACE_ASM_IRQ_ENABLE 191 192 ld r0, [sp, PT_status32] ; U/K mode at time of entry 193 lr r10, [AUX_IRQ_ACT] 194 195 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 196 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 197 198;####### Return from Intr ####### 199 200debug_marker_l1: 201 bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 202 203.Lisr_ret_fast_path: 204 ; Handle special case #1: (Entry via Exception, Return via IRQ) 205 ; 206 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 207 ; task now returning to U mode (riding the Intr) 208 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 209 ; won't be switched to correct U mode value (from AUX_SP) 210 ; So force AUX_IRQ_ACT.U for such a case 211 212 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 213 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 214 sr r11, [AUX_IRQ_ACT] 215 216 INTERRUPT_EPILOGUE irq 217 rtie 218 219;####### Return from Exception / pure kernel mode ####### 220 221.Lexcept_ret: ; Expects r0 has PT_status32 222 223debug_marker_syscall: 224 EXCEPTION_EPILOGUE 225 rtie 226 227;####### Return from Intr to insn in delay slot ####### 228 229; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 230; 231; Intr returning to a Delay Slot (DS) insn 232; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 233; entry was via Exception in DS which got preempted in kernel). 234; 235; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround 236; 237; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline 238; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly 239 240.Lintr_ret_to_delay_slot: 241debug_marker_ds: 242 243 ld r2, [@intr_to_DE_cnt] 244 add r2, r2, 1 245 st r2, [@intr_to_DE_cnt] 246 247 ld r2, [sp, PT_ret] 248 ld r3, [sp, PT_status32] 249 250 ; STAT32 for Int return created from scratch 251 ; (No delay dlot, disable Further intr in trampoline) 252 253 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 254 st r0, [sp, PT_status32] 255 256 mov r1, .Lintr_ret_to_delay_slot_2 257 st r1, [sp, PT_ret] 258 259 ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots 260 st r2, [sp, 0] 261 st r3, [sp, 4] 262 263 b .Lisr_ret_fast_path 264 265.Lintr_ret_to_delay_slot_2: 266 ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP 267 sub sp, sp, SZ_PT_REGS 268 st r9, [sp, -4] 269 270 ld r9, [sp, 0] 271 sr r9, [eret] 272 273 ld r9, [sp, 4] 274 sr r9, [erstatus] 275 276 ; restore AUX_USER_SP if returning to U mode 277 bbit0 r9, STATUS_U_BIT, 1f 278 ld r9, [sp, PT_sp] 279 sr r9, [AUX_USER_SP] 280 2811: 282 ld r9, [sp, 8] 283 sr r9, [erbta] 284 285 ld r9, [sp, -4] 286 add sp, sp, SZ_PT_REGS 287 288 ; return from pure kernel mode to delay slot 289 rtie 290 291END(ret_from_exception) 292