1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 4 * 5 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 6 */ 7 8#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 9#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 10#include <asm/errno.h> 11#include <asm/arcregs.h> 12#include <asm/irqflags.h> 13 14; A maximum number of supported interrupts in the core interrupt controller. 15; This number is not equal to the maximum interrupt number (256) because 16; first 16 lines are reserved for exceptions and are not configurable. 17#define NR_CPU_IRQS 240 18 19 .cpu HS 20 21#define VECTOR .word 22 23;############################ Vector Table ################################# 24 25 .section .vector,"a",@progbits 26 .align 4 27 28# Initial 16 slots are Exception Vectors 29VECTOR res_service ; Reset Vector 30VECTOR mem_service ; Mem exception 31VECTOR instr_service ; Instrn Error 32VECTOR EV_MachineCheck ; Fatal Machine check 33VECTOR EV_TLBMissI ; Intruction TLB miss 34VECTOR EV_TLBMissD ; Data TLB miss 35VECTOR EV_TLBProtV ; Protection Violation 36VECTOR EV_PrivilegeV ; Privilege Violation 37VECTOR EV_SWI ; Software Breakpoint 38VECTOR EV_Trap ; Trap exception 39VECTOR EV_Extension ; Extn Instruction Exception 40VECTOR EV_DivZero ; Divide by Zero 41VECTOR EV_DCError ; Data Cache Error 42VECTOR EV_Misaligned ; Misaligned Data Access 43VECTOR reserved ; Reserved slots 44VECTOR reserved ; Reserved slots 45 46# Begin Interrupt Vectors 47VECTOR handle_interrupt ; (16) Timer0 48VECTOR handle_interrupt ; unused (Timer1) 49VECTOR handle_interrupt ; unused (WDT) 50VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI) 51VECTOR handle_interrupt ; (20) perf Interrupt 52VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI) 53VECTOR handle_interrupt ; unused 54VECTOR handle_interrupt ; (23) unused 55# End of fixed IRQs 56 57.rept NR_CPU_IRQS - 8 58 VECTOR handle_interrupt 59.endr 60 61 .section .text, "ax",@progbits 62 63reserved: 64 flag 1 ; Unexpected event, halt 65 66;##################### Interrupt Handling ############################## 67 68ENTRY(handle_interrupt) 69 70 INTERRUPT_PROLOGUE irq 71 72 # irq control APIs local_irq_save/restore/disable/enable fiddle with 73 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) 74 # However a taken interrupt doesn't clear these bits. Thus irqs_disabled() 75 # query in hard ISR path would return false (since .IE is set) which would 76 # trips genirq interrupt handling asserts. 77 # 78 # So do a "soft" disable of interrutps here. 79 # 80 # Note this disable is only for consistent book-keeping as further interrupts 81 # will be disabled anyways even w/o this. Hardware tracks active interrupts 82 # seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts 83 # unless this one returns (or higher prio becomes pending in 2-prio scheme) 84 85 IRQ_DISABLE 86 87 ; icause is banked: one per priority level 88 ; so a higher prio interrupt taken here won't clobber prev prio icause 89 lr r0, [ICAUSE] 90 mov blink, ret_from_exception 91 92 b.d arch_do_IRQ 93 mov r1, sp 94 95END(handle_interrupt) 96 97;################### Non TLB Exception Handling ############################# 98 99ENTRY(EV_SWI) 100 ; TODO: implement this 101 EXCEPTION_PROLOGUE 102 b ret_from_exception 103END(EV_SWI) 104 105ENTRY(EV_DivZero) 106 ; TODO: implement this 107 EXCEPTION_PROLOGUE 108 b ret_from_exception 109END(EV_DivZero) 110 111ENTRY(EV_DCError) 112 ; TODO: implement this 113 EXCEPTION_PROLOGUE 114 b ret_from_exception 115END(EV_DCError) 116 117; --------------------------------------------- 118; Memory Error Exception Handler 119; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 120; Instruction fetch or Data access, under a single Exception Vector 121; --------------------------------------------- 122 123ENTRY(mem_service) 124 125 EXCEPTION_PROLOGUE 126 127 lr r0, [efa] 128 mov r1, sp 129 130 FAKE_RET_FROM_EXCPN 131 132 bl do_memory_error 133 b ret_from_exception 134END(mem_service) 135 136ENTRY(EV_Misaligned) 137 138 EXCEPTION_PROLOGUE 139 140 lr r0, [efa] ; Faulting Data address 141 mov r1, sp 142 143 FAKE_RET_FROM_EXCPN 144 145 SAVE_CALLEE_SAVED_USER 146 mov r2, sp ; callee_regs 147 148 bl do_misaligned_access 149 150 ; TBD: optimize - do this only if a callee reg was involved 151 ; either a dst of emulated LD/ST or src with address-writeback 152 RESTORE_CALLEE_SAVED_USER 153 154 b ret_from_exception 155END(EV_Misaligned) 156 157; --------------------------------------------- 158; Protection Violation Exception Handler 159; --------------------------------------------- 160 161ENTRY(EV_TLBProtV) 162 163 EXCEPTION_PROLOGUE 164 165 lr r0, [efa] ; Faulting Data address 166 mov r1, sp ; pt_regs 167 168 FAKE_RET_FROM_EXCPN 169 170 mov blink, ret_from_exception 171 b do_page_fault 172 173END(EV_TLBProtV) 174 175; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 176; need to call do_page_fault(). 177; ECR in pt_regs provides whether access was R/W/X 178 179.global call_do_page_fault 180.set call_do_page_fault, EV_TLBProtV 181 182;############# Common Handlers for ARCompact and ARCv2 ############## 183 184#include "entry.S" 185 186;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 187; 188; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 189; IRQ shd definitely not happen between now and rtie 190; All 2 entry points to here already disable interrupts 191 192.Lrestore_regs: 193restore_regs: 194 195 # Interrpts are actually disabled from this point on, but will get 196 # reenabled after we return from interrupt/exception. 197 # But irq tracer needs to be told now... 198 TRACE_ASM_IRQ_ENABLE 199 200 ld r0, [sp, PT_status32] ; U/K mode at time of entry 201 lr r10, [AUX_IRQ_ACT] 202 203 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 204 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 205 206;####### Return from Intr ####### 207 208debug_marker_l1: 209 ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 210 btst r0, STATUS_DE_BIT ; Z flag set if bit clear 211 bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set 212 213.Lisr_ret_fast_path: 214 ; Handle special case #1: (Entry via Exception, Return via IRQ) 215 ; 216 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 217 ; task now returning to U mode (riding the Intr) 218 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 219 ; won't be switched to correct U mode value (from AUX_SP) 220 ; So force AUX_IRQ_ACT.U for such a case 221 222 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 223 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 224 sr r11, [AUX_IRQ_ACT] 225 226 INTERRUPT_EPILOGUE irq 227 rtie 228 229;####### Return from Exception / pure kernel mode ####### 230 231.Lexcept_ret: ; Expects r0 has PT_status32 232 233debug_marker_syscall: 234 EXCEPTION_EPILOGUE 235 rtie 236 237;####### Return from Intr to insn in delay slot ####### 238 239; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 240; 241; Intr returning to a Delay Slot (DS) insn 242; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 243; entry was via Exception in DS which got preempted in kernel). 244; 245; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround 246; 247; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline 248; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly 249 250.Lintr_ret_to_delay_slot: 251debug_marker_ds: 252 253 ld r2, [@intr_to_DE_cnt] 254 add r2, r2, 1 255 st r2, [@intr_to_DE_cnt] 256 257 ld r2, [sp, PT_ret] 258 ld r3, [sp, PT_status32] 259 260 ; STAT32 for Int return created from scratch 261 ; (No delay dlot, disable Further intr in trampoline) 262 263 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 264 st r0, [sp, PT_status32] 265 266 mov r1, .Lintr_ret_to_delay_slot_2 267 st r1, [sp, PT_ret] 268 269 ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots 270 st r2, [sp, 0] 271 st r3, [sp, 4] 272 273 b .Lisr_ret_fast_path 274 275.Lintr_ret_to_delay_slot_2: 276 ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP 277 sub sp, sp, SZ_PT_REGS 278 st r9, [sp, -4] 279 280 ld r9, [sp, 0] 281 sr r9, [eret] 282 283 ld r9, [sp, 4] 284 sr r9, [erstatus] 285 286 ; restore AUX_USER_SP if returning to U mode 287 bbit0 r9, STATUS_U_BIT, 1f 288 ld r9, [sp, PT_sp] 289 sr r9, [AUX_USER_SP] 290 2911: 292 ld r9, [sp, 8] 293 sr r9, [erbta] 294 295 ld r9, [sp, -4] 296 add sp, sp, SZ_PT_REGS 297 298 ; return from pure kernel mode to delay slot 299 rtie 300 301END(ret_from_exception) 302