11f6ccfffSVineet Gupta/* 21f6ccfffSVineet Gupta * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 31f6ccfffSVineet Gupta * 41f6ccfffSVineet Gupta * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 51f6ccfffSVineet Gupta * 61f6ccfffSVineet Gupta * This program is free software; you can redistribute it and/or modify 71f6ccfffSVineet Gupta * it under the terms of the GNU General Public License version 2 as 81f6ccfffSVineet Gupta * published by the Free Software Foundation. 91f6ccfffSVineet Gupta */ 101f6ccfffSVineet Gupta 111f6ccfffSVineet Gupta#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 121f6ccfffSVineet Gupta#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 131f6ccfffSVineet Gupta#include <asm/errno.h> 141f6ccfffSVineet Gupta#include <asm/arcregs.h> 151f6ccfffSVineet Gupta#include <asm/irqflags.h> 161f6ccfffSVineet Gupta 171f6ccfffSVineet Gupta .cpu HS 181f6ccfffSVineet Gupta 191f6ccfffSVineet Gupta#define VECTOR .word 201f6ccfffSVineet Gupta 211f6ccfffSVineet Gupta;############################ Vector Table ################################# 221f6ccfffSVineet Gupta 231f6ccfffSVineet Gupta .section .vector,"a",@progbits 241f6ccfffSVineet Gupta .align 4 251f6ccfffSVineet Gupta 261f6ccfffSVineet Gupta# Initial 16 slots are Exception Vectors 273971cdc2SVineet GuptaVECTOR res_service ; Reset Vector 281f6ccfffSVineet GuptaVECTOR mem_service ; Mem exception 291f6ccfffSVineet GuptaVECTOR instr_service ; Instrn Error 301f6ccfffSVineet GuptaVECTOR EV_MachineCheck ; Fatal Machine check 311f6ccfffSVineet GuptaVECTOR EV_TLBMissI ; Intruction TLB miss 321f6ccfffSVineet GuptaVECTOR EV_TLBMissD ; Data TLB miss 331f6ccfffSVineet GuptaVECTOR EV_TLBProtV ; Protection Violation 341f6ccfffSVineet GuptaVECTOR EV_PrivilegeV ; Privilege Violation 351f6ccfffSVineet GuptaVECTOR EV_SWI ; Software Breakpoint 361f6ccfffSVineet GuptaVECTOR EV_Trap ; Trap exception 371f6ccfffSVineet GuptaVECTOR EV_Extension ; Extn Instruction Exception 381f6ccfffSVineet GuptaVECTOR EV_DivZero ; Divide by Zero 391f6ccfffSVineet GuptaVECTOR EV_DCError ; Data Cache Error 401f6ccfffSVineet GuptaVECTOR EV_Misaligned ; Misaligned Data Access 411f6ccfffSVineet GuptaVECTOR reserved ; Reserved slots 421f6ccfffSVineet GuptaVECTOR reserved ; Reserved slots 431f6ccfffSVineet Gupta 441f6ccfffSVineet Gupta# Begin Interrupt Vectors 451f6ccfffSVineet GuptaVECTOR handle_interrupt ; (16) Timer0 461f6ccfffSVineet GuptaVECTOR handle_interrupt ; unused (Timer1) 471f6ccfffSVineet GuptaVECTOR handle_interrupt ; unused (WDT) 48bb143f81SVineet GuptaVECTOR handle_interrupt ; (19) Inter core Interrupt (IPI) 49bb143f81SVineet GuptaVECTOR handle_interrupt ; (20) perf Interrupt 50bb143f81SVineet GuptaVECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI) 51bb143f81SVineet GuptaVECTOR handle_interrupt ; unused 52bb143f81SVineet GuptaVECTOR handle_interrupt ; (23) unused 53bb143f81SVineet Gupta# End of fixed IRQs 541f6ccfffSVineet Gupta 551f6ccfffSVineet Gupta.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8 561f6ccfffSVineet Gupta VECTOR handle_interrupt 571f6ccfffSVineet Gupta.endr 581f6ccfffSVineet Gupta 591f6ccfffSVineet Gupta .section .text, "ax",@progbits 601f6ccfffSVineet Gupta 613d592659SVineet Guptareserved: 623d592659SVineet Gupta flag 1 ; Unexpected event, halt 631f6ccfffSVineet Gupta 641f6ccfffSVineet Gupta;##################### Interrupt Handling ############################## 651f6ccfffSVineet Gupta 661f6ccfffSVineet GuptaENTRY(handle_interrupt) 671f6ccfffSVineet Gupta 681f6ccfffSVineet Gupta INTERRUPT_PROLOGUE irq 691f6ccfffSVineet Gupta 701f6ccfffSVineet Gupta clri ; To make status32.IE agree with CPU internal state 711f6ccfffSVineet Gupta 721f6ccfffSVineet Gupta lr r0, [ICAUSE] 731f6ccfffSVineet Gupta 741f6ccfffSVineet Gupta mov blink, ret_from_exception 751f6ccfffSVineet Gupta 761f6ccfffSVineet Gupta b.d arch_do_IRQ 771f6ccfffSVineet Gupta mov r1, sp 781f6ccfffSVineet Gupta 791f6ccfffSVineet GuptaEND(handle_interrupt) 801f6ccfffSVineet Gupta 811f6ccfffSVineet Gupta;################### Non TLB Exception Handling ############################# 821f6ccfffSVineet Gupta 831f6ccfffSVineet GuptaENTRY(EV_SWI) 841f6ccfffSVineet Gupta flag 1 851f6ccfffSVineet GuptaEND(EV_SWI) 861f6ccfffSVineet Gupta 871f6ccfffSVineet GuptaENTRY(EV_DivZero) 881f6ccfffSVineet Gupta flag 1 891f6ccfffSVineet GuptaEND(EV_DivZero) 901f6ccfffSVineet Gupta 911f6ccfffSVineet GuptaENTRY(EV_DCError) 921f6ccfffSVineet Gupta flag 1 931f6ccfffSVineet GuptaEND(EV_DCError) 941f6ccfffSVineet Gupta 95541366daSVineet Gupta; --------------------------------------------- 96541366daSVineet Gupta; Memory Error Exception Handler 97541366daSVineet Gupta; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 98541366daSVineet Gupta; Instruction fetch or Data access, under a single Exception Vector 99541366daSVineet Gupta; --------------------------------------------- 100541366daSVineet Gupta 101541366daSVineet GuptaENTRY(mem_service) 102541366daSVineet Gupta 103541366daSVineet Gupta EXCEPTION_PROLOGUE 104541366daSVineet Gupta 105541366daSVineet Gupta lr r0, [efa] 106541366daSVineet Gupta mov r1, sp 107541366daSVineet Gupta 108541366daSVineet Gupta FAKE_RET_FROM_EXCPN 109541366daSVineet Gupta 110541366daSVineet Gupta bl do_memory_error 111541366daSVineet Gupta b ret_from_exception 112541366daSVineet GuptaEND(mem_service) 113541366daSVineet Gupta 1141f6ccfffSVineet GuptaENTRY(EV_Misaligned) 1151f6ccfffSVineet Gupta 1161f6ccfffSVineet Gupta EXCEPTION_PROLOGUE 1171f6ccfffSVineet Gupta 1181f6ccfffSVineet Gupta lr r0, [efa] ; Faulting Data address 1191f6ccfffSVineet Gupta mov r1, sp 1201f6ccfffSVineet Gupta 1211f6ccfffSVineet Gupta FAKE_RET_FROM_EXCPN 1221f6ccfffSVineet Gupta 1231f6ccfffSVineet Gupta SAVE_CALLEE_SAVED_USER 1241f6ccfffSVineet Gupta mov r2, sp ; callee_regs 1251f6ccfffSVineet Gupta 1261f6ccfffSVineet Gupta bl do_misaligned_access 1271f6ccfffSVineet Gupta 1281f6ccfffSVineet Gupta ; TBD: optimize - do this only if a callee reg was involved 1291f6ccfffSVineet Gupta ; either a dst of emulated LD/ST or src with address-writeback 1301f6ccfffSVineet Gupta RESTORE_CALLEE_SAVED_USER 1311f6ccfffSVineet Gupta 1321f6ccfffSVineet Gupta b ret_from_exception 1331f6ccfffSVineet GuptaEND(EV_Misaligned) 1341f6ccfffSVineet Gupta 1351f6ccfffSVineet Gupta; --------------------------------------------- 1361f6ccfffSVineet Gupta; Protection Violation Exception Handler 1371f6ccfffSVineet Gupta; --------------------------------------------- 1381f6ccfffSVineet Gupta 1391f6ccfffSVineet GuptaENTRY(EV_TLBProtV) 1401f6ccfffSVineet Gupta 1411f6ccfffSVineet Gupta EXCEPTION_PROLOGUE 1421f6ccfffSVineet Gupta 1431f6ccfffSVineet Gupta lr r0, [efa] ; Faulting Data address 1441f6ccfffSVineet Gupta mov r1, sp ; pt_regs 1451f6ccfffSVineet Gupta 1461f6ccfffSVineet Gupta FAKE_RET_FROM_EXCPN 1471f6ccfffSVineet Gupta 1481f6ccfffSVineet Gupta mov blink, ret_from_exception 1491f6ccfffSVineet Gupta b do_page_fault 1501f6ccfffSVineet Gupta 1511f6ccfffSVineet GuptaEND(EV_TLBProtV) 1521f6ccfffSVineet Gupta 1531f6ccfffSVineet Gupta; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 1541f6ccfffSVineet Gupta; need to call do_page_fault(). 1551f6ccfffSVineet Gupta; ECR in pt_regs provides whether access was R/W/X 1561f6ccfffSVineet Gupta 1571f6ccfffSVineet Gupta.global call_do_page_fault 1581f6ccfffSVineet Gupta.set call_do_page_fault, EV_TLBProtV 1591f6ccfffSVineet Gupta 1601f6ccfffSVineet Gupta;############# Common Handlers for ARCompact and ARCv2 ############## 1611f6ccfffSVineet Gupta 1621f6ccfffSVineet Gupta#include "entry.S" 1631f6ccfffSVineet Gupta 1641f6ccfffSVineet Gupta;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 1651f6ccfffSVineet Gupta; 1661f6ccfffSVineet Gupta; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 1671f6ccfffSVineet Gupta; IRQ shd definitely not happen between now and rtie 1681f6ccfffSVineet Gupta; All 2 entry points to here already disable interrupts 1691f6ccfffSVineet Gupta 1701f6ccfffSVineet Gupta.Lrestore_regs: 1711f6ccfffSVineet Gupta 1721f6ccfffSVineet Gupta ld r0, [sp, PT_status32] ; U/K mode at time of entry 1731f6ccfffSVineet Gupta lr r10, [AUX_IRQ_ACT] 1741f6ccfffSVineet Gupta 1751f6ccfffSVineet Gupta bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE 1761f6ccfffSVineet Gupta breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 1771f6ccfffSVineet Gupta 1781f6ccfffSVineet Gupta;####### Return from Intr ####### 1791f6ccfffSVineet Gupta 1801f6ccfffSVineet Guptadebug_marker_l1: 1814255b07fSVineet Gupta bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 1824255b07fSVineet Gupta 1834255b07fSVineet Gupta.Lisr_ret_fast_path: 1841f6ccfffSVineet Gupta ; Handle special case #1: (Entry via Exception, Return via IRQ) 1851f6ccfffSVineet Gupta ; 1861f6ccfffSVineet Gupta ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 1871f6ccfffSVineet Gupta ; task now returning to U mode (riding the Intr) 1881f6ccfffSVineet Gupta ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 1891f6ccfffSVineet Gupta ; won't be switched to correct U mode value (from AUX_SP) 1901f6ccfffSVineet Gupta ; So force AUX_IRQ_ACT.U for such a case 1911f6ccfffSVineet Gupta 1921f6ccfffSVineet Gupta btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 1931f6ccfffSVineet Gupta bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 1941f6ccfffSVineet Gupta sr r11, [AUX_IRQ_ACT] 1951f6ccfffSVineet Gupta 1961f6ccfffSVineet Gupta INTERRUPT_EPILOGUE irq 1971f6ccfffSVineet Gupta rtie 1981f6ccfffSVineet Gupta 1991f6ccfffSVineet Gupta;####### Return from Exception / pure kernel mode ####### 2001f6ccfffSVineet Gupta 2011f6ccfffSVineet Gupta.Lexcept_ret: ; Expects r0 has PT_status32 2021f6ccfffSVineet Gupta 2031f6ccfffSVineet Guptadebug_marker_syscall: 2041f6ccfffSVineet Gupta EXCEPTION_EPILOGUE 2051f6ccfffSVineet Gupta rtie 2061f6ccfffSVineet Gupta 2074255b07fSVineet Gupta;####### Return from Intr to insn in delay slot ####### 2084255b07fSVineet Gupta 2094255b07fSVineet Gupta; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 2104255b07fSVineet Gupta; 2114255b07fSVineet Gupta; Intr returning to a Delay Slot (DS) insn 2124255b07fSVineet Gupta; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 2134255b07fSVineet Gupta; entry was via Exception in DS which got preempted in kernel). 2144255b07fSVineet Gupta; 215cbfe74a7SVineet Gupta; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround 216cbfe74a7SVineet Gupta; 217cbfe74a7SVineet Gupta; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline 218cbfe74a7SVineet Gupta; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly 219cbfe74a7SVineet Gupta 2204255b07fSVineet Gupta.Lintr_ret_to_delay_slot: 2214255b07fSVineet Guptadebug_marker_ds: 2224255b07fSVineet Gupta 2234255b07fSVineet Gupta ld r2, [@intr_to_DE_cnt] 2244255b07fSVineet Gupta add r2, r2, 1 2254255b07fSVineet Gupta st r2, [@intr_to_DE_cnt] 2264255b07fSVineet Gupta 2274255b07fSVineet Gupta ld r2, [sp, PT_ret] 2284255b07fSVineet Gupta ld r3, [sp, PT_status32] 2294255b07fSVineet Gupta 230cbfe74a7SVineet Gupta ; STAT32 for Int return created from scratch 231cbfe74a7SVineet Gupta ; (No delay dlot, disable Further intr in trampoline) 232cbfe74a7SVineet Gupta 2334255b07fSVineet Gupta bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK 2344255b07fSVineet Gupta st r0, [sp, PT_status32] 2354255b07fSVineet Gupta 2364255b07fSVineet Gupta mov r1, .Lintr_ret_to_delay_slot_2 2374255b07fSVineet Gupta st r1, [sp, PT_ret] 2384255b07fSVineet Gupta 239cbfe74a7SVineet Gupta ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots 2404255b07fSVineet Gupta st r2, [sp, 0] 2414255b07fSVineet Gupta st r3, [sp, 4] 2424255b07fSVineet Gupta 2434255b07fSVineet Gupta b .Lisr_ret_fast_path 2444255b07fSVineet Gupta 2454255b07fSVineet Gupta.Lintr_ret_to_delay_slot_2: 246cbfe74a7SVineet Gupta ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP 2474255b07fSVineet Gupta sub sp, sp, SZ_PT_REGS 2484255b07fSVineet Gupta st r9, [sp, -4] 2494255b07fSVineet Gupta 2504255b07fSVineet Gupta ld r9, [sp, 0] 2514255b07fSVineet Gupta sr r9, [eret] 2524255b07fSVineet Gupta 2534255b07fSVineet Gupta ld r9, [sp, 4] 2544255b07fSVineet Gupta sr r9, [erstatus] 2554255b07fSVineet Gupta 256cbfe74a7SVineet Gupta ; restore AUX_USER_SP if returning to U mode 257cbfe74a7SVineet Gupta bbit0 r9, STATUS_U_BIT, 1f 258cbfe74a7SVineet Gupta ld r9, [sp, PT_sp] 259cbfe74a7SVineet Gupta sr r9, [AUX_USER_SP] 260cbfe74a7SVineet Gupta 261cbfe74a7SVineet Gupta1: 2624255b07fSVineet Gupta ld r9, [sp, 8] 2634255b07fSVineet Gupta sr r9, [erbta] 2644255b07fSVineet Gupta 2654255b07fSVineet Gupta ld r9, [sp, -4] 2664255b07fSVineet Gupta add sp, sp, SZ_PT_REGS 267cbfe74a7SVineet Gupta 268cbfe74a7SVineet Gupta ; return from pure kernel mode to delay slot 2694255b07fSVineet Gupta rtie 2704255b07fSVineet Gupta 2711f6ccfffSVineet GuptaEND(ret_from_exception) 272