1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * vineetg: May 2011 9 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1. 10 * They are semantically the same although in different contexts 11 * VALID marks a TLB entry exists and it will only happen if PRESENT 12 * - Utilise some unused free bits to confine PTE flags to 12 bits 13 * This is a must for 4k pg-sz 14 * 15 * vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods 16 * -TLB Locking never really existed, except for initial specs 17 * -SILENT_xxx not needed for our port 18 * -Per my request, MMU V3 changes the layout of some of the bits 19 * to avoid a few shifts in TLB Miss handlers. 20 * 21 * vineetg: April 2010 22 * -PGD entry no longer contains any flags. If empty it is 0, otherwise has 23 * Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler 24 * 25 * vineetg: April 2010 26 * -Switched form 8:11:13 split for page table lookup to 11:8:13 27 * -this speeds up page table allocation itself as we now have to memset 1K 28 * instead of 8k per page table. 29 * -TODO: Right now page table alloc is 8K and rest 7K is unused 30 * need to optimise it 31 * 32 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 33 */ 34 35 #ifndef _ASM_ARC_PGTABLE_H 36 #define _ASM_ARC_PGTABLE_H 37 38 #include <asm/page.h> 39 #include <asm/mmu.h> 40 #include <asm-generic/pgtable-nopmd.h> 41 42 /************************************************************************** 43 * Page Table Flags 44 * 45 * ARC700 MMU only deals with softare managed TLB entries. 46 * Page Tables are purely for Linux VM's consumption and the bits below are 47 * suited to that (uniqueness). Hence some are not implemented in the TLB and 48 * some have different value in TLB. 49 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in 50 * seperate PD0 and PD1, which combined forms a translation entry) 51 * while for PTE perspective, they are 8 and 9 respectively 52 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos 53 * (saves some bit shift ops in TLB Miss hdlrs) 54 */ 55 56 #if (CONFIG_ARC_MMU_VER <= 2) 57 58 #define _PAGE_ACCESSED (1<<1) /* Page is accessed (S) */ 59 #define _PAGE_CACHEABLE (1<<2) /* Page is cached (H) */ 60 #define _PAGE_U_EXECUTE (1<<3) /* Page has user execute perm (H) */ 61 #define _PAGE_U_WRITE (1<<4) /* Page has user write perm (H) */ 62 #define _PAGE_U_READ (1<<5) /* Page has user read perm (H) */ 63 #define _PAGE_K_EXECUTE (1<<6) /* Page has kernel execute perm (H) */ 64 #define _PAGE_K_WRITE (1<<7) /* Page has kernel write perm (H) */ 65 #define _PAGE_K_READ (1<<8) /* Page has kernel perm (H) */ 66 #define _PAGE_GLOBAL (1<<9) /* Page is global (H) */ 67 #define _PAGE_MODIFIED (1<<10) /* Page modified (dirty) (S) */ 68 #define _PAGE_FILE (1<<10) /* page cache/ swap (S) */ 69 #define _PAGE_PRESENT (1<<11) /* TLB entry is valid (H) */ 70 71 #else 72 73 /* PD1 */ 74 #define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */ 75 #define _PAGE_U_EXECUTE (1<<1) /* Page has user execute perm (H) */ 76 #define _PAGE_U_WRITE (1<<2) /* Page has user write perm (H) */ 77 #define _PAGE_U_READ (1<<3) /* Page has user read perm (H) */ 78 #define _PAGE_K_EXECUTE (1<<4) /* Page has kernel execute perm (H) */ 79 #define _PAGE_K_WRITE (1<<5) /* Page has kernel write perm (H) */ 80 #define _PAGE_K_READ (1<<6) /* Page has kernel perm (H) */ 81 #define _PAGE_ACCESSED (1<<7) /* Page is accessed (S) */ 82 83 /* PD0 */ 84 #define _PAGE_GLOBAL (1<<8) /* Page is global (H) */ 85 #define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */ 86 #define _PAGE_SHARED_CODE (1<<10) /* Shared Code page with cmn vaddr 87 usable for shared TLB entries (H) */ 88 89 #define _PAGE_MODIFIED (1<<11) /* Page modified (dirty) (S) */ 90 #define _PAGE_FILE (1<<12) /* page cache/ swap (S) */ 91 92 #define _PAGE_SHARED_CODE_H (1<<31) /* Hardware counterpart of above */ 93 #endif 94 95 /* Kernel allowed all permissions for all pages */ 96 #define _K_PAGE_PERMS (_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ | \ 97 _PAGE_GLOBAL | _PAGE_PRESENT) 98 99 #ifdef CONFIG_ARC_CACHE_PAGES 100 #define _PAGE_DEF_CACHEABLE _PAGE_CACHEABLE 101 #else 102 #define _PAGE_DEF_CACHEABLE (0) 103 #endif 104 105 /* Helper for every "user" page 106 * -kernel can R/W/X 107 * -by default cached, unless config otherwise 108 * -present in memory 109 */ 110 #define ___DEF (_PAGE_PRESENT | _PAGE_DEF_CACHEABLE) 111 112 #define _PAGE_READ (_PAGE_U_READ | _PAGE_K_READ) 113 #define _PAGE_WRITE (_PAGE_U_WRITE | _PAGE_K_WRITE) 114 #define _PAGE_EXECUTE (_PAGE_U_EXECUTE | _PAGE_K_EXECUTE) 115 116 /* Set of bits not changed in pte_modify */ 117 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) 118 119 /* More Abbrevaited helpers */ 120 #define PAGE_U_NONE __pgprot(___DEF) 121 #define PAGE_U_R __pgprot(___DEF | _PAGE_READ) 122 #define PAGE_U_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE) 123 #define PAGE_U_X_R __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE) 124 #define PAGE_U_X_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE | \ 125 _PAGE_EXECUTE) 126 127 #define PAGE_SHARED PAGE_U_W_R 128 129 /* While kernel runs out of unstrslated space, vmalloc/modules use a chunk of 130 * kernel vaddr space - visible in all addr spaces, but kernel mode only 131 * Thus Global, all-kernel-access, no-user-access, cached 132 */ 133 #define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_DEF_CACHEABLE) 134 135 /* ioremap */ 136 #define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS) 137 138 /* Masks for actual TLB "PD"s */ 139 #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT) 140 #define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \ 141 _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \ 142 _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ) 143 144 /************************************************************************** 145 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific) 146 * 147 * Certain cases have 1:1 mapping 148 * e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED 149 * which directly corresponds to PAGE_U_X_R 150 * 151 * Other rules which cause the divergence from 1:1 mapping 152 * 153 * 1. Although ARC700 can do exclusive execute/write protection (meaning R 154 * can be tracked independet of X/W unlike some other CPUs), still to 155 * keep things consistent with other archs: 156 * -Write implies Read: W => R 157 * -Execute implies Read: X => R 158 * 159 * 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W 160 * This is to enable COW mechanism 161 */ 162 /* xwr */ 163 #define __P000 PAGE_U_NONE 164 #define __P001 PAGE_U_R 165 #define __P010 PAGE_U_R /* Pvt-W => !W */ 166 #define __P011 PAGE_U_R /* Pvt-W => !W */ 167 #define __P100 PAGE_U_X_R /* X => R */ 168 #define __P101 PAGE_U_X_R 169 #define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */ 170 #define __P111 PAGE_U_X_R /* Pvt-W => !W */ 171 172 #define __S000 PAGE_U_NONE 173 #define __S001 PAGE_U_R 174 #define __S010 PAGE_U_W_R /* W => R */ 175 #define __S011 PAGE_U_W_R 176 #define __S100 PAGE_U_X_R /* X => R */ 177 #define __S101 PAGE_U_X_R 178 #define __S110 PAGE_U_X_W_R /* X => R */ 179 #define __S111 PAGE_U_X_W_R 180 181 /**************************************************************** 182 * Page Table Lookup split 183 * 184 * We implement 2 tier paging and since this is all software, we are free 185 * to customize the span of a PGD / PTE entry to suit us 186 * 187 * 32 bit virtual address 188 * ------------------------------------------------------- 189 * | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE | 190 * ------------------------------------------------------- 191 * | | | 192 * | | --> off in page frame 193 * | | 194 * | ---> index into Page Table 195 * | 196 * ----> index into Page Directory 197 */ 198 199 #define BITS_IN_PAGE PAGE_SHIFT 200 201 /* Optimal Sizing of Pg Tbl - based on MMU page size */ 202 #if defined(CONFIG_ARC_PAGE_SIZE_8K) 203 #define BITS_FOR_PTE 8 204 #elif defined(CONFIG_ARC_PAGE_SIZE_16K) 205 #define BITS_FOR_PTE 8 206 #elif defined(CONFIG_ARC_PAGE_SIZE_4K) 207 #define BITS_FOR_PTE 9 208 #endif 209 210 #define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE) 211 212 #define PGDIR_SHIFT (BITS_FOR_PTE + BITS_IN_PAGE) 213 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */ 214 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 215 216 #ifdef __ASSEMBLY__ 217 #define PTRS_PER_PTE (1 << BITS_FOR_PTE) 218 #define PTRS_PER_PGD (1 << BITS_FOR_PGD) 219 #else 220 #define PTRS_PER_PTE (1UL << BITS_FOR_PTE) 221 #define PTRS_PER_PGD (1UL << BITS_FOR_PGD) 222 #endif 223 /* 224 * Number of entries a user land program use. 225 * TASK_SIZE is the maximum vaddr that can be used by a userland program. 226 */ 227 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 228 229 /* 230 * No special requirements for lowest virtual address we permit any user space 231 * mapping to be mapped at. 232 */ 233 #define FIRST_USER_ADDRESS 0 234 235 236 /**************************************************************** 237 * Bucket load of VM Helpers 238 */ 239 240 #ifndef __ASSEMBLY__ 241 242 #define pte_ERROR(e) \ 243 pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 244 #define pgd_ERROR(e) \ 245 pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 246 247 /* the zero page used for uninitialized and anonymous pages */ 248 extern char empty_zero_page[PAGE_SIZE]; 249 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 250 251 #define pte_unmap(pte) do { } while (0) 252 #define pte_unmap_nested(pte) do { } while (0) 253 254 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) 255 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 256 257 /* find the page descriptor of the Page Tbl ref by PMD entry */ 258 #define pmd_page(pmd) virt_to_page(pmd_val(pmd) & PAGE_MASK) 259 260 /* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */ 261 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK) 262 263 /* In a 2 level sys, setup the PGD entry with PTE value */ 264 static inline void pmd_set(pmd_t *pmdp, pte_t *ptep) 265 { 266 pmd_val(*pmdp) = (unsigned long)ptep; 267 } 268 269 #define pte_none(x) (!pte_val(x)) 270 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 271 #define pte_clear(mm, addr, ptep) set_pte_at(mm, addr, ptep, __pte(0)) 272 273 #define pmd_none(x) (!pmd_val(x)) 274 #define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK)) 275 #define pmd_present(x) (pmd_val(x)) 276 #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) 277 278 #define pte_page(x) (mem_map + \ 279 (unsigned long)(((pte_val(x) - PAGE_OFFSET) >> PAGE_SHIFT))) 280 281 #define mk_pte(page, pgprot) \ 282 ({ \ 283 pte_t pte; \ 284 pte_val(pte) = __pa(page_address(page)) + pgprot_val(pgprot); \ 285 pte; \ 286 }) 287 288 /* TBD: Non linear mapping stuff */ 289 static inline int pte_file(pte_t pte) 290 { 291 return pte_val(pte) & _PAGE_FILE; 292 } 293 294 #define PTE_FILE_MAX_BITS 30 295 #define pgoff_to_pte(x) __pte(x) 296 #define pte_to_pgoff(x) (pte_val(x) >> 2) 297 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 298 #define pfn_pte(pfn, prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) 299 #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 300 301 /* 302 * pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system) 303 * and returns ptr to PTE entry corresponding to @addr 304 */ 305 #define pte_offset(dir, addr) ((pte_t *)(pmd_page_vaddr(*dir)) +\ 306 __pte_index(addr)) 307 308 /* No mapping of Page Tables in high mem etc, so following same as above */ 309 #define pte_offset_kernel(dir, addr) pte_offset(dir, addr) 310 #define pte_offset_map(dir, addr) pte_offset(dir, addr) 311 312 /* Zoo of pte_xxx function */ 313 #define pte_read(pte) (pte_val(pte) & _PAGE_READ) 314 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE) 315 #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED) 316 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) 317 #define pte_special(pte) (0) 318 319 #define PTE_BIT_FUNC(fn, op) \ 320 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } 321 322 PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE)); 323 PTE_BIT_FUNC(mkwrite, |= (_PAGE_WRITE)); 324 PTE_BIT_FUNC(mkclean, &= ~(_PAGE_MODIFIED)); 325 PTE_BIT_FUNC(mkdirty, |= (_PAGE_MODIFIED)); 326 PTE_BIT_FUNC(mkold, &= ~(_PAGE_ACCESSED)); 327 PTE_BIT_FUNC(mkyoung, |= (_PAGE_ACCESSED)); 328 PTE_BIT_FUNC(exprotect, &= ~(_PAGE_EXECUTE)); 329 PTE_BIT_FUNC(mkexec, |= (_PAGE_EXECUTE)); 330 331 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 332 333 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 334 { 335 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 336 } 337 338 /* Macro to mark a page protection as uncacheable */ 339 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE)) 340 341 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 342 pte_t *ptep, pte_t pteval) 343 { 344 set_pte(ptep, pteval); 345 } 346 347 /* 348 * All kernel related VM pages are in init's mm. 349 */ 350 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 351 #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) 352 #define pgd_offset(mm, addr) (((mm)->pgd)+pgd_index(addr)) 353 354 /* 355 * Macro to quickly access the PGD entry, utlising the fact that some 356 * arch may cache the pointer to Page Directory of "current" task 357 * in a MMU register 358 * 359 * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply 360 * becomes read a register 361 * 362 * ********CAUTION*******: 363 * Kernel code might be dealing with some mm_struct of NON "current" 364 * Thus use this macro only when you are certain that "current" is current 365 * e.g. when dealing with signal frame setup code etc 366 */ 367 #ifndef CONFIG_SMP 368 #define pgd_offset_fast(mm, addr) \ 369 ({ \ 370 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \ 371 pgd_base + pgd_index(addr); \ 372 }) 373 #else 374 #define pgd_offset_fast(mm, addr) pgd_offset(mm, addr) 375 #endif 376 377 extern void paging_init(void); 378 extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE); 379 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 380 pte_t *ptep); 381 382 /* Encode swap {type,off} tuple into PTE 383 * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that 384 * both PAGE_FILE and PAGE_PRESENT are zero in a PTE holding swap "identifier" 385 */ 386 #define __swp_entry(type, off) ((swp_entry_t) { \ 387 ((type) & 0x1f) | ((off) << 13) }) 388 389 /* Decode a PTE containing swap "identifier "into constituents */ 390 #define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f) 391 #define __swp_offset(pte_lookalike) ((pte_lookalike).val << 13) 392 393 /* NOPs, to keep generic kernel happy */ 394 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 395 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 396 397 #define kern_addr_valid(addr) (1) 398 399 /* 400 * remap a physical page `pfn' of size `size' with page protection `prot' 401 * into virtual address `from' 402 */ 403 #include <asm-generic/pgtable.h> 404 405 /* to cope with aliasing VIPT cache */ 406 #define HAVE_ARCH_UNMAPPED_AREA 407 408 /* 409 * No page table caches to initialise 410 */ 411 #define pgtable_cache_init() do { } while (0) 412 413 #endif /* __ASSEMBLY__ */ 414 415 #endif 416