1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_MMU_H 10 #define _ASM_ARC_MMU_H 11 12 #ifndef __ASSEMBLY__ 13 #include <linux/threads.h> /* NR_CPUS */ 14 #endif 15 16 #if defined(CONFIG_ARC_MMU_V1) 17 #define CONFIG_ARC_MMU_VER 1 18 #elif defined(CONFIG_ARC_MMU_V2) 19 #define CONFIG_ARC_MMU_VER 2 20 #elif defined(CONFIG_ARC_MMU_V3) 21 #define CONFIG_ARC_MMU_VER 3 22 #elif defined(CONFIG_ARC_MMU_V4) 23 #define CONFIG_ARC_MMU_VER 4 24 #endif 25 26 /* MMU Management regs */ 27 #define ARC_REG_MMU_BCR 0x06f 28 #if (CONFIG_ARC_MMU_VER < 4) 29 #define ARC_REG_TLBPD0 0x405 30 #define ARC_REG_TLBPD1 0x406 31 #define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */ 32 #define ARC_REG_TLBINDEX 0x407 33 #define ARC_REG_TLBCOMMAND 0x408 34 #define ARC_REG_PID 0x409 35 #define ARC_REG_SCRATCH_DATA0 0x418 36 #else 37 #define ARC_REG_TLBPD0 0x460 38 #define ARC_REG_TLBPD1 0x461 39 #define ARC_REG_TLBPD1HI 0x463 40 #define ARC_REG_TLBINDEX 0x464 41 #define ARC_REG_TLBCOMMAND 0x465 42 #define ARC_REG_PID 0x468 43 #define ARC_REG_SCRATCH_DATA0 0x46c 44 #endif 45 46 /* Bits in MMU PID register */ 47 #define __TLB_ENABLE (1 << 31) 48 #define __PROG_ENABLE (1 << 30) 49 #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) 50 51 /* Error code if probe fails */ 52 #define TLB_LKUP_ERR 0x80000000 53 54 #if (CONFIG_ARC_MMU_VER < 4) 55 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) 56 #else 57 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) 58 #endif 59 60 /* TLB Commands */ 61 #define TLBWrite 0x1 62 #define TLBRead 0x2 63 #define TLBGetIndex 0x3 64 #define TLBProbe 0x4 65 66 #if (CONFIG_ARC_MMU_VER >= 2) 67 #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ 68 #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ 69 #endif 70 71 #if (CONFIG_ARC_MMU_VER >= 4) 72 #define TLBInsertEntry 0x7 73 #define TLBDeleteEntry 0x8 74 #endif 75 76 #ifndef __ASSEMBLY__ 77 78 typedef struct { 79 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ 80 } mm_context_t; 81 82 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA 83 void tlb_paranoid_check(unsigned int mm_asid, unsigned long address); 84 #else 85 #define tlb_paranoid_check(a, b) 86 #endif 87 88 void arc_mmu_init(void); 89 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); 90 void read_decode_mmu_bcr(void); 91 92 static inline int is_pae40_enabled(void) 93 { 94 return IS_ENABLED(CONFIG_ARC_HAS_PAE40); 95 } 96 97 extern int pae40_exist_but_not_enab(void); 98 99 #endif /* !__ASSEMBLY__ */ 100 101 #endif 102