1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_IO_H 10 #define _ASM_ARC_IO_H 11 12 #include <linux/types.h> 13 #include <asm/byteorder.h> 14 #include <asm/page.h> 15 16 extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size); 17 extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, 18 unsigned long flags); 19 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) 20 { 21 return (void __iomem *)port; 22 } 23 24 static inline void ioport_unmap(void __iomem *addr) 25 { 26 } 27 28 extern void iounmap(const void __iomem *addr); 29 30 #define ioremap_nocache(phy, sz) ioremap(phy, sz) 31 #define ioremap_wc(phy, sz) ioremap(phy, sz) 32 #define ioremap_wt(phy, sz) ioremap(phy, sz) 33 34 /* Change struct page to physical address */ 35 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 36 37 #define __raw_readb __raw_readb 38 static inline u8 __raw_readb(const volatile void __iomem *addr) 39 { 40 u8 b; 41 42 __asm__ __volatile__( 43 " ldb%U1 %0, %1 \n" 44 : "=r" (b) 45 : "m" (*(volatile u8 __force *)addr) 46 : "memory"); 47 48 return b; 49 } 50 51 #define __raw_readw __raw_readw 52 static inline u16 __raw_readw(const volatile void __iomem *addr) 53 { 54 u16 s; 55 56 __asm__ __volatile__( 57 " ldw%U1 %0, %1 \n" 58 : "=r" (s) 59 : "m" (*(volatile u16 __force *)addr) 60 : "memory"); 61 62 return s; 63 } 64 65 #define __raw_readl __raw_readl 66 static inline u32 __raw_readl(const volatile void __iomem *addr) 67 { 68 u32 w; 69 70 __asm__ __volatile__( 71 " ld%U1 %0, %1 \n" 72 : "=r" (w) 73 : "m" (*(volatile u32 __force *)addr) 74 : "memory"); 75 76 return w; 77 } 78 79 #define __raw_writeb __raw_writeb 80 static inline void __raw_writeb(u8 b, volatile void __iomem *addr) 81 { 82 __asm__ __volatile__( 83 " stb%U1 %0, %1 \n" 84 : 85 : "r" (b), "m" (*(volatile u8 __force *)addr) 86 : "memory"); 87 } 88 89 #define __raw_writew __raw_writew 90 static inline void __raw_writew(u16 s, volatile void __iomem *addr) 91 { 92 __asm__ __volatile__( 93 " stw%U1 %0, %1 \n" 94 : 95 : "r" (s), "m" (*(volatile u16 __force *)addr) 96 : "memory"); 97 98 } 99 100 #define __raw_writel __raw_writel 101 static inline void __raw_writel(u32 w, volatile void __iomem *addr) 102 { 103 __asm__ __volatile__( 104 " st%U1 %0, %1 \n" 105 : 106 : "r" (w), "m" (*(volatile u32 __force *)addr) 107 : "memory"); 108 109 } 110 111 #ifdef CONFIG_ISA_ARCV2 112 #include <asm/barrier.h> 113 #define __iormb() rmb() 114 #define __iowmb() wmb() 115 #else 116 #define __iormb() do { } while (0) 117 #define __iowmb() do { } while (0) 118 #endif 119 120 /* 121 * MMIO can also get buffered/optimized in micro-arch, so barriers needed 122 * Based on ARM model for the typical use case 123 * 124 * <ST [DMA buffer]> 125 * <writel MMIO "go" reg> 126 * or: 127 * <readl MMIO "status" reg> 128 * <LD [DMA buffer]> 129 * 130 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com 131 */ 132 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 133 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 134 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 135 136 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) 137 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) 138 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) 139 140 /* 141 * Relaxed API for drivers which can handle barrier ordering themselves 142 * 143 * Also these are defined to perform little endian accesses. 144 * To provide the typical device register semantics of fixed endian, 145 * swap the byte order for Big Endian 146 * 147 * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de 148 */ 149 #define readb_relaxed(c) __raw_readb(c) 150 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ 151 __raw_readw(c)); __r; }) 152 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ 153 __raw_readl(c)); __r; }) 154 155 #define writeb_relaxed(v,c) __raw_writeb(v,c) 156 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) 157 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) 158 159 #include <asm-generic/io.h> 160 161 #endif /* _ASM_ARC_IO_H */ 162