1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __ARC_ASM_CACHE_H 10 #define __ARC_ASM_CACHE_H 11 12 /* In case $$ not config, setup a dummy number for rest of kernel */ 13 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT 14 #define L1_CACHE_SHIFT 6 15 #else 16 #define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT 17 #endif 18 19 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 20 #define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) 21 22 /* 23 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF) 24 * Ideal for wiring memory mapped peripherals as we don't need to do 25 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers 26 */ 27 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000 28 29 #ifndef __ASSEMBLY__ 30 31 /* Uncached access macros */ 32 #define arc_read_uncached_32(ptr) \ 33 ({ \ 34 unsigned int __ret; \ 35 __asm__ __volatile__( \ 36 " ld.di %0, [%1] \n" \ 37 : "=r"(__ret) \ 38 : "r"(ptr)); \ 39 __ret; \ 40 }) 41 42 #define arc_write_uncached_32(ptr, data)\ 43 ({ \ 44 __asm__ __volatile__( \ 45 " st.di %0, [%1] \n" \ 46 : \ 47 : "r"(data), "r"(ptr)); \ 48 }) 49 50 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 51 52 extern void arc_cache_init(void); 53 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); 54 extern void read_decode_cache_bcr(void); 55 56 extern int ioc_enable; 57 extern unsigned long perip_base, perip_end; 58 59 #endif /* !__ASSEMBLY__ */ 60 61 /* Instruction cache related Auxiliary registers */ 62 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ 63 #define ARC_REG_IC_IVIC 0x10 64 #define ARC_REG_IC_CTRL 0x11 65 #define ARC_REG_IC_IVIR 0x16 66 #define ARC_REG_IC_ENDR 0x17 67 #define ARC_REG_IC_IVIL 0x19 68 #define ARC_REG_IC_PTAG 0x1E 69 #define ARC_REG_IC_PTAG_HI 0x1F 70 71 /* Bit val in IC_CTRL */ 72 #define IC_CTRL_DIS 0x1 73 74 /* Data cache related Auxiliary registers */ 75 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */ 76 #define ARC_REG_DC_IVDC 0x47 77 #define ARC_REG_DC_CTRL 0x48 78 #define ARC_REG_DC_IVDL 0x4A 79 #define ARC_REG_DC_FLSH 0x4B 80 #define ARC_REG_DC_FLDL 0x4C 81 #define ARC_REG_DC_STARTR 0x4D 82 #define ARC_REG_DC_ENDR 0x4E 83 #define ARC_REG_DC_PTAG 0x5C 84 #define ARC_REG_DC_PTAG_HI 0x5F 85 86 /* Bit val in DC_CTRL */ 87 #define DC_CTRL_DIS 0x001 88 #define DC_CTRL_INV_MODE_FLUSH 0x040 89 #define DC_CTRL_FLUSH_STATUS 0x100 90 #define DC_CTRL_RGN_OP_INV 0x200 91 #define DC_CTRL_RGN_OP_MSK 0x200 92 93 /*System-level cache (L2 cache) related Auxiliary registers */ 94 #define ARC_REG_SLC_CFG 0x901 95 #define ARC_REG_SLC_CTRL 0x903 96 #define ARC_REG_SLC_FLUSH 0x904 97 #define ARC_REG_SLC_INVALIDATE 0x905 98 #define ARC_REG_SLC_RGN_START 0x914 99 #define ARC_REG_SLC_RGN_END 0x916 100 101 /* Bit val in SLC_CONTROL */ 102 #define SLC_CTRL_DIS 0x001 103 #define SLC_CTRL_IM 0x040 104 #define SLC_CTRL_BUSY 0x100 105 #define SLC_CTRL_RGN_OP_INV 0x200 106 107 /* IO coherency related Auxiliary registers */ 108 #define ARC_REG_IO_COH_ENABLE 0x500 109 #define ARC_REG_IO_COH_PARTIAL 0x501 110 #define ARC_REG_IO_COH_AP0_BASE 0x508 111 #define ARC_REG_IO_COH_AP0_SIZE 0x509 112 113 #endif /* _ASM_CACHE_H */ 114